modern academy for engineering and technology in maadi

CHAPTER - 2

INTRODUCTION TO

CMOS CIRCUIT

Samir kamal Spring 2018

1- MOS transistor construction.

2- MOS transistor conduction characteristics.

3- MOS transistor switches.

4- CMOS logic circuits (Inverter, NAND, NOR and compound

gates).

5- Circuit and system representations.

2.1 CHAPTER OBJECTIVES

Understand the basic principles of the following:


2.3 MOS TRANSISTORS CONSTRUCTION

- The MOS technology provides two types of transistors or

devices: an n-type transistor (nMOS) and a p-type

transistor (pMOS).

- A Metal Oxide-Silicon (MOS) structure is created by

superimposing several layers of conducting, insulating,

and transistor-forming materials to create a sandwich-like

structure.


MOS Tr.s CONSTRUCTION-Cont-1

- Typical physical structures for the types of MOS transistors

are shown in Fig. 2.1.

- These structures are created by a series of chemical

processing steps (see Ch-4)


(a) n-MOS transistor

Fig. 2.1 Physical structure of MOS Transistors and their schematic icons.



(b) p-MOS transistor

Fig. 2.1 Physical structure of MOS Transistors and their schematic icons.



nMOS pMOS Fig. 1 MOS Transistor Symbols



- For n-transistor, the structure, which is constructed by

using the chemical process, consists of a section of:

a- p-type silicon (called substrate or positive substrate).

b- Two areas negatively diffused (doped) silicon that is

rich in electrons n-diffusion [Drain and Source].

c- The area separating the n regions is capped with a

sandwitch consisting of silicon dioxide (an insulator)

and a conducting electrode (polycrystalline silicon or -

poly) called the gate.



Fig. 2.2a nMOS Transistor structure

[4] MOS Tr.s CONSTRUCTION-Cont-6


Another characterization for nMOS transistors structure

Fig. a nMOS Transistor structure




- Similarly, for the p-transistor the structure consists of a

section of n-type (substrate) separating two p-type

(rich in holes) areas [Drain and Source] and the

same gate.

- The gate is a control input that affects the flow of

electrons (electrical current) between the drain and

source, which are physically equivalent.

- The name of D or S assignment depends on the

direction of current flow


Fig. 2.2b pMOS Transistor structure



2.4 MOS Tr.s CONDUCTION Ch/s

- In n MOS device: Majority carriers are electrons.

- In p MOS device: Majority carriers are holes.

- +ve / -ve voltage applied to the gate (w. r. t.

substrate) enhances the number of e’s / h’s in the channel and increases conductivity between S and D.


- Threshold voltage (Vt) defines the voltage at which

the MOS transistor begins to conduct.

MOS Tr.s CONDUCTION Ch/s-Cont-1

- For voltages less than Vt, the channel is cut off.

- Assuming that the S -to- the D voltage vds is fixed, the

relation between the transistor terminals voltages is

drawn in Fig. 2.3.


Fig. 2.3 Conduction characteristics for enhancement and depletion mode

MOS transistors (assuming fixed Vds).


ENHANCEMENT & DEPLETION MODE DEVICES

The devices that are normally CUT-OFF (i.e., non-conducting)

with zero gate bias are known as ENHANCEMENT mode

device, whereas

Those devices that conduct with zero gate bias are called

DEPLETION mode devices.

An n-channel devices with +ve vt are known as E-MOSFET

devices, and

those with -ve vt are known as D-MOSFET devices.

OR


This idea can be shown as:

- N-channel and P-channel MOSFET transistor

switching circuits are shown in Fig. 2.3 together with

input and output waveforms.

- With the enhancement devices illustrated, no channel

exists while the gate is at the same potential as the

source.

- Therefore, unlike JFETs, MOSFETs require no

external bias voltage to switch them off; i.e., they can

be operated from a single polarity supply.

MOSFET Switches idea:


For the N-channel MOSFET:

- The output is – VDD while no drain current is flowing.

- A -ve signal on the gate terminal switches the transistor

on, causing the output level to change to – (ID RD(on)).

- A +ve input pulse is necessary for switch-on.

- When the input signal becomes positive, ID flows, and the

output voltage drops from VDD –to- (ID RD(on)).

For the P-channel MOSFET:

MOSFET Switches idea - Cont-1


(a) N – channel enhancement MOSFET switch

Fig 2.4 (a) an n – channel enhancement MOSFET used as a

switch of until a positive Input voltage is applied to the gate.



(b) P – channel enhancement MOSFET switch

Fig 2.4 (b) A similar p – channel device requires a negative gate

voltage for switch – on



2.5 MOS TRANSISTORS SWITCHES

- The gate controls the current between S and D.

- Simplifying this to the extreme allows the MOS transistors

to be viewed as simple on/off switches.

- We will assume that a ‘1’ is a high voltage that is normally

set to a value between 1.5 and 15 volts and called

POWER (PWR) or VDD.

- The symbol ‘0’ will be assumed to be a low voltage that is

normally set to zero volts and called GROUND (GND) or

VSS.


- The power supplies (VDD and VSS) are the source of the

strongest ‘1’s and ‘0’s.

- The nMOS switch is shown in Fig. 2.5(a).

- The gate has been labeled with the signal s, the drain a,

and the source b.

- In an N-switch, the switch is closed or ‘ON’ if the drain

and the source are connected. This occurs when there

is a ‘1’ on the gate.

- The switch is open or ‘OFF’ if the drain and source are

disconnected. A ‘0’ on the gate ensures this condition.

MOS TRANSISTORS SWITCHES – Cont -1


Fig 2.5 n-MOS switch symbols and characteristics



- These conditions are summarized in Fig. 2.5(b).

- An N-switch is almost a perfect switch when a ‘0’ is to be

passed from an output to an input (say a to b in Fig. 2.5c).

- However the N-switch is an imperfect switch when passing

a ‘1’. In doing this, the ‘1’ voltage level is reduced a little.

These cases are shown in Fig. 2.5(c).



- The pMOS switch is shown in Fig. 2.5(d).

- The P-switch is ‘ON’ when there is a ‘0’ on ‘G’.

- The switch is ‘OFF’ when there is a ‘1’ on ‘G’.

- Figure 2.5(e) depicts these conditions.

- We denote this difference for a P-switch by including

the inversion bubble in the schematic icon notation.



Fig 2.5 p-MOS switch symbols and characteristics



- A P-switch is almost perfect for passing ‘1’ signals but

imperfect when passing ‘0’ signals. This is illustrated in

Fig 2.5(f).

Note that:

The pMOS and nMOS switches are ON and OFF for

complementary values of the gate signal.



Fig 2.5 n-MOS and p-MOS switch symbols and characteristics



- By combining an N-switch and a P-switch in parallel

(Fig. 2.6a), we obtain a switch in which ‘0’s and ‘1’s are

passed in an acceptable fashion (Fig. 2.6b).

- We term this a complementary switch, or C-switch.

- Note that:

In a circuit where only a ‘0' or a ‘1’ has to be passed,

the appropriate sub-switch (n or p) may be deleted,

reverting to a P-switch or an N-switch.



Fig 2.6 A complementally CMOS switches



- The complementary switch is also called a

transmission gate or pass gate (complementary).

Commonly used schematic icons for the

transmission gate are shown in Fig. 2.6(c).

Note that:

- The control input and its complement are routed to

all switches where necessary.

- The control signal is applied to the n-transistor and

the complement to the p-transistor.



2.6 CMOS LOGIC

2.6.1 The Inverter Table 2.1 Inverter Truth Table

Output Input

1 0

0 1

- From the table, we see that when there is a ‘0’ on the

input, there is a ‘1’ at the output.

- This suggests a P-switch connected from a ‘1’ source

(VDD) to the output, as shown in Fig 2.7(a).

- Table 2.1 shows the inverter truth table.


Fig 2.7 A CMOS inverter

Inverter – Cont - 1


- When there is a ‘1’ on the input, a ‘0’ has to be

connected to the output.

- This suggests the addition of an N-switch between the

output and a ‘0’ source (VSS).

- The completed circuit is shown in Fig 2.7(b).

- The transistor schematic and the schematic icon

forms for this are shown in Fig 2.7(c).



Note that:

- As the lower switch only has to pass a ‘0’ (the VSS -

source of ‘0’s is stronger than the output of the

inverter), only an N-switch is needed.

- By similar reasoning, the upper switch, which only has

to pass a ‘1,’ needs only a P-switch.

- In general, a fully complementary CMOS gate always

has an N-switch (pull-down) array to connect the

output to ‘0’ (VSS) and a P-switch (pull-up) array to

connect the output to ‘1’ (VDD).



2.6.2 Combinational Logic

- If two N-Switches are placed in series, the composite

switch constructed by this action is closed (or ON) if

both switches are closed (see Fig 2.8a).

- This yields an ‘AND’ function

- The corresponding structure for P-Switches is shown in

Fig. 2.8(b). This yields an ‘NOR’ function. The

composite switch is closed if both inputs are set to ‘0’.


Fig 2.8 Connection and behavior of series and parallel N- and P – switches

AND

NOR

Combinational Logic – Cont - 1


- By using combinations of these constructions, CMOS

combinational gates may be constructed.

- When two N-Switches are placed in parallel (Fig. 2.8c), the

composite switch is closed if either switch is closed (if either

input is a ‘1’). Thus an ‘OR’ function is created.

- The corresponding structure for P-Switches is shown in Fig.

2.8(d). In contrast to the previous case, if either input is a ‘0’

the switch is closed. Thus an ‘NAND’ function is created



Fig 2.8 Connection and behavior of series and parallel N- and P – switches

OR

NAND



As a conclusion

- N-Switches in series, yields an ‘AND’ function.

- N-Switches in Parallel, yields an ‘OR’ function.

- P-Switches in series, yields an ‘NOR’ function.

- p-Switches in Parallel, yields an ‘NAND’ function.



Logic Gates

OR-gate AND-gate XOR-gate


NOR-gate NAND-gate XNOR-gate

Logic Gates- cont


2.6.3 The NAND Gate

- Figure 2.9 Presents the logic symbol and the truth table of

a 2-input NAND gate.

Fig 2.9 Logic symbol and the truth table of a 2-input NAND gate.


Fig 2.10a A CMOS - NAND gate

- Figure 2.10a outlines the construction of a 2-input NAND

gate using the constructions introduced in Figs. 2.8(a & d).

NAND gate - Cont


Fig 2.8a & d Connection and behavior of series and parallel N-and P- switches

AND

NAND

NAND gate - Cont


- The pull-down tree is a series pair of N-switches with one

end connected to VSS and the other end connected to

the output.

- The output level of this structure, given the logic levels

on the control inputs, is shown in Table 2.3.

Table 2.3 NAND Gate Pull-Down Truth Table

NAND gate - Cont


- The pull-up tree is a parallel connection pair of P-switches

with one end connected to VDD and the other connected

to the NAND gate output.

- The level of the output of the combined switch is shown in

Table 2.4.

Table 2.4 NAND Gate Pull-Up Truth Table

NAND gate - Cont


- The circuit and logic schematics for the 2-input NAND

gate are shown in Figs. 2.10(b & c).

Fig 2.10b & c A CMOS - NAND gate

NAND gate - Cont


Fig 2.10d A CMOS - NAND gate

Larger input NAND gates:

They are constructed by placing one N-switch in series on

the n side and one P-switch in parallel for each additional

input to the gate (Fig. 2.10d).

NAND gate - Cont


2.6.4 The NOR Gate

- Figure 2.11 Presents the logic symbol and the truth table

of a 2-input NOR gate.

Fig 2.11 Logic symbol and the truth table of a 2-input NOR gate.


- For the NOR gate we will start with the conventional

Karnaugh map shown in Table 2.5.

- Here the ‘0’s and ‘1’s has been grouped together.

- The ‘0’ term (pull- down to ‘0’) dictates an OR structure

(A + B).

Table 2.5 Karnaugh for 2-i/p CMOS-NOR Gate

NOR gate - Cont


- Grouping the ‘1’s together results in a structure that

requires Ā . This is realized by the series p AND

structure.

- The complemented signals are obtained automatically

through the operation of the p-device.

B

Note that:

- The N -and- P switch combinations are the dual or

complement of the combination for the NAND gate.

NOR gate - Cont


Fig 2.12a A CMOS – NOR gate

- The 2-input NOR gate schematic is shown in Fig. 2.12(a).

- It is composed from sections introduced in Figs. 2.8(b & c).

NOR gate - Cont


Fig 2.8b & c Connection and behavior of series and parallel N-and P- switches

NOR gate - Cont

NOR

OR


- In contrast to the NAND gate, extra inputs are

accommodated in the NOR structure by adding N-

switches in parallel and P-switches in series with the

corresponding switch structures (Fig. 2.12d).

Fig 2.12d A CMOS – NOR gate

NOR gate - Cont


Fig 2.12 A CMOS – NOR gate

NOR gate - Cont


2.6.5 Compound Gates

A compound gate is formed by using a combination of

series – and parallel-switches structures

Example 2.1:

Derive the switch connection diagram for the function

F = )).().(( DCBA


Solution:

- The derivation of the switch connection diagram for this

function is shown in Fig. 2.13.

- The decomposition of this function and generation of

the diagram may be approached as follows.

- For the n-side, take the uninverted expression:

((A.B) + (CD))

Example-2 - Cont


- The AND expressions (A.B) and (C.D) may be

implemented by series connections of switches, as

shown in Fig. 2.13(a).

Example-2 - Cont

ANDs

Fig 2.13a & b CMOS compound gate for function F= )).().(( DCBA

OR


Example-2 - Cont

ANDs

Fig 2.13a & b CMOS compound gate for function F=

OR

- Now, taking these as sub-switches and ORing the

result requires the parallel connection of these

two structures. This is shown in Fig. 2.13(b).

)).().(( DCBA


Fig 2.13a & b CMOS compound gate for function F=

ANDs OR

Example-2 - Cont

)).().(( DCBA


- For the p-side we invert the expression used for the n-

expansion, yielding ((A + B). (C + D)).

- This suggests two OR structures, which are subsequently

connected in series, Figs. 2.13(c & d).

Fig 2.13c & d CMOS compound gate for function F= )).().(( DCBA

NAND NOR

Example-2 - Cont


Fig 2.13c & d CMOS compound gate for function F=

NAND NOR

Example-2 - Cont

)).().(( DCBA


- The final step requires connecting one end of the p-

structure to ‘1’ (VDD) and the other to the output.

Example-2 - Cont

- One side of the n- structure is connected to ‘0’ (VSS) and

the other to the output in common with the p-structure.

- This yields the final connection diagram (Fig. 2.13e).


Fig. 2.13e CMOS compound gate for function F= )).().(( DCBA

Example-2 - Cont


Fig. 2.13 CMOS compound gate for function F=

)).().(( DCBA

)).().(( DCBA

Example-2 - Cont


2.6.6 Multiplexers

- Complementary switches may be used to select

between a numbers of inputs, thus forming a

multiplexer function.

- Figure 2.16(a) shows a connection diagram for a 2-

input multiplexer.

Fig. 2.16a A 2 input CMOS multiplexer


Fig. 2.TT A pass gate symbol

Multiplexers - Cont

- As the switches have to pass ‘0’s and ‘1’s

equally well, complementary switches with n-

and p-transistors are used, Fig 2.TT


- The Karnaugh map for the structure in Fig. 2.16(a) is

shown in Table 2.6.

- It can be seen that this implements the function:

Output = A.S + B. S

Table 2.6 2-Input multiplexer Karnaugh map

Multiplexers - Cont


Table 2.7 Modified 2-input multiplexer Karnaugh map

Multiplexers - Cont

-Table 2.6 which shows the tow 2-input multiplexer

Karnaugh map can be modified as shown in table 2.7.

- In table 2.7:

S ….denotes the control signal and

F ….denotes the MUX output function.


Fig. 2.16c A 2 input CMOS multiplexer

- The multiplexer connection in terms of this symbol and

transistor symbols is shown in Fig. 2.16(c).

Multiplexers - Cont


Fig. 2.16 A 2 input CMOS multiplexer

Multiplexers - Cont


2.6.7 Memory—Latches and Registers

- We have now constructed enough CMOS structures to

enable a memory element to be constructed.

- A structure called a D latch using one 2-input multiplexer

and two inverters is shown in Fig. 2.17 (a).

- It consists of:

* a data input, D;

* a clock input, CLK and

* outputs Q and -Q.

Fig. 2.17a A CMOS positive –level– sensitive D latches


Fig. 2.TT A pass gate symbol

Memory - Latches - Cont


Fig. 2.17a & b A CMOS positive –level– sensitive D latches

When CLK= 1:

Q is set to D and -Q is set to – D, (Fig. 2.17b).



When CLK= 0:

- The input D is ignored and a feedback path around the

inverter pair is established (Fig. 2.17c).

- So, Q is still set to D and -Q is still set to –D.

Fig. 2.17a & c A CMOS positive –level– sensitive D latches



- This is known as a positive level-sensitive latch, i.e.,

the state of the output is dependent on the level of the

clock signal.

- By reversing the control connections to the multiplexer,

a negative level-sensitive latch may be constructed.



Fig. 2.17 A CMOS positive – level – sensitive D latches



- By combining two level-sensitive latches, one positive

sensitive and one negative sensitive, one may construct

an edge-triggered register as shown in Fig. 2.18(a).

- By convention, the first latch-stage is called the master

and the second is called the slave.

Fig. 2.18a A CMOS positive edge – triggered D registers


Master (- ve -latch) Slave (+ ve -latch)


While CLK is low:

- The master latch output (-QM) follows the D input while the

slave latch holds the previous value (Fig. 2.17b).

Fig. 2.17a & b A CMOS positive edge – triggered D registers



Fig. 2.18d A CMOS positive edge – triggered D registers



- The master latch stopped to sample the input and stores

the D value at the time of the clock transition.

- The slave latch opens, passing the stored master value

(-QM) to the output of the slave latch (Q).

- The D input is prevented from affecting the output

because the master is disconnected from the D input

(Fig. 2.18c).


When the clock transitions from 0 to 1:


Fig. 2.18a & c A CMOS positive edge – triggered D registers



Fig. 2.18d A CMOS positive edge – triggered D registers



- This device is a positive edge-triggered register.

- Also, it is called a D register or D flip-flop, because it

samples the input at an edge of the clock.

- By reversing the latch polarities, a negative edge-triggered

register may be constructed.

- Apart from RAM and ROM, these structures form the basis

of most CMOS storage elements.



Fig. 2.18 A CMOS positive edge – triggered D registers



2.7 CIRCUIT AND SYSTEM REPRESENTATIONS

- In the previous section we developed the basic functions

required in any digital system.

- Any complex digital system may he eventually broken

down into component gates and memory elements by

successively subdividing the system in a hierarchical

manner.

- This subdivision may be done manually or may be

mechanized.


- Highly automated techniques now exist for taking very

high level descriptions of system behavior and

converting the descriptions into a form that finally may

be used to specify how a chip is manufactured.

- To do this, a specific set of abstractions have been

developed to describe integrated electronic systems.

These are well shown in Fig. 2.19.

- In Fig. 2.19, three design domains are represented by

three radial lines:

* Behavioral domain,

* Structural domain, and

* Physical domain.

Cir. & Sys. Representations - Cont


Fig. 2.19 Digital domains and levels of abstraction.



- Each design domain may be specified at a variety of

levels of abstraction.

- Concentric circles around the center indicate the

various levels of abstraction that are common in

electronic design.

- From highest to lowest they might include:

• Architectural,

• Algorithmic,

• Module or functional block,

• Logical,

• Switch, and

• Circuit levels.



- Generally, a design is expressed in terms of the three

design domains, while the levels of abstraction that

are used vary depending on design style and circuit

complexity.

- The behavioral domain:

* This domain specifies what is the system does.

* The system can be described by:

+ Logic (Boolean) equations,

+ Truth tables, or

+ Algorithms.

- The three design domains (Behavioral, Structural, and

Physical) are defined as follows.



- The structural domain:

* This domain specifies how entities are connected

together to effect the prescribed behavior.


+ Logic diagrams,

+ Hardware Description Languages, such as:

SPICE, VHDL, Verilog or ELLA.

- Finally, the physical domain:

* This domain specifies how to actually build a structure

that has the required connectivity to implement the

pre-scribed behavior.


+ Circuit on the transistor level



physical domain Structural Domain Behavioral Domain

This domain specifies

how actually build the

system


how entities are

connected together


what the system does.

The system can be

described by:

- Circuit on the

transistor level

The system can be

described by:

- Logic diagrams

-Hardware description

languages

[VHDL, Verilog, ELLA

or SPICE]

The system can be

described by:

- Logic equations

- Truth tables

- Algorithms

Integrated electronic system can be described by:



Example 2.3:

For the addition importance in digital processing, we will

use this as an example to demonstrate these domains.

Design of a full adder



Behavioral Representation for n-bit adder

- An n-bit adder is constructed by cascading n 1-bit

adders.

- A 1-bit adder has two inputs, A and B; a carry input, C; a

carry output, Co; and a sum output, S.

- The truth table for an adder is shown in Table 2.8.

- The Boolean equations that implement this function are

as follows:



Table 2.8 Truth Table for 1-bit Binary Adder

S Co In C B A

0 0 0 0 0

1 0 1 0 0

1 0 0 1 0

0 1 1 1 0

1 0 0 0 1

0 1 1 0 1

0 1 0 1 1

1 1 1 1 1



Structural Representation for n-bit adder

- A graphical view of the adder hierarchy is shown in Fig.

2.20(a).

- The carry gate schematic is shown in Fig. 2.20(b) for

both logic and switch implementations.

- Note: In this implementation the pull-up tree is not the

exact complement of the pull-down tree.

- This form is used as it reduces the physical layout size



Fig. 2.20(a) Structural decomposition of a CMOS adder



Fig 2.20(b) Structural decomposition of a CMOS adder



Physical Representation for n-bit adder

- At the module level, the physical layout for the 4-bit

adder may be defined by a rectangle or polygon that

specifies the outer boundary of all the geometry for the

adder, a set of calls to sub-modules, and a collection of

ports.

- Each port corresponds to an I/O connection in the

structural description of the adder.

- The position, layer, name, and width are specified for

each port.



- This level of physical information may be represented

symbolically, as shown in Fig. 2.21, for the add4 and

add modules.

- The add module is constructed in a way that allows the

interconnection of the carry signal between adder bits

via vertical abutment.

- The inputs enter on the left, and the sum outputs are

available on the right.



Fig. 2.21 An abstract view of the physical representation of CMOS adder



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