WP2 Review MeetingMilano, Oct 05, 2011

04/22/23

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MODERN ENIAC WP2 Meeting

WP2 and Tasks review

Milano Agrate, 2011 Oct. 05

Meeting hosted by Micron

13:00 – 16:00 pm

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Overview D233

• Identification of most relevant process variations in planar bulk CMOS devices down to 32nm, parameter fluctuation effects based on hardware (STF2, IUNET, AMS)

– Evaluation of Vt, and Id matching performances of C032/028 RVT devices (STMicroelectronics)

– Main mechanisms affective threshold voltage variability investigated through sensitivity analysis (IUNET)

– Generation of Correlated Monte Carlo SPICE models (Austria Microsystems AG)

• Sources for PV in new device architectures, suitable for 22nm CMOS; major deltas in comparison to standard planar bulk CMOS (NXP, LETI & IMEP)

– Drain current variability and MOSFETs parameters correlations in planar FDSOI (LETI-CEA)

– FinFET mismatch in subthreshold region (IUNET& NXP)

3

Evaluation of Vt, b and Id matching performances of C032/028 RVT devices (STMicroelectronics)

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0.01 0.1 1 10

L_shrink (µm)

iAV

t_sh

rin

k(m

V.µ

m)

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0.01 0.1 1 10

L_shrink (µm)

iAV

t_sh

rin

k(m

V.µ

m)

NMOS

Vt_GMmax

Vt_cc_lin

Vt_cc_sat

Vt_GMmax

Vt_cc_lin

Vt_cc_sat

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L_shrink (µm)

iAV

t_sh

rin

k(m

V.µ

m)

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L_shrink (µm)

iAV

t_sh

rin

k(m

V.µ

m)

PMOS

Vt_GMmax

Vt_cc_lin

Vt_cc_sat

Vt_GMmax

Vt_cc_lin

Vt_cc_sat

Normalized Vt mismatch parameter for (a) NMOS and (b) PMOS, using Vt_Gmmax method in linear mode, Vt_cc in linear mode and Vt_cc in saturated

mode

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Ls (µm)

iA

(%.µ

m)

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Ls (µm)

iA

(%.µ

m)

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Ls (µm)

iA

(%.µ

m)

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Ls (µm)

iA

(%.µ

m)

AVt

A

2.8mV.µm for NMOS and

2.5mV.µm for PMOS

0.6%.µm for NMOS and 0.5%.µm for

PMOS

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Main mechanisms affecting threshold voltage variability investigated through TCAD sensitivity analysis (IUNET)

Doping profiles of 32 nm RVT NMOS (a) and PMOS (b) as obtained by STM after calibration with electrical characteristics

RDD => AVt=1.5 to 1.8mV.µm

LER =>

VthLER2

Vthy1

2

LER2

Vthy2

2

LER2 .

L

W

LLL

LER

WWerfe

WL

221

2 2

2

2

2

22

AVt=0.75 to 0.9 mV.µm

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Generation of Correlated Monte Carlo SPICE models (AMS AG)

Histograms for VTH HV NMOS, TCAD (blue, mean 413mV)vs. SPICE Monte Carlo (red,

mean 412mV)

HV NMOS Ron vs. VTHLIN results for TCAD (left) and measurement (right)

TCADSPICE

TCAD EXP

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Drain current variability and MOSFETs parameters correlations in planar FDSOI (LETI-CEA)

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1/sqrt(W.L) (µm-1)

σ(Δ

I SA

T/I

SA

T)

(%)

VG=VD=0.9V

nMOS

6nm SOI

TBOX=145nm

[8] - Bulk

LMIN=90nm

VD=1.2V

[9] - BulkL=60nm

VD=1.2V

[10] - BulkL=70nm

VD=1.2V

L=35nmW=80nm

Benchmark of the on state ID mismatch in FDSOI vs

bulk data

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100

0 0.2 0.4 0.6 0.8 1 1.2

VG (V)

σΔ

ID/I

D (

%)

Vd=0.9V

Vd=0.05V

nMOSL=35nmW=0.5µm

VD=0.9V

VD=50mVVT

6nm SOI

TBOX=145nm

σ(∆ID/ID) versus gate and drain voltages

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LEFF (nm)

RO

N (

Ω.µ

m) 6nm SOI

10nm SOI

12nm sSOI (nMOS)12nm sSOI (pMOS)

RSD

On-resistance RON for various effective lengths

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1/sqrt(W.L) (µm-1)

σ(Δ

I D/I D

) (%

)

nMOS

VD=50mV

W=0.5µm

(1)ON

D

DT

D

DON

D

DT

D

D

D

D R,I

ΔIV,

I

ΔI2

R,I

ΔI2

V,I

ΔI2

I

ΔI ... 2

0.9VVat σ G/IΔI LINLIN

ONDDDD R),/I(ΔTG/IΔI σ0.7VVVat σ I

TDD V),/I(Δσ I

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RSD (Ω.µm)

σ∆

RO

N (

Ω.µ

m)

6nm SOI

10nm SOI

12nm sSOI (nMOS)

12nm sSOI (pMOS)

30nm<LEFF<200nm

σ(∆ID/ID) comes from σ ∆VT and σ∆Ron plus

correlation(σ∆Ron related to

Rsd)

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FinFET mismatch in subthreshold region (IUNET)

S

SVS

VV

SS

VV

SS

thVDIth

thGSSthGSVth

,2

2

222

log

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V

th (

mV

)

WL-1/2 (m-1)

nFinFETW

fin=10nm

WL-1/2 (m-1)

pFinFETW

fin=10nm

A(ΔVth) equal to 2.91mVmm and 2.58mVmm for nFinFET

and pFinFET

LER for L>55nm

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25

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5

10

15

20

S/S

(%

)

Experimental Modeled with

L=3.5nm

nFinFET

0.4%m

(a)

(b)

S/S

(%

)

WL-1/2 (m-1)

Experimental Modeled with

L=3.5nm

pFinFET

0.34%m

0.01 0.1 10.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

LC

nFinFETpFinFET

(V

th,

S)

corr

ela

tion

Length (m)

Correlation between ΔVth and ΔS as a function of the gate length. For

L≥55 nm ΔVth and ΔS are uncorrelated, while for L<55nm a negative correlation is observed

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Main conclusions D233

• Vt, , and Id matching performances of typical C32/28 : good matching performances, AVt< 3mV.µm, and centered on 0.5%.µm for (STM).

• TCAD 32/28nm Vt variability simulations : major contribution from RDD central part of channel and from LER (IUNET).• A flow for implementing PV simulation results into statistical SPICE models has been presented (AMS). Gaussian distribution shows good agreement with the measurement statistics in terms of correlation. The extraction of covariance matrix and implementation into SPICE was shown.• Variability of drain current (ID) in 6nm thin undoped Silicon-On-Insulator (SOI) MOSFETs studied (LETI & IMEP). ID variations (σID) are found to be highly correlated with both threshold voltage (VT) and ON-state resistance (RON) fluctuations. Improving the access resistances (RSD) enables lowering the RON variability.• Drain current mismatch of FinFET devices in subthreshold, has been studied from both modeling and experimental points of view (IUNET & NXP). Critical length delimits two different mismatch behavior of a FinFET in subthreshold region (Lc=55nm). For L<Lc, both VT and SS fluctuations increase Id variability.