modern vlsi design 4e: chapter 6 copyright 2008 wayne wolf topics memories: –rom; –sram;...
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![Page 1: Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf Topics Memories: –ROM; –SRAM; –DRAM; –Flash. Image sensors. FPGAs. PLAs](https://reader035.vdocuments.net/reader035/viewer/2022062217/56649ec95503460f94bd698e/html5/thumbnails/1.jpg)
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Topics
• Memories:– ROM;
– SRAM;
– DRAM;
– Flash.
• Image sensors.• FPGAs.• PLAs.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
High-density memory architecture
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Memory operation
• Address is divided into row, column.– Row may contain full word or more than one
word.
• Selected row drives/senses bit lines in columns.
• Amplifiers/drivers read/write bit lines.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Read-only memory (ROM)
• ROM core is organized as NOR gates—pulldown transistors of NOR determine programming.
• Erasable ROMs require special processing that is not typically available.
• ROMs on digital ICs are generally mask-programmed—placement of pulldowns determines ROM contents.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
ROM core circuit
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Static RAM (SRAM)
• Core cell uses six-transistor circuit to store value.
• Value is stored symmetrically—both true and complement are stored on cross-coupled transistors.
• SRAM retains value as long as power is applied to circuit.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
SRAM core cell
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
SRAM core operation
• Read:– precharge bit and bit’ high;– set select line high from row decoder;– one bit line will be pulled down.
• Write:– set bit/bit’ to desired (complementary) values;– set select line high;– drive on bit lines will flip state if necessary.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
SRAM sense amp
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Sense amp operation
• Differential pair—takes advantage of complementarity of bit lines.
• When one bit line goes low, that arm of diff pair reduces its current, causing compensating increase in current in other arm.
• Sense amp can be cross-coupled to increase speed.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
3-transistor dynamic RAM (DRAM)
• First form of DRAM—modern commercial DRAMs use one-transistor cell.
• 3-transistor cell can easily be made with a digital process.
• Dynamic RAM loses value due to charge leakage—must be refreshed.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
3-T DRAM core cell
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
3-T DRAM operation
• Value is stored on gate capacitance of t1.
• Read:– read = 1, write = 0, read_data’ is precharged;
– t1 will pull down read_data’ if 1 is stored.
• Write:– read = 0, write = 1, write_data = value;– guard transistor writes value onto gate
capacitance.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
3-T DRAM operation
• Value is stored on gate capacitance of t1.
• Read:– read = 1, write = 0, read_data’ is precharged;
– t1 will pull down read_data’ if 1 is stored.
• Write:– read = 0, write = 1, write_data = value;– guard transistor writes value onto gate
capacitance.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
1-T DRAM
• Word line controls pass transistor.
• Pass transistor guards access to capacitor.
• Read is destructive.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Stacked capacitor DRAM
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Trench capacitor DRAM
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Floating gate transistor
• Poly 1 gate is not connected.
• Schematic symbol:
p
n+ n+
poly 1
poly 2 SiO2
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Fowler-Nordheim tunneling
p
n+ n+
poly 1
poly 2 SiO2
n-well
n+p+
floating
- -
+20 V
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Fowler-Nordheim erasing
p
n+ n+
poly 1
poly 2 SiO2
n-well
n+p+
floating floating- -+20 V
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
NOR flash architecture
• Same as NOR ROM but with floating gate pulldowns. pullup
+
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
NAND flash architecture
• Want to provide banked memory for higher data throughput.
• Widely used for data storage.
• Likely to become standard architecture.
bank0
bank1
bank2
bank3
address
data
address 1address 2
data 1 data 2
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
2-bit NAND flash cell
bit
n+ source
Select bottom
Select top
RA0
RA1
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
NAND flash cell programming
bit
Select bottom
Select top
RA0
RA1
+20V
+20V
+5V
0V
+7V
Row notprogrammed
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Wear in flash memory
• Write cycles slowly damage devices.• Limited number of write cycles: 10,000.• Software balances utilization of locations to
level wear across the device.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Image sensors
• Two major types of image sensors:– Charge-coupled device (CCD) requires
specialized fabrication steps.– CMOS image sensor uses standard CMOS
technology, perhaps with low-noise modifications.
• CMOS image sensor is an array circuit similar to a RAM.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Photodiodes
• Photodiode turns photons into electrons.
• Photocurrent density:
photons+
n
p
x1
x2
x3
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Active pixel sensor (APS) circuit
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
APS column
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
SRAM-based FPGAs
• Program logic functions, interconnect using SRAM.
• Advantages:– dynamically reconfigurable;– uses standard processes.
• Disadvantages:– SRAM burns power.– Possible to steal, disrupt configuration bits.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Logic elements
• Logic element includes combinational function + register(s).
• Use SRAM as lookup table for combinational function.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
LUT-based logic element
Lookuptable
configurationbits
out
inputs
Can multiplex at output or address at input
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Example
1, 1, 1, 1, 1, 1, 1, 0
111
0, 1, 1, 0, 1, 0, 0, 1
111
0 1
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Evaluation of SRAM-based LUT
• N-input LUT can handle function of 2n inputs.
• All logic functions take the same amount of space.
• SRAM is larger than static gate equivalent of function.
• Burns power at idle.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Static CMOS gate vs. LUT
• Number of transistors:– NAND/NOR gate has 2n transistors.
– 4-input LUT has 128 transistors in SRAM, 96 in multiplexer.
• Delay:– 4-input NAND gate has 9 delay.
– SRAM decoding has 21 delay.
• Power:– Static gate’s power depends on activity.
– SRAM always burns power.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Registers in logic elements
• Want to selectively add register to LE:
Comblogic
D Q
Configuration bit
LE out
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Other LE features
• Multiple logic functions in an LE.• Addition logic:
– carry chain.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Programmable interconnect
• MOS switch controlled by configuration bit:
D Q
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Programmable vs. fixed interconnect
• Switch adds delay.• Transistor off-state is worse in advanced
technologies.• FPGA interconnect has extra length =
added capacitance.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Programmable logic array (PLA)
• Used to implement specialized logic functions.
• A PLA decodes only some addresses (input values); a ROM decodes all addresses.
• PLA not as common in CMOS as in nMOS, but is used for some logic functions.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
PLA organization
AND plane OR plane
p1
p2
p3
p4
f0 f1i0 i0’ i1 i1’product term
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
PLA structure
• AND plane, OR plane, inverters together form complete two-level logic functions.
• Both AND and OR planes are implemented as NOR circuits.
• Pulldown transistors form programming/personality of PLA. Transistors may be referred to as programming tabs.
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
PLA AND/OR cell
programmingtab
no tab
VSS
input 1 input 2
output 1
output 2