module 13: interrupts & exceptions · peralihan berlaku apabila default stack terjadi...

68000 Microprocessor

Module 13: Interrupts & Exceptions

What are exceptionsWhat happens when an exception happensWhat happens when an exception happens (exception processing)The vector tableThe vector tableInterruptsVarious input/output mechanismsVarious input/output mechanismsWriting exception handlers

© 2006 [email protected] 13-1


Exceptions & InterruptsExceptions:

events that alter the normal execution of a programdeviations from the normal sequence of actions carried out by a computerE ample Reset B s error Interr pt etcExample: Reset, Bus error, Interrupt, etc.

Interrupts:Exceptions which are caused by sources external to the 68000.

Exceptions transfer control to the program controlling the system (usually aExceptions transfer control to the program controlling the system (usually a monitor program or an operating system).Examples

Trap:pUser program executes a TRAP instruction for performing input/output

Bus error:PC in user program accesses reserved memory location. An exception handler is i k d i th t b t i t dinvoked, causing the program to be terminated.

Interrupt:An peripheral device requests attention through interrupt lines. The currently running program is suspended temporarily to service the peripheral


p g p p y p p


68000 Exceptions

ExceptionsExceptions

Hardware Software

Reset Interrupts Bus Error ProgrammerInitiated Trace Errors

Traps Emulator AddressError

PrivilegeViolation



Exception Handlers

Exception handler:A routine which is executed when a specific exception p poccursA different handler is required for each type of exception

Interrupt service routine (ISR)Exception handler for interrupts

To return to the interrupted program an exception handlerTo return to the interrupted program, an exception handler executes the RTE (return from exception) instruction.RTE works just like the RTS (return from subrutine) but it j ( )pops SR and PC instead of just the PC



Processing StatesTo help exception processing (and to enable implementation of multi-userimplementation of multi user operating systems), the MC68000 makes specific provisions for two (actuallyprovisions for two (actually three) operating states:･

normal stateexception stateHALTED state - used to prevent unpredictable p pbehavior when a serious system failure occurs



Supervisor vs User ModeSupervisor mode

Default modeUsed in single-user operating systems and monitor programsAll e ception handling programs normall r n in s per isor modeAll exception handling programs normally run in supervisor mode.

User mode Restricted access to the system environment, useful in multi-user environments.

The supervisor bit (bit 13 of the status register) is 1 if the 68000 is in supervisorThe supervisor bit (bit 13 of the status register) is 1 if the 68000 is in supervisor (privileged) mode.



User vs Supervisor Stacks

So that the 68000 does not become confused there are two stacks.

USP references the user stack while the 68000 is in supervisor mode.MOVE.L USP,An and MOVE.L An,USP are the only instructions that can access th t k hil th 68000 i i i d Th b th i il dthe user stack while the 68000 is in supervisor mode. They are both privileged instructions and transfer only long words (32 bits).



User vs Supervisor ModesUser mode Supervisor mode

Enter the mode by… Clear S bit in status register

Executing TRAP instruction,

privilege violationstatus register privilege violation, reset, interrupt

FC2 pin on device (same as S bit) 0 1

D f lt St kPeralihan berlaku apabila

terjadi kekecualianDefault Stack Pointer USP SSP

Access to SR Read whole SRWrite to CCR only

Read whole SRWrite whole SR

Mod Penyelia

Mod Pengguna

terjadi kekecualian

All instructions, except:RESETRTESTOP

Peralihan berlaku melalui lima suruhan:

ANDI ke SR EORI ke SR MOVE ke SR

O SUsable instructionsSTOP

ANDI #d, SREORI #d, SRORI #d, SRMOVE <ea>SR

All instructions ORI ke SR RTE


MOVE An,USP


Exception ProcessingMulakan

Kekecualian

Salin SR ke daftar dalaman

1. Save SR in internal register2. Set S-bit and clear T-bit in SR. If

ti i i t t t thdaftar dalaman

S = 1, T = 0

Sampukan Kemaskini topeng k

exception is an interrupt, set the interrupt mask according to interrupt level.G t th t b f thSampukan

? sampukan

Cari nombor vektor

3. Get the vector number for the exception. Then access the vector address = vector number x 4

Alamat vektor = nombor vektor x 4

Tindan PC dan SR lama

x 44. Stack original PC and SR on

supervisor stack. Stack extra 4 words for bus error or address

PC = Alamat di alamat vektor

Teruskan perlaksanaan

words for bus error or address error.

5. Jump to vector address.


perlaksanaan


Exception Vector Table



System Stack During Exception Processing

Most exceptions cause PC and SR to be stacked.T t t i i l

Status Register

Program Counter (High)

SSP - 6

SSP - 4

SSP after exception

To return to original program, use RTE instruction.

og a Cou e ( g )

Program Counter (Low)SSP - 2

SSPSSP before exception

SSP after exception

Access Address (High)

Memory Access TypeSSP - 14

SSP 12

For bus error or address error exceptions, more data is

Status RegisterSSP - 6

Instruction Register

Access Address (Low)

Access Address (High)SSP - 12

SSP - 10

SSP - 8

e cept o s, o e data sstacked.Normally not possible to return to original program.

g

Program Counter (High)

Program Counter (Low)

SSP - 4

SSP - 2

SSPSSP before exception



How does the 68000 start up?

MULA

S ← 1 T ← 0

I2I1I0 ← 7

Pungut vektor 0 Ralat bas?

Yabas?

SSP ← Kandungan

vektor 0

Tidak

Ralat bas?

Pungut vektor 1

PC ←

Ralat bas kembar

Ya

TidakPC ← Kandungan

vektor 1

TAMAT TAMAT


TAMAT TAMAT


Reset ActionsWhen the 68000 is reset (either on power-up or pressing the reset button), a vector number of 0 is generated.

T l f ROMTemplate for ROM contents.

ORG 0DC.L <bottom of supervisor stack>DC L <add ess of sta t p o tine>DC.L <address of startup routine>…

<startup routine>:1. code to initialize system2 application program


2. application program


Monitor Programs

Single board computers do not typically have an operating system. They have a simple program called a monitor which contains exception service routines whose starting addresses are loaded into the exception vector table at memory locations $8 - $3FF (remember the RESET vector must be inlocations $8 $3FF (remember the RESET vector must be in the first eight memory locations). Typically, the monitor will service key exceptions such as bus dd di id b i h ifi iaddress errors, divide by zero, etc. with specific service

routines. All other exceptions are handled by a generic serviceAll other exceptions are handled by a generic service routine.



Example 68000 Startup CodeIn this example, the monitor program starts at $008146, and the base of the supervisor stack at $0005000$0005000.

The memory (i.e. the RESET vector) in this example looks like

This is how the monitor jumps to a user program.

# 0MOVEA.L #USERSTK,A0 ; Initialize USP MOVE.L A0,USP ; (needs 2 instructions)MOVE.L #MULA,-(SP) ; Set up starting address of user pgmMOVE.W #0,-(SP) ; Set up initialize user status reg

i !


RTE ; Execute it!


“Program-Killing” ExceptionsReset

Not a true exception:Cannot go back to original program, nothing saved on stack

Bus ErrorOccurs when BERR* signal is returned during a bus cycle (instead of DTACK* or VPA*)Typical applications: attempting to write to ROM, memory device error, non-existent memory or memory privilege violation (when used with memory management)Mostly unrecoverable, but still recoverable if the operating system can analyze the extra y , p g y yinfo on stack

Address ErrorOccurs when a word or longword access is attempted on an odd addressMostly unrecoverable because the running program is faulty, but again it also dependsMostly unrecoverable because the running program is faulty, but again it also depends on the operating system

Double Bus FaultNot a true exception, but an indication of unrecoverable errorDefined as “A bus error or address error that happens when attempting to process a busDefined as A bus error or address error that happens when attempting to process a bus error, address error or reset”µP cannot proceed any further!HALT* is asserted LOW to indicate µP has given up working.



BERR* GeneratorThe HC164 shift register resets when AS* is low and starts shifting when AS* is high. This happens every bus cycle.The shift register is clocked using E signal so the frequency is 1/10 the CPU frequencyfrequency.In regular operation, DTACK* or VPA* that is received by the CPU terminates the current bus cycle before the 1 bit has a chance to arrive at the other end of the register.register.If DTACK* or VPA* never arrives or arrives too late, the BERR* signal is asserted.Similar BERR* generator can be implemented using a counter.

MC68000



Exceptions Caused by SoftwareC d b ECaused by Errors

Illegal opcodeAn opcode pattern unrecognizable by the CPU.

Privilege ViolationHappens when a privileged instruction is executed in user mode

Divide by zeroHappens when DIVU or DIVS is attempted and divisor is 0.

Intentionally Used by the ProgrammerTRAP instruction

A request to execute system-level subroutine.TRAPV (Trap if overflow)

Placed after arithmetic instructions. Trap only when V = 1

CHKUsed to check if Dn (D0-D7) exceeds a limit.Trap only if Dn > immediate

Emulator A & FOpcode is $AXXX or $FXXX.Can be used to execute a system subroutine or to impelement a “co-processor”

Trace


Used by the debugger to single-step


Review of I/O StrategiesProgrammed (polled) I/O

“Ask” each device sequentially if it needs service.CPU executes the polling loop repeatedlyCPU executes the polling loop repeatedlyNot efficient: no devices may need servicing during the poll

Interrupt-driven I/ODevice “interrupts” CPU to indicate that it needs service.Need interrupt handling mechanismEfficient: CPU is not tied up in a polling loopp p g p

ISR ISR

Utama Utama Utama



InterruptsWho needs to interrupt?

Devices that perform input/output intermittently: keyboard, printer, etcTypes of interrupt

Non-maskable interruptsA program cannot choose to ignore a non-maskable interrupt. A non-maskable interrupt is used for events that must always be serviced.p yOn 68000, interrupt level 7 is non-maskableExample: Power failure

Maskable interruptspThe program can choose to “ignore” a maskable interruptA maskable interrupt has a level of 1 through 6 on the 68000On systems with 6 devices or less, assign a different interrupt level to each y , g pdeviceThe interrupt mask (I2I1I0) in status register controls an interrupt’s visibilityTo be seen by the 68000, the interrupt level must be higher than the


current value of the interrupt mask.


Interrupt LevelsFor an interrupt to be seen by the 68000, the interrupt level of a device must be higher than the current value of the interrupt mask.

For example, an interrupt mask of 011 enables interrupts only from devices i h l l 4 6with level 4, 5, 6 or 7

Interrupt request level 0 means no interruptDevice with interrupt level 7 cannot be masked

Topeng sampukan(I2I1I0)

Tahap sampukan dibenarkandi IPL2*, IPL1*, IPL0*

000 1 7000 1-7001 2-7010 3-7011 4-7100 5 7100 5-7101 6-7110 7111 7



When An Interrupt is Accepted1. Processor enters supervisor state.2. Status word pushed on supervisor stack.

PC h d i t k3. PC pushed on supervisor stack.4. Mask level raised to level of interrupt.5 Get handler address:5. Get handler address:

If auto-vectoring, get handler address from fixed location in vector table.Otherwise, read vector number from data bus (D7-D0) and get handler address from vector table.

L d PC ith h dl dd6. Load PC with handler address.7. Handler executes RTE to return, restoring PC, PS, and

privilege level.


p g


Priority Encoder 74LS148Active low input & output (0=H, 1=L)The value appearing at output A2/A1/A0 is the binary value for the highest active inputactive inputExample: pins 6, 4 and 1 all LOW highest = 6

There output is 6 = 110 = LLH

7INT7*74LS148

76543

A2A1

IPL2*IPL1*

INT7INT6*INT5*INT4*INT3*

68000

210

A0 IPL0*INT3INT2*INT1*+5 V



Interrupt Acknowledge

Device that interrupts the processors wants to know if the interrupt request is seen by the CPUWh th t i t d P i k l d tWhen the request is granted, µP gives an acknowledgement

IACK7*IACK6*IACK5*

76

A2A1

A3A2

74LS138

68000IACK5*IACK4*IACK3*IACK2*IACK1*

54321

A0A1

E1

E2A

+5 VFC0FC1

10

E2B

FC2

AS*



Identification of Interrupting DevicePolled Interrupt

have a common interrupt service routine for all devicesthe interrupt service routine checks the status of each device in turn (high software overhead)overhead)

Vectored InterruptCPU obtains a vector number from the interrupting device.Device responds to an IACK by providing a vector number on D00-D07 and asserting DTACK*.

Autovectored InterruptOlder devices for 8-bit processor cannot provide vector numbers.If VPA* is asserted at IACK cycle the 68000 carries out autovectored interruptIf VPA is asserted at IACK cycle, the 68000 carries out autovectored interrupt.Internally, the 68000 generates the appropriate vector number. Vectors $19-$1F reserved for autovectored interrupt

68K

Device1

Device 2

Device3

Device4


Data Bus


Vectored Interrupt

68000 Serpihan I/O

IPL0IPL1 P

enge

kod

keut

amaa

n IRQ1IRQ2IRQ3IRQ4IRQ5

IRQ12 0

Jadual Vektor000000000004000008

12

Nombor vektor

Memory Address

Pen

geko

d 3-

ke-8

A3A2A1

CBA

IACK1IACK2IACK3IACK4IACK

IACK

IPL2 P k IRQ5IRQ6IRQ7

3a 4

31

3200007C000080

128

129

000200000204

6 7

FC0FC1FC2

A1 A IACK5IACK6IACK7 Daftar Vektor

Sampukan

Nombor vektor3b E1 E2

255 0003FC

129 000204

Alamat Rutin Servis S k

8D0-D7

5Nombor vektor

DTACKDTACK

SampukanLaksanakan Rutin Servis Sampukan

hingga tamat

RTE



Another View of Previous Slide

Avbrotts-ingång

5

IACK2

3

45

IRQDTACK

110

Vektorregister

6

79

IACK8

CPU



Other Types of Interrupt

Spurious InterruptWhen an interrupt acknowledge is given, the peripheral p g g , p pmust respond by returning DTACK* or VPA*.If the original interrupt was not really an interrupt (example, comes from a hardware glitch) an external circuitcomes from a hardware glitch), an external circuit (watchdog timer) dan output BERR* to cancel the interrupt

Uninitialized Interruptp68000 peripherals (PIT/DUART/etc) must be initialized with a vector value in the IVR (interrupt vector register), before i i i t tissuing any interruptsIf the IVR is not changed, the vector number $0F is returned


etu ed


Vectored & Autovectored Interrupts in Same System



Writing the Interrupt Service Routine (ISR)

1. Choose suitable interrupt for the device (1-7)2 Choose a vector type: regular (68000 family) or autovector2. Choose a vector type: regular (68000 family) or autovector

(6800 family).3. From (1) and (2), get the vector address( ) ( ), g

Example: interrupt level 6, autovector -> vector number 30 -> vector address $78 (3010 x 4).

4. Choose a suitable location for ISR (interrupt service routine). Enter this address in the vector table.

5 Write your routine beginning at chosen address5. Write your routine beginning at chosen address



Example 1: Keyboard buffering

1. Assume keyboard has no internal buffer, so processor has to provide software bufferto provide software buffer.

2. Assume type-ahead is nice.3. Assume polling is bad.4. Assume keyboard is ``dumb,'' so auto-vectoring is used.5. Keyboard uses IRQ2, which uses location 0x68 (auto-vector

2) i t t bl2) in vector table6. Keyboard is memory mapped, using locations DATAIN,

DATAOUT, and STATUS.7. Keyboard buffer is LINEDATAOUT, and STATUS.7. Keyboard buffer is LINE



Example: Keyboard buffering (cont)//INTVEC EQU $68 // Location in vector table.

INTEN EQU $40 // Keyboard int. enable.INTDIS EQU 0 // Keyboard int. disable.NEWPS EQU $0100 // 68000 int. mask.RTRN EQU $0D // ASCII for carriage return.

...

MOVE.L #READ, INTVEC // Initialization.MOVE.L #LINE, PNTRMOVE.B #INTEN, STATUSMOVE.L #NEWPS, -(A7) // Load correct mask and PCMOVE.L #MAIN, -(A7) // and enter user privilege level.RTE....

MAIN ...

// Keyboard interrupt handler.

READ MOVEA.L A0, -(A7) // Save register.MOVEA.L PNTR, A0MOVE.B DATAIN, (A0)+MOVEA.L A0, PNTRCMPI.B #RTRN, -1(A0)BNE DONEMOVE.B #INTDIS, STATUS // Process line of input.BSR TEXT


DONE MOVEA.L (A7)+, A0RTE


Typical Monitor Routine* MONITOR INITIALIZATION ROUTINE* MONITOR INITIALIZATION ROUTINE* ASSUMES RESET VECTOR CONTAINS ADDRESS OF INIT AT $4STARTSP EQU $8000 ;initial stack pointer value

* EXCEPTION VECTOR ADDRESSES IN SEQUENTIAL ORDERVBUSERR EQU $08Q $VADDERR EQU $0CVILLEGINST EQU $10VZERODIV EQU $14VCHK EQU $18VTRAPV EQU $1C

$VPRIVINST EQU $20VTRACE EQU $24

* STORE EXCEPTION VECTORS IN THE ADDRESS TABLE

* RESET vector starts here* RESET vector starts hereINIT LEA STARTSP,SP ;initialize SSP

MOVE.L #BUSERR,VBUSERR.W ;initialize exceptionMOVE.L #ADDERR,VADDERR.W ;vector tableMOVE.L #ILLINST,VILLINST.WMOVE.L #XHANDLE,VZERODIV.W,MOVE.L #XHANDLE,VCHK.WMOVE.L #XHANDLE,VTRAPV.WMOVE.L #PRIVIOL,VPRIVINST.WMOVE.L #TRACE,VTRACE.W

$28 0 l d f h i bl


LEA $28,A0 ;load rest of the exception table;from address $28 to $3FC with;starting address of routine XHANDLE


Typical Monitor Routine (cont)ABINIT MOVE.L #XHANDLE,(A0)+

CMPA.L #$400,A0BCS.S TABINIT

MAIN {This is the mini-operating system and is a programthat always runs. It might interpret commands, etc.}BRA MAIN

* EXCEPTION SERVICE ROUTINES

BUSERR { t d f ti h }BUSERR {put code for routine here}

ADDERR {put code for routine here}

ILLINST {put code for routine here}ILLINST {put code for routine here}

PRIVIOL {put code for routine here}

TRACE {put code for routine here}


{p }


Typical Monitor Routine (cont)

XHANDLE ;prints error messageXHANDLE ;prints error messageMOVEQ #0,D0 ;clear D1LEA EXCEPTMSG,A0 ;load location of messageJSR PUTSTRING ;print itMOVE.L 2(SP),D0 ;get return address from system stackJSR PUTHEX ;print itJSR NEWLINE

* FLUSH THE RETURN ADDRESS AND SR FROM THE SYSTEM STACKADDQ.W #6,SP ;flush the stackBRA MAIN t t itBRA MAIN ;return to monitor

EXCEPTMSG DC.B 'UNEXPECTED EXCEPTION AT ',0



Interrupts and Real-time ProcessingMultitasking (multiprogramming)

concurrent executionlti l t k ( )multiple tasks (processes)

resource sharing (multiple users using the same printer)

Multiprocessingparallel execution pmultiple PROCESSORS!



Multitasking

Operating system (to schedule activities)


Interrupt mechanism (to switch between tasks)


Real-Time Operating SystemReal time - meaningful time

fast enough to influence the system at that momentspace shuttle / chemical plantspace shuttle / chemical plant

Real-time systemOptimizes the response time to eventsTries to use resources efficiently

Multitasking systemMultitasking systemOptimizes resource utilization Tries to provide a reasonable response timep p



Real-Time KernelScheduler is the kernel, nucleus, of a real-time OSFunctions

fi t l l i t t h dla first-level interrupt handlerscheduler - the sequence in which tasks are executed interprocess communicationinterprocess communication

Task StatesReady

READY BLOCKEDyRunningBlocked (dormant)

RUNNING



TasksVolatile portion (PC, status, registers)Task control block (TCB)

T k ID

Figure 6.25

Task IDTask block pointer

PCSPSPstatus registerother registers

Task statusrun / ready / blckd

Task priorityTask time allocation

how many slots



SummaryExceptions enable the implementation of very reliable systemsTypes of exceptions are: error-caused or intentionalAll exceptions require the use of the vector table to arrive at the exception handlertable to arrive at the exception handlerInterrupts are serviced using the exception handling mechanismhandling mechanismInterrupts enable more efficient use of CPU ti


time

Backup SlidesBackup Slides


Exception Handling and TasksPreemptive real-time OS:

RTC generates periodic interrupts used by the kernel to locate and run the next task

How to deal with other interrupts?How to deal with other interrupts? Service them independently, subject to priorityIntegrate them into the real-time task structure

Vectoredinterrupt

Real-time clockinterrupt

Exception

Turn on readyto run flag of

appropriate task

Turn on readyto run flag of

appropriate task

Call RT taskscheduler and switch tasks

RTE



Ex.2: Output to Port with Fixed Software Delay

Port EQU $01800 Location of PortCount EQU 128 Size of block to outputDeloop EQU 64 wait loop

$

PSEUDO-CODE:

FOR i=1 to 128ORG $000400 Program origin

:MOVE #Count,D1 ;set up loop counterLEA Table,A0 ;A0 points to table in memoryLEA Port,A1 ;A1 points to Port

move data from

table to port

it fi d tio t, ; po ts to o t:

LOOP1 MOVE.B (A0)+,D0 ;D0 memory([A0]); [A0] [A0]+1

MOVE.B D0,(A1) ;Output data

wait a fixed time

END FOR

JSR DelaySUB #1,D1 ;decrement loop countBNE LOOP1 ;repeat for all 128 data

:Delay MOVE #deloop, D2 ;set up delay loop time

Disadvantages:

•Need delay time between outputs to be sufficient for external d iDelay MOVE #deloop, D2 ;set up delay loop time

Loop2 SUB #1,D2 ;decrement loop timeBNE Loop2 ;wait for loop timeRTS ;return from subroutine

devices.

•No handshake used

•Microprocessor tied up by hil iti


ORG $002000Table DS.B 128 ;128bytes reserved for data table

program while waiting


Output to Port with PollingPortdata EQU $08000 Location of Port dataPortstat EQU $08002 Location of Port’s status byteCount EQU 128 Size of block to input

ORG $000400 Program origin

PSEUDO-CODE:

FOR i=1 to 128:

MOVE #Count, D1 ;set up loop counterLEA Table,A0 ;A0 points to table in memoryLEA Portdat,A1 ;A1 points to Port dataLEA Portstat,A2 ;A2 points to Port status

get data from table

wait until port ready

::

LOOP MOVE.B (A0)+,D0 ;D0 memory([A0]); [A0] [A0]+1

WAIT MOVE.B (A2),D2 ;Read status

y

output data

END FOR( ), ;

AND.B #1,D2 ;mask off all but ready bitBEQ WAIT ;wait for port readyMOVE.B D0,(A1) ;Output data to peripheralSUB #1,D1 ;decrement loop countBNE LOOP1 ;repeat for all 128 data

Disadvantages:

• Limited handshakeBNE LOOP1 ;repeat for all 128 data

::

ORG $002000Table DS B 128 ;128bytes reserved for data table

• Microprocessor tied up waiting for peripheral to be ready


Table DS.B 128 ;128bytes reserved for data table


Interrupt Driven I/OModify previous example (of last 2 slides): to obtain regular slow timed outputs-interrupt could be caused by a software pre-

d Ti / t hi t t

OUTPUT EQU $008000 Location of O/P Port

programmed Timer/counter chip output connected to a processor interrupt line.

ORG $000400 Start of program:

INTY MOVEM.L D0-D7/A0-A6,-(A7) Save environment – general for subroutinesMOVEA.L POINTER,A0 Point A0 to bufferMOVE.B (A0)+,D0 Read a byte from bufferO . ( 0) , 0 ead a byte o bu eMOVE.B D0,Output Send to O/P portMOVE.L A0,POINTER Save updated pointerMOVEM.L (A7)+,Do-D7/A0-A6 Restore EnvironmentRTE Return from interrupt::

ORG $002000 Data OriginBUFFER DS.B 1024 Reserve 1024 bytesPOINTER DC.L BUFFER Reserve long word


module 13: interrupts & exceptions · peralihan berlaku apabila default stack terjadi...

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