NOISE IN DEVICES AND CIRCUITS

Moore’s law and the energy requirement ofcomputing versus performance

L.B. Kish

Abstract: It has recently been recognised that speed, noise and energy dissipation are stronglyinterrelated entities. Following Moore’s law of miniaturisation, at sizes below 40nm, physics willimpose fundamental and practical limits of performance by shrinking noise margin, increasing andquickening noise, and increasing power dissipation. It is important to locate the fundamentalaspects of the problem, explore relevant practical problems and possible solutions, and investigatethis situation, not only in microelectronics (CMOS etc.) but also in single-electron-transistor-basednanoelectronics and also in quantum informatics applications. The energy requirement of runningclassical and quantum logic gates is compared.

1 Thermal noise and the Rice equation

Thermal noise is an omnipresent small voltage fluctuationon resistors. It has been thought that thermal noise willnever be an issue in digital electronics. This view has beenre-evaluated and changed recently [1, 2]. On a parallelresistor–capacitor (RC) unit, the effective thermal noisevoltage Un is given as

Un ¼ffiffiffiffiffiffiffiffiffiffiffikT=C

pð1Þ

and the bandwidth fc of this noise is

fc ¼1

2pRCð2Þ

Gaussian noise processes, such as thermal noise, can crosslarge amplitude levels provided that sufficiently long time isavailable. In a logic circuitry, noise amplitudes reachingbeyond the noise margin Uth cause false bit flips, which canresult in bit errors. For a single, band-limited noise process,the mean frequency n(Uth) of bit errors can be obtainedfrom the Rice formula [1, 2]:

nðUthÞ ¼2ffiffiffi3

p exp�U 2

th

2U 2n

� �fc ð3Þ

where Un is the effective noise voltage and fc is thebandwidth.

So, what happens during miniaturisation? In CMOStechnology, the resistors are two-dimensional conductors,so the resistance stays (roughly) constant. Therefore, thesupply voltage has to be decreased to keep the electrical fieldand dissipation at an acceptable level. The capacitances aredecreasing. Together, these effects yield the followingtrends:

(i) a shrinking noise margin because Uth is only a fraction ofthe supply voltage

(ii) a growing noise because of (1)

(iii) the bandwidth is growing; see (2) – quickening of thenoise.

All these phenomena, (i)–(iii), help toward radicallyincreasing the frequency of bit errors via (3). To have afeeling for the nature of this problem, in Fig. 1 the bit errorfrequency versus the noise margin normalised to the noisevoltage is shown for different bandwidths (clock frequency)and different numbers of transistors. The practical limit ofusability is a certain Uth/Un ratio when the bit error rate isaround 1 error /year. Even a 10% decrease of the Uth/Un

ratio compared to its critical value yields an error rateincrease to 105 when we consider all transistors in a modernPC (3� 109–1010 transistors).

Using these results and a prediction of the evolution ofcapacitance and noise margin using present trends, recentlya prediction of the end of Moore’s law was published [1, 2],see Fig. 2.

10− 15

10− 12

10− 9

10− 6

10− 3

100

103

106

109

1012

8 9 10 11 12

freq

uenc

y of

bit

flip

erro

rs, 1

/yea

r

clock frequency: 2GHz

1 transistor

108 transistors

1010 transistors

109 transistors

clock frequency: 20GHz

Uth /Un

Fig. 1 Bit errors against ratio of noise margin and effective noisevoltage [1, 2]

The author is with the Department of Electrical Engineering, Texas A&MUniversity, College Station TX 77843-3128, USA

r IEE, 2004

IEE Proceedings online no. 20040434

doi:10.1049/ip-cds:20040434

Paper first received 9th June and in final revised form 29th October 2003

190 IEE Proc.-Circuits Devices Syst., Vol. 151, No. 2, April 2004

The shrinking noise margin (logic threshold voltage) andthe increasing noise margin required by the increasing andquickening noise pose conflicting requirements which wouldstop miniaturisation in 6–8 years if the trends of recent yearscontinue.

In the rest of this paper, we outline the objectives thatneed further analysis and give some initiatives for extendedresearch in the future.

2 Refinements of predictions for CMOS technology

It has been pointed out in [1, 2] that the prediction wasbased on strong approximations to keep generality andbecause of lack of information about certain deviceparameters. Since [1] was published new information frommicroprocessor makers about some previously unknownparameters have emerged and some new efforts have beenmade to reduce the supply voltage with a rate less thanpreviously supposed. These efforts are, however, controver-sial because many large-scale users, for example in aviationelectronics [3], would like to increase the rate of supplyvoltage reduction in order to improve the device failure rate,which has been steadily growing due to high electric fields inchips.

Therefore theoretical efforts have been made on refiningthe prediction for the bit error problem due to thermalnoise. The refined model takes into the account thefollowing aspects:

� further noise margin decrease due to the openingthreshold voltages of the P and N type MOSFETtransistors

� somewhat reduced noise due to parallel gate circuits

� the various supply voltage reduction strategies (predic-tions are controversial)

� the fact that the internal supply voltage and noise marginof microprocessors in 2002 was already less than supposedin [1].

Interestingly, the preliminary investigations indicate thatthe size range, where the problems begin, remains the samebecause the different corrections act in different directions

and the effects compensate each other. Thus, the conclu-sions obtained in the context of Fig. 2 remain the same.

3 Single-electron transistor based microprocessors

The next question is the bit error situation of micropro-cessors based on single-electron transistors (SETs) [4]. SETsutilise tunnelling, which is not dissipative, but the processescoupled to it are dissipative. The electrons at the tunneljunction of a closed SET can be excited by thermal energyfluctuations to the energy level where tunnelling can occurand a single electron can cause a single bit error in a SET.Similarly, an open SET can be temporarily shut down bythermal fluctuations. So, the tentative expectation is thatSETs will have similar types of bit error characteristics asCMOS. However, the picture is more complex [4]:

� Instead of a single capacitance, three different capaci-tances influence the bit errors, the two tunnel junctioncapacitances and the quantum dot capacitance (gatecapacitance).

� The noise margin cannot be increased arbitrarily byincreasing supply voltage. It has a practical maximumwhich is equal to the voltage difference between the totallyclosed and totally open transistor. Higher voltages causemultiple electron operation modes and large noise anddissipation.

� There are two different working ranges versus thequantum dot size. A larger size, Coulomb blockade controlsthe current transport, and smaller size (o10nm) quantumconfinement effects dominate.

Preliminary studies [4] show that the requirement forsmall quantum dot sise becomes much harder to satisfywhen not only the DC characteristics but also bit errorsmatter in a microprocessor with 108 or more SETs. To haveSET based microprocessors, the characteristic quantum dotsise has to be 1nm.

4 Ultimate limits of energy dissipation versusperformance in classical and quantum computing

The ultimate and most fundamental questions are related tothe power requirement of classical and quantum informa-tion processing. If CMOS and SET fail, it is a naturalquestion if quantum computing and quantum informationcan help and how. Because, so far, the existing quantumcomputing architectures are not practical, the only questionwe may be able to address is regarding the ultimate limits ofperformance. Performance includes error rate (accuracy),speed (bandwidth) and power dissipation. It is veryimportant to take temperature into account, and tocompare the ultimate performance limits of classical andquantum computers at the same temperature [5].

Recent studies [5, 6] (see the Appendix, Section 7) showthat quantum computers have problems at high accuracydue to Heisenberg’s uncertainty principle. Classical compu-ters performmuch better as accuracy is concerned; however,quantum computers can balance this deficiency by a greaterspeed [5] (see in the Appendix). For a comparison of theenergy requirements of a classical and a quantum gate whenthey run at the same clock frequency, see Figs. 3 and 4 [2, 5].

Recent studies [7] comparing general-purpose quantumand classical computers indicate that, even by using errorcorrection, quantum computer will dissipate at least 100times more energy at the same performance.

0.1

1

10 100

logi

c th

resh

old

volta

ge U

th, V

size, nm

A

B

noise constraintC ∝ s −2

noise constraintC ∝ s −1

dissipationconstraintU0 ∝ s

pentium 4

Fig. 2 Prediction of the end of Moore’s law [1, 2]The technology faces a difficult problem when the upper limit of noisemargin set by the dissipation/field constraint and the lower limit ofnoise margin required by the noise/error constraint cross each other(between points A or B, depending on the evolution of gate oxidethickness)A: 36nm, 0.3V; B: 25nm, 0.2V

IEE Proc.-Circuits Devices Syst., Vol. 151, No. 2, April 2004 191

However, it is important to note that the ultimatefocus of this study, in the future, will not be the accuracy(error rate) of classical and quantum computers but theenergy requirements of processing Shannon information(bit). This aspect induces many new questions includingthe problem of computer architectures which are notsensitive to noise. In the Appendix (Section 7.2), we show

that the ultimate measure, Shannon’s informationchannel capacity versus the energy dissipation, also givesbetter results in a classical than in a quantum gate(see Fig. 5).

5 Conclusion

We have all been enjoying the fast growth of speed andmemory size of computers during the last few decades.Recently, the emerging fields of quantum computing andnanoelectronics have suggested that the future will be evenmore brilliant.

However, as soon as we confront physical laws andreality with expectations, the future seems to be less bright.The author of this paper has developed the opinion that‘nano’ and ‘quantum’ will turn out to be dead ends as far asinformation technology is concerned. Most probably, themicroelectronics in the 50–100nm range will be proven tobe the best technology, at least, for silicon. However, itwas important to experience the nano and quantumscales in order to draw this conclusion and for theimportant fundamental scientific results and the limitsfound there.

6 References

1 Kish, L.B.: ‘End of Moore’s law: thermal (noise) death of integrationin micro and nanoelectronics’, Phys. Lett., 2002, 305, pp. 144–149

2 Kish, L.B.: ‘Moore’s law, performance and power dissipation’, in‘Encyclopedia of nano science’ (Marcel Dekker, in press)

3 Huang, B., Qin, J., Walters, J., and Bernstein, J.B.: ‘Development ofderating guidelines for semiconductor devices’. Aerospace VehicleSystems Institute Report, 2003, unpublished

4 Kim, J., and Kish, L.B.: ‘Can single electronic microprocessors everwork at room temperature?’, Proc. SPIE-Int. Soc. Opt. Eng., 2003,5115, pp. 174–182

5 Kish, L.B.: ‘Moore’s law is killed by classical physics; can quantuminformation save it?’, Proc. SPIE-Int. Soc. Opt. Eng., 2003, 5115,pp. 167–173

6 Gea-Banacloche, J.: ‘Minimum energy requirements for quantumcomputation’, Phys. Rev. Lett., 2002, 89, p. 217901/1-4

7 Gea-Banacloche, J., and Kish, L.B.: ‘Comparison of energy require-ments for classical and quantum information processing’, Fluct. NoiseLett., 2003, 3, pp. C3–C7

8 Landauer, R.: IBM J. Res. Dev., 1961, 5, p. 1839 Allahverdyan, A.E., and Nieuwenhuizen, Th.M.: ‘Testing the

violation of the Clausius inequality in nanoscale electric circuits’,Phys. Rev. B, Condens. Matter Mater. Phys., 2002, 66, p. 115309

10 Kiss, L.B.: ‘To the problem of zero-point energy and thermal noise’,Solid State Commun., 1988, 67, p. 749

7 Appendix

7.1 Accuracy versus power dissipation inCMOS and quantum computersThe lowest limit of the energy requirement, Eq, for a singleoperation of a quantum logic gate is given by Gea-Banacloche (see [2]) as

Eq ��h

eqtq¼ �hfc;q

eqð4Þ

where eq and tq are the error probability and the timerequirements of the quantum logic operation; 1/eq is relatedto the accuracy of the gate operation. Then, for the case ofsequential operation of the gate, the maximum clockfrequency is given as fc,q¼ 1/tq. Although the requiredenergy is not the dissipated energy but the energy requiredto be put into the quantum gate, we can consider this energyas a practically dissipated energy. The situation is verysimilar in CMOS technology, where the electrical energydue to the gate capacitance charge is an ordered energy: it ismost obvious that this energy is practically dissipated ateach change of logic state.

10− 2510− 2210− 1910− 1610− 1310− 1010− 710− 410− 1

102105

10− 31 10− 26 10− 21 10− 16 10− 11 10− 6

CMOS gate 3 GHzCMOS gate 20 GHzquantum gate 3 GHzquantum gate 20 GHz

10− 1

ener

gy d

issi

patio

n/op

erat

ion,

J

CMOS gate

quantum gate

error ratio �

Fig. 3 Minimal energy dissipation of single logical gates [2, 5, 6],classical (CMOS) and quantum, against the error ratio of the gateThe quantum gate result is for zero temperature. See the derivation inthe Appendix (Section 7.1)

10− 31 10− 26 10− 21 10− 16 10− 11 10− 6 10− 1

error ratio �

10− 1510− 1210− 910− 610− 3

100103106109

10121015 power, CMOS, 3 GHz

power, CMOS, 20 GHzpower, quantum, 3 GHzpower, quantum, 20 GHz

pow

er d

issi

patio

n of

sin

gle

gate

, W

CMOS gates

quantum gates max. of total chip power today

Fig. 4 Minimal power dissipation of single logical gates [2, 5, 6],classical (CMOS) and quantum, against the error ratio of the gateThe quantum gate result is for zero temperature. See the derivation inthe Appendix (Section 7.1)

1019

1020

1012

1013

1014

1015

0 10 20 30 40 50 60 70

Kc

and

Kq,

bit/

J at

300

K

fc (clock frequency of quantum gate, Eq = 70 kT )

Kc (MOS gate) and Kq in classical limit(kT = hfc = Eq)

Kq (quantum gate, Eq = 70 kT )

hfc = kT

Eq /hfc

fc , Hz

Fig. 5 Bit/joule performance of classical and quantum logicalgates [5]See derivation in the Appendix (Section 7.2)

192 IEE Proc.-Circuits Devices Syst., Vol. 151, No. 2, April 2004

For CMOS transistors, the mean frequency of bit errors[6] is given as

n ¼ 2ffiffiffi3

p exp�U 2

th

2U2n

� �fc ð5Þ

where Uth (logic threshold voltage) is the noise marginbetween the logic low (0) and high (1) levels, Un is theeffective thermal noise voltage on the CMOS transistors’resultant gate capacitance, and fc is the RC time constant ofthe gate capacitance and its driving resistance, which is themaximal clock frequency. Then, if we drive the system atfrequency fc, the error probability is

ec ¼nfc

¼ 2ffiffiffi3

p exp�U2

th

2U 2n

� �ð6Þ

Because U2th and U2

n are related to the static andthermodynamic energies in the capacitor, respectively, thisresult can be generalised for any kind of available digitaltechnology where, without exception, the logic thresholdenergy is dissipated during the change of logic state. Takinginto the account that the logic voltage change is the voltagechange on the gate capacitance, the lower limit of energydissipated during the change of logic state satisfies therelation

Ec 1

2CU2

th Ec;min ð7Þ

where C is the resultant capacitance at the gate electrode.Note that the actual value is

1

2C ðU0 þ UthÞ2 � U2

0

h i¼ 1

2C U 2

th þ 2U0Uth� �

1

2CU 2

th

where U0 is the low (0) logic voltage level, so (7) indeed givesthe lower limit (the U0¼ 0 case). The mean thermal noiseenergy in the capacitor is

1

2CU 2

n ¼ kT2

Using (2), for room temperature, the minimum Uth/Un ratiofor error-free operation (o1 false-bit-flip/year due tothermal noise) was given 12 [1], which corresponds to

Ec

kT 72 � 70 ð8Þ

Thus, the error rate can be given as

ec ¼2ffiffiffi3

p exp�U 2

th

2U 2n

� �¼ 2ffiffiffi

3p exp

�CU2th

2CU 2n

� �

¼ 2ffiffiffi3

p exp�Ediss;min

kT

� �ð9Þ

which is a generalised result for digital gates, independent oftechnology. We can then express the minimum dissipatedenergy per bit-flip as follows:

Ec;min ¼ �kT ln

ffiffiffi3

p

2ec

!ð10Þ

If, on the average, N transistors are changing their logicalstate in the processor during one clock period, the totaldissipated power is

Ptotal;min ¼ �NfckT ln

ffiffiffi3

p

2ec

!ð11Þ

In Fig. 3, the energy dissipation of one logical gate, for asingle classical or quantum operation, versus the error ratioof the gate, is shown. The quantum case is given by the

results of Gea-Banacloche [6]. At today’s clock frequenciesand those expected in the near future, the quantum gatedissipates more energy than the classical gate for error rateso10�6. At the required error rate (10�25) of today’sclassical gates, the quantum gate would need B100J for asingle operation!

In Fig. 4, the power dissipation of single logical gates,classical (CMOS) and quantum, driven with a given clockfrequency, versus the error ratio of the gate, is shown. It issupposed that the classical gate changes its state in eachclock frequency period. Already at a modest error rate of10–16, a single quantum gate would require more powerthan today’s microprocessors. At the error rate of a classicallogical gate (E1025), the single quantum gate woulddissipate over 104 megawatts.

As an example, let us now estimate the classical powerlimit for today’s microprocessors (2003). The number oftransistors is E1.5� 108. Suppose that, at maximum load,all transistors are effectively changing their logic state ateach clock period. The clock frequency is 3 GHz and let theallowed total bit error frequency in the system of theE1.5� 108 transistors be 1/year [1]. Then

ec ¼1=ð3� 109 � 3600� 24� 365� 1:5� 108Þ¼7:05� 10�26 ð12Þ

and from (11) we obtain

Ptotal;min ¼� 1:5� 108 � 3� 109 � 4� 10�21

ln

ffiffiffi3

p

2� 7:05� 10�26

!� 0:105W ð13Þ

This calculation indicates that the energy efficiency oftoday’s microprocessors withE100W power dissipation, atthe given error probability, is B0.1%. We will see in thefollowing Section that this low error rate, which is necessaryfor the error-free running of the programs and processorroutines, is not necessary for the information content ofdata. In computers which would be able to utilise theShannon information, the required power is even less.

7.2 Energy requirement of Shannon-information transfer in single classical (CMOS)and quantum gatesIn this Section, we evaluate the energy requirement ofShannon information transfer. This measure, which cannotbe improved by error correcting algorithms, is the ultimateone, the real characteristic of performance versus powerdissipation. How to see this? Shannon’s information channelcapacity depends on two factors: the bandwidth and thesignal to noise ratio (see below). A greater error probabilitycan be compensated by a greater bandwidth to keep goodperformance. For example, the poor accuracy of quantumcomputers can, in principle, be compensated by a sufficientlyhigher speed of operation. Although the practical realisationof such systems is not obvious, it is still interesting to explorethe ultimate limits of performance for Shannon information.If the signal to noise ratio (SNR), which is the ratio of thesignal power, Ps , to the noise power, PN , and the frequencybandwidth B is known, then Shannon’s information channelcapacity can be calculated by the Shannon formula. For thequantum gate, the SNR is 1=eq , so using the best case givenby Gea-Banacloche (see [2]), we obtain

Cq ¼B log2 1þ PsPN

� �¼ 1

tqlog2 1þ 1

eq

� �

¼ 1

tqlog2 1þ Eqtq

�h

� �¼ fc log2 1þ Eq

fc �h

� �ð14Þ

IEE Proc.-Circuits Devices Syst., Vol. 151, No. 2, April 2004 193

where the maximum clock frequency is fc ¼ 1=tq. Let usintroduce the normalised information channel capacity K(bit/s/W or bit/J), which is the information channel capacitydivided by the power dissipation. In the case of quantumgate, it is as follows:

Kq ¼Cq

Pq¼ Cq

fcEq¼ fc

fcEqlog2 1þ Eq

�hfc

� �

¼ 1

Eqlog2 1þ Eq

�hfc

� �ð15Þ

where Pq is the power dissipation of the quantum gate whendriven by the maximum clock frequency. At nonzerotemperature, the following natural limitations occur for thequantum limit:

�hfc � kT ðthermal ðclassicalÞdecoherence constraintÞ;

�hfc Eq ðquantumuncertainty errorconstraint; comparewith equationð1Þ ½2�

Eq � kT ðthermodynamical errorconstraint for quantumgateÞ

9>>>>>>=>>>>>>; ð16Þ

The last condition is required to avoid flipping the logicstate of the quantum gate by thermal activation andrequires the same kind of thermal noise considerations as(3) and (5). As a practically motivated example, in Fig. 3,the maximum information transfer rate is at 1W powerdissipation (bit/s/W) when the clock frequency is varied andEq is set so that flipping the quantum gate’s state by thermalnoise can be neglected (Eq¼ 70kT). The broken line showshow the clock frequency should be decreased to improveperformance. The Figure contains the whole range ofmeaningful working range as expressed by (16). The righthand end of the X-axis corresponds to the classicalthermodynamical (thermal decoherence) decoherence limit,and the left hand end to the case limited by quantumuncertainty, eq¼ 1 (see (4).

For a CMOS (classical) gate the error probability e, whenit is small, is

ec ¼nðEcÞfc

¼ tcnðEcÞ ð17Þ

Because the signal to noise ratio (SNR) is equal to the errorprobability, the information channel capacity can be givenas

Cc ¼B log2 1þ PsPN

� �¼ fc log2 1þ fc

n

� �

¼fc log2 1þffiffiffi3

p

2exp

U 2th

2U2n

� �" #

¼fc log2 1þffiffiffi3

p

2exp

Ec

kT

� �" #ð18Þ

and for EcckT

Cc � fcEc

kTð19Þ

Thus, in the case of a classical gate, the normalisedinformation channel capacity is

Kc ¼Cc

Pc¼ Cc

fcEc¼ fc

fcEclog2 1þ

ffiffiffi3

p

2exp

Ec

kT

� �" #

¼ 1

Eclog2 1þ

ffiffiffi3

p

2exp

Ec

kT

� �" #� 1

kTð20Þ

Equation (20) contains an exact analytical result. It is ofinterest to note that the dissipation is the same asLandauer’s conjecture [8] about the energy dissipationduring information erasure at reversible computing, whichis about kT per bit. However, it is important to emphasisethat our result is not for reversible computing, so it is notdirectly relevant for Landauer’s case. The total energy in theCMOS capacitor is dissipated during discharge which is anirreversible process.

Equation (20) indicates that the classical gate performsbetter by more than an order of magnitude than the thermalnoise free quantum gate (Eq¼ 70kT); see Fig. 3. It isimportant to note that in the limit of

kT ¼ Eq ¼ �hfc ð21Þ

the quantum gate would have the same performance as theclassical, because then Kq¼ 1/kT. Altough this case isexcluded by (16), it can be approached. From another angleof view, the conditions described by (21) set the limit whenthe quantum system becomes classical. This finding and thefact that then (21) yields the same results as (20), confirmsthat both the classical and quantum theories are on the righttrack. However, in this limit the error probability eqapproaches 1 (see Equation (4)), and thus the quantumgate is useless for practical applications. To improve theaccuracy to an acceptable level, we have to move toward thestrongly quantum limit, but then the value of Kq decreases.A simple estimation shows that for o0.1 error probabilitycaused independently by both the thermal excitation andthe quantum measurement, we would need EqZ2.4kT (3)and Eq 10�hfc ((4)). As, according to (16), �hfc � kT , thecondition Eq 10�hfc � 10 kT satisfies both relations andthen the quantum error would be dominant (0.1). Similarconsiderations would lead to EqZ70kT for an errorprobability requirement of 1.5% dominated by thequantum error again.

Finally, let us estimate how much power today’s micro-processors would need in the most ideal case of a classicalCMOS gate for processing of Shannon information.The same conditions as in (13), yield

Ptotal;min � 1:5� 108 � 3� 109 � 4� 10�21

� 0:002W ð22Þ

which is 50 times less than the minimal power required bytoday’s error rate; see (13). So, compared to the energyrequirement of the processing of Shannon information, theenergy efficiency of today’s microprocessors is B0.002%.

The general conclusion of these derivations is that, ingeneral purpose applications, where we have to have accessto each memory element in the computer, classicalcomputers perform many orders of magnitude better whenhigh data accuracy is required. This is not really surprising.The phenomena of zero-point thermal noise [9, 10] showthat ‘quantum’ can produce noise even when ‘classical’ iscertainly silent, which is at zero temperature.

194 IEE Proc.-Circuits Devices Syst., Vol. 151, No. 2, April 2004