mos – ak montreux 18/09/06 institut dÉlectronique du sud advances in 1/f noise modeling: 1/f gate...

MOS – AK Montreux 18/09/06Institut d’Électronique du Sud

Advances in 1/f noise modeling: Advances in 1/f noise modeling: 1/f gate tunneling current noise model of 1/f gate tunneling current noise model of

ultrathin Oxide MOSFETsultrathin Oxide MOSFETs

UMR 5507

Institut d’Électronique du Sud – CEM2 UMR 5507, Place E.Bataillon, U.M. II, 34095 Montpellier Cedex 5, France.

F. MARTINEZF. MARTINEZ, M.VALENZA, M.VALENZA

MOS – AK Montreux 18/09/06 22

IntroductionIntroduction

Reduction of oxide thickness Reduction of oxide thickness → → Increase of gate leakage currentIncrease of gate leakage current

• Limitation of classical characterization methodsLimitation of classical characterization methods• New noise sourcesNew noise sources

Low-frequency noise is a very sensitive tool for probing slow oxide trapsLow-frequency noise is a very sensitive tool for probing slow oxide traps

The gate to channel current noise must be taken into account in the The gate to channel current noise must be taken into account in the MOSFET noise characterization.MOSFET noise characterization.

We will show that our 1/f gate noise model can be applied to:We will show that our 1/f gate noise model can be applied to:• the characterization of slow oxide trapsthe characterization of slow oxide traps• compact noise modeling of MOSFETscompact noise modeling of MOSFETs

The off state drain current is dominated by the overlap gate leakage The off state drain current is dominated by the overlap gate leakage currentcurrent

• What about the overlap gate current LF noise ?What about the overlap gate current LF noise ?


OutlineOutline


Gate current low-frequency noise model and Gate current low-frequency noise model and

characterizationcharacterization

Drain and gate current LFN Comparison Drain and gate current LFN Comparison

Contributions of Channel Gate and Overlap Gate Currents Contributions of Channel Gate and Overlap Gate Currents

on 1/f Gate Current Noiseon 1/f Gate Current Noise

ConclusionConclusion


Gate current LF Noise MeasurementsGate current LF Noise Measurements

Experimental Set-UpExperimental Set-Up

ANALYSERANALYSER

HP89410A

A

Trans-impedance Trans-impedance AMPLIFIERAMPLIFIER

TRANSISTORTRANSISTOR

VVDSDSVVGSGS


Typical Gate Noise PSDTypical Gate Noise PSD

• 1/f noise level extracted at 1 Hz1/f noise level extracted at 1 Hz

• RTS noise observed on Gate currentRTS noise observed on Gate current


1/f Oxide Trapping noise Model1/f Oxide Trapping noise Model

Trapping – Detrapping model (McWhorter)Trapping – Detrapping model (McWhorter)

EC

EFn

EV

EC

EV

Ei

q

q

qVGB

n Poly +

SiO2

p Substrate

y

EF

PΨSΨ

22

,, 4 ,

1 ,

n

t n

n

F

n t F

F

E yS f y kT N E y

E y

0 exp y


1/f Gate Current Noise Model1/f Gate Current Noise Model

n

t

t F

N

kTN ES f

f 2

2FB

t FV

ox

kTN EqS f

C x z f

Fluctuation of the number Fluctuation of the number

of filled trapsof filled traps

Fluctuation Fluctuation

of the Flat Band Voltageof the Flat Band Voltage

Gate Current FluctuationsGate Current Fluctuations , ,GG GB

GB

dJI x t V x t W x

dV

Power Spectral Density Power Spectral Density of gate current noiseof gate current noise

0

22

2

,

with ,

G

G

G

LI

I

G tI

GB oxx

S x fS f dx

x

dJ q kT NS x f W x

dV C f

Power Spectral Density Power Spectral Density of gate current noiseof gate current noise

VVDSDS = 0 V = 0 V and and homogeneous structurehomogeneous structure

2 2

2G

G tI

GB ox

dI q kT NS f

dV WLC f


Devices Under TestDevices Under Test

Nitrided gate dielectric EOT = 1.2 nm Nitrided gate dielectric EOT = 1.2 nm • DPN process (Plasma Nitridation)DPN process (Plasma Nitridation)

nn+ + Polysilicon Gate (1200 Polysilicon Gate (1200 ÅÅ))

Isolated Devices with Individual ElectrodesIsolated Devices with Individual Electrodes

Constant Width of 10 µmConstant Width of 10 µm

L ranging from 40 nm to 10 µmL ranging from 40 nm to 10 µm

nMOS Transistors – 65 nm CMOS TechnologynMOS Transistors – 65 nm CMOS Technology


1/f Gate Current Noise Model1/f Gate Current Noise ModelExperimental ValidationExperimental Validation

Slow Oxide trap density Slow Oxide trap density extracted fromextracted from

Low frequency Low frequency gategate noise noise measurementsmeasurements

NNT T (E(EFF) ) 1 10 1 101818 cm cm-3-3 eV eV-1-1


Impact of Drain Voltage on LF Gate Current NoiseImpact of Drain Voltage on LF Gate Current Noise

There is noThere is no low-frequency induced gate noise from channel current noise low-frequency induced gate noise from channel current noise

nMOSnMOSW / L = 10 / 0.2 µmW / L = 10 / 0.2 µm


Gate RTS NoiseGate RTS Noise

Time and Spectral signature of Oxide Single DefectTime and Spectral signature of Oxide Single Defect

f (Hz)100 101 102 103 104 105

SI G

(f)

(A

2 /H

z)

10-23

10-22

10-21

10-20

10-19

(b)

W / L = 10 / 10 µmW / L = 10 / 10 µmNo RTSNo RTS noise observed on noise observed on Drain CurrentDrain Current

RTSRTS noise observed on noise observed on Gate CurrentGate Current

Single defect Single defect characterisation characterisation

by RTS by RTS GateGate current current noise measurementsnoise measurements


Gate RTS NoiseGate RTS Noise

exp

,

nt F

en inv t

E E

kT

f N T y

1

,cn inv tf N T y

EC

EF

nE

VEC

EV

Ei

q

q

qVG

B

n+ Poly

SiO2

p Substrat

Y yt

EF

Et0

SΨPΨ

S.R.H. StatisticsS.R.H. Statistics

Surface Surface PotentialPotential

Model Model

xxtt (nm) (nm) EET0T0 (eV) (eV) EEB B (eV)(eV) 00 (cm²) (cm²)

0.10.1 2.952.95 0.40.4 5 105 10-20-20

Typical Characteristics Typical Characteristics of Nitrogen-related Trapof Nitrogen-related Trap(C. Leyris WoDim 2006)(C. Leyris WoDim 2006)


OutlineOutline









Comparison of SComparison of SVFBVFB(f) extracted from(f) extracted fromDrain and Gate noise measurementsDrain and Gate noise measurements

The The samesame Flat Band Voltage fluctuations Flat Band Voltage fluctuations are involved are involved

in in draindrain and and gategate current LF noise current LF noise

nMOS W / L = 10 / 1 µmnMOS W / L = 10 / 1 µmDrainDrain Current LF noise Current LF noise

nMOS W / L = 10 / 1 µmnMOS W / L = 10 / 1 µmGateGate Current LF noise Current LF noise


Devices Under TestDevices Under Test

Nitrided gate dielectric EOT = 12 Ǻ

RTN process (Rapid Thermal Nitridation)

n+ Poly-silicon Gate (1200 Ǻ)

nMOS TransistorsnMOS Transistors

Isolated Devices with Individual Electrodes

Constant Width of 10 µm

L ranging from 0.04 to 10 µm

Standard devices

Bulk

Gate stack

Channel engineering

Devices parameters

Strained devices

Si0.8Ge0.2


Drain current noise measurementsDrain current noise measurements

SVG(f) obtained from the drain noise model are independent of the gate biases

1/f behavior is observed An average value of was found around 0.8 Trap density exponentially decreases when moving away from Si/SiON interface*

Flat band voltage PSD extracted from drain current noise in strong inversion regime

*[JAYARAMAN and SODINI, Trans. Electron Devices, 1990]

W/L = 10 µm / 0.34 µm

≈ -0.8


Gate current noiseGate current noise

Gate current noise level at f = 1 Hz for two gate lengths, VDS = 25 mV

Data are extracted from the strong inversion regime Levels obtained at f = 1 Hz are in good agreement with the proposed gate noise model

G fb

2

GI V

GB

dIS (f) S (f)

dV


Comparison of SComparison of SVfbVfb(f) from gate and drain current noise (f) from gate and drain current noise

Same values of SVfb(f) due to the same trapping process are obtained for frequencies below 1 kHz

Full shot noise (2qIG) dominates the gate noise above 1 kHz

VDS = 25 mV

The The samesame Flat Band Voltage fluctuations are involved in Flat Band Voltage fluctuations are involved in draindrain and and gategate current LF noise current LF noise

VGS = 0.95 V

10 x 1 µm²

VGS = 0.65 V

10 x 0.34 µm²


Strained-channel vs. standard n-MOSFETs Strained-channel vs. standard n-MOSFETs

Normalized Flat band voltage fluctuation PSD SVfb x W x L extracted from drain and gate current noise for both strained and standard devices.

Good accordance of results achieved for several gate lengths As the same gate stack process was used for both architectures

The slow oxide trap densities involved in LFN are not affected by channel engineering

VDS = 25 mV

VGS = 0.8 V


Impact of Gate LFN on Drain LFNImpact of Gate LFN on Drain LFN

W / L = 10 / 10 µmW / L = 10 / 10 µmFluctuation Continuity EquationFluctuation Continuity Equation

,,G

d i x tW J x t

dx

Drain and Source LFN PSDDrain and Source LFN PSD

2 2

2 22 2

2 2 20 0

1D

L Lt t GD

I S effinv ox GBx x

q kTN q kT N dJI R xS f µ dx W dx

WL f Q q C f L dV

2 222 2 2

2 20 0

11

S

L LS t t G

I S effinv ox GBx x

I q kTN q kT N dJR xS f µ dx W dx

WL f Q q C f L dV


LF Gate-Source noise modelLF Gate-Source noise model

Electrical Modeling of LF Gate Current NoiseElectrical Modeling of LF Gate Current Noise

Noiseless

MOSFET

Gate Drain

Source Source

SIGS SID

BSIM4 LF Drain Current NoiseBSIM4 LF Drain Current NoiseBased on Based on N-N-µ Modelµ Model

3 noise parameters : 3 noise parameters : NOIA NOIB NOICNOIA NOIB NOIC

NOIA = NNOIA = Ntt(E(EFF) in units of J) in units of J-1-1 m m-3-3

SIGD

2

20

,G

GD

LI

I

S x fxS dx

L x

2

0

,1 G

GS

LI

I

S x fxS dx

L x

LF Gate-Drain noise modelLF Gate-Drain noise model

CorrelationCorrelation

0

,1 G

GD GS

LI

I I

S x fx xS dx

L L x


OutlineOutline









p-MOSFET Gate Leakage Currentp-MOSFET Gate Leakage Current

-VGS (V)0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

I D, I

S, I

G, I

B (

A)

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

ID

IS

IG

-VGS (V)

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Cur

rent

s (A

)

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

ID

IS

IG

IB

N

P+P+

P+VD=-1V

IGC IGDO

VGS

Saturation Range VSaturation Range VDSDS = -1 V = -1 V

N

P+P+

P+

VD=-25 mV

IGC IGDO

VGS

Low drain bias VLow drain bias VDS DS = -25 mV= -25 mV


Gate to Channel Current Noise Gate to Channel Current Noise Characterization at low drain biasCharacterization at low drain bias

IG (A)10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4

Wef

f*L

eff*

SI G

(f)

(m2 .A

2 /Hz)

10-4010-3910-3810-3710-3610-3510-3410-3310-3210-3110-3010-2910-2810-2710-26

10x100.3x1010x1010x0.310x1

(2)

N

P+

P+

VD=-25 mVIGC

VGS

P+

VVDSDS = -25 mV = -25 mV

Gate to Channel Gate to Channel

leakageleakage

SSVFBVFB Extraction Extraction

A single value of SA single value of SVFBVFB x WL x WL

allows to simulate the gate allows to simulate the gate

current noise of studied current noise of studied

devices:devices:

20 2 23 10 V m /HzFBVS W L

2

G

GI VFB

GB

dIS f S

dV


Gate to Channel Current Noise Gate to Channel Current Noise Characterization in Saturation RangeCharacterization in Saturation Range

HUNT2 (PLI1032 D16) LA(D & F) PMOSComparaison 1-C4 & D4 10x10, 2-C4 1x10, 3-D3 7x10, 4-B2 10x1,

VD=-1V, WxLxSIG(1 Hz)=f(-IG)

IG (A)10-11 10-10 10-9 10-8 10-7

WxL

xSI G

(f=

1 H

z) (

µm

2 .A2 /H

z)

10-27

10-26

10-25

10-24

10-23

10-22

10-21

10-20

10-19

10 x 10 µm2

1 x 10 µm2

7 x 10 µm2

10 x 1 µm2 (2)

NP+

P+

P+

VD=-1VIGC

VGSVVDSDS = -1 V = -1 V

Gate to Channel Gate to Channel leakageleakage Same Same SSVFBVFB x WL x WL Value for Value for

Saturation RangeSaturation Range

20 2 23 10 V m /HzFBVS W L

2

G

GI VFB

GB

dIS f S

dV


Gate to Drain Overlap Current Noise Gate to Drain Overlap Current Noise Characterization (1/2)Characterization (1/2)

NP+P+

P+

VDSIGC

VGS=0

HUNT2 (PLI1032 D16) C4 & D4 & F3 LAF PMOSW=10, L=10, SIG

(1 Hz)=f(-IG)

IG (A)10-11 10-10 10-9 10-8 10-7

S I G(f

=1 H

z) (

A2 /H

z)

10-28

10-27

10-26

10-25

10-24

10-23

10-22

10-21

VDS = -1 V, VGS varies

VGS = 0 V, VDS varies (2)(2)

HUNT2 (PLI1032 D16) B2 & D2 LAD PMOSW=10, L=1, SIG

(1 Hz)=f(-IG)

IG (A)10-11 10-10 10-9 10-8 10-7

SI G

(f=

1 H

z) (

A2 /H

z)

10-28

10-27

10-26

10-25

10-24

10-23

10-22

10-21


VGS = 0 V, VDS varies

(2)

W/L = 10 µm / 10 µmOV

Overlap Length

L 15nm

W/L = 10 µm / 1 µm


Gate to Drain Overlap Current Noise Gate to Drain Overlap Current Noise Characterization (2/2)Characterization (2/2)

Extraction of SExtraction of SVFBVFB for for

different Widths different Widths

and L =10 µmand L =10 µm

IG (A)10-11 10-10 10-9 10-8

WxS

I G(f

=1

Hz)

(µ

m.A

2 /Hz)

10-30

10-29

10-28

10-27

10-26

10-25

10-24

10-23

10-22

10-21

10 x 10 µm2

1 x 10 µm2

7 x 10 µm2

10 x 1 µm2

ModelModel

2

0G

G

GI VFB

DS V

dIS f S

dV

20 2 23 10 V m /HzFBV OVS W L

OVOverlap Length L 15nm

The same Normalized SThe same Normalized SVFBVFB is used to model is used to model

the gate overlap current LF noise the gate overlap current LF noise

NP+P+

P+

VDSIGC

VGS=0


Gate Current Noise (On/Off state)Gate Current Noise (On/Off state)Circuit Design point of viewCircuit Design point of viewHUNT2 (PLI1032 D16) C4 & D4 & F3 LAF PMOS

W=10, L=10, SIG(1 Hz)=f(-IG)

IG (A)10-11 10-10 10-9 10-8 10-7

S I G(f

=1 H

z) (

A2 /H

z)

10-28

10-27

10-26

10-25

10-24

10-23

10-22

10-21


VGS = 0 V, VDS varies (2)(2)

HUNT2 (PLI1032 D16) B2 & D2 LAD PMOSW=10, L=1, SIG

(1 Hz)=f(-IG)

IG (A)10-11 10-10 10-9 10-8 10-7

SI G

(f=

1 H

z) (

A2 /H

z)

10-28

10-27

10-26

10-25

10-24

10-23

10-22

10-21


VGS = 0 V, VDS varies

(2)

-VGS (V)0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

I D, I

S, I

G, I

B (

A)

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

ID

IS

IG

-VGS (V)0.0 0.2 0.4 0.6 0.8 1.0

Cur

rent

s (A

)

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

ID

IS

IG

W/L = 10 µm / 10 µm W/L = 10 µm / 1 µm

VDS= -1 V VDS= -1 V

1/f gate noise is higher in the off-state than in the on-state 1/f gate noise is higher in the off-state than in the on-state for short channel devicesfor short channel devices


OutlineOutline










The 1/f gate current noise model involves slow oxide trapsThe 1/f gate current noise model involves slow oxide traps

Extraction of slow oxide trap densities by gate current noise measurementsExtraction of slow oxide trap densities by gate current noise measurements

Good agreement with slow oxide trap densities extracted from drain current noiseGood agreement with slow oxide trap densities extracted from drain current noise• The same Flat Band voltage fluctuations are involved in both gate and drain LF noiseThe same Flat Band voltage fluctuations are involved in both gate and drain LF noise

For short channel devices, gate current LF noise can be higher in the off-state than in the For short channel devices, gate current LF noise can be higher in the off-state than in the on-state.on-state.

Implantation in MOSFET compact model Implantation in MOSFET compact model • Formulation with NOIA BSIM4 noise parameter and gate LF noise partitionFormulation with NOIA BSIM4 noise parameter and gate LF noise partition

mos – ak montreux 18/09/06 institut dÉlectronique du sud advances in 1/f noise modeling: 1/f gate...

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