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MOS Channel ResistanceMOS Channel Resistance

• From previous analysis of CMOS deviceFrom previous analysis of CMOS deviceIIdsds = = ((V((Vgs gs – V– Vtt)V)Vdsds – V – Vdsds

22/2) /2)

RRcc = = (V(Vgsgs – V – Vtt), where ), where =(=(/t/toxox)(W/L))(W/L)

• However, VHowever, Vgsgs varies over input, and (V varies over input, and (Vdsds22/2) may not be /2) may not be

ignored.ignored.• Use SPICE to compute average resistance.Use SPICE to compute average resistance.

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MOS CapacitanceMOS Capacitance

Accumulation CC00 = = sio200 A / t A / toxox Depletion CCdepdep = = si00 A / d A / d

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MOS CapacitorMOS Capacitor

Inversion

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MOSFET CapacitanceMOSFET Capacitance

• Depletion Capacitance:Depletion Capacitance: CCdepdep = = SiSi 00 A/d A/d, , SiSi = 12, = 12, dd = depletion layer depth = depletion layer depth

• Total Total CC between gate & substrate between gate & substrate C Cgbgb

• CC00 in series within series with C Cdepdep

• CCgbgb = C = C00 Accumulation ModeAccumulation Mode

• CCgbgb = C = C00 C Cdep dep /(/(CC00 + C + Cdepdep) Depletion Mode) Depletion Mode

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MOSFET CapacitanceMOSFET Capacitance

• In inversion, there is a limited supply of charge carriers In inversion, there is a limited supply of charge carriers to the inversion layer, so it cannot track rapid voltage to the inversion layer, so it cannot track rapid voltage changes.changes.

• Dynamic Dynamic CC is the same as for depletion is the same as for depletion• CCgbgb = C = C00 {{f < f < 100100 Hz Hz}}

= C= C00 C Cdepdep/(C/(C00 + C + Cdepdep)=C)=Cminmin {{high f high f } }

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MOSFET CapacitancesMOSFET Capacitances

• Logic Gate load capacitance has 3 C’s in parallel Logic Gate load capacitance has 3 C’s in parallel between gate output & substrate:between gate output & substrate:

1.1. Transistor gate capacitance (of other gate inputs Transistor gate capacitance (of other gate inputs connected to this gate output)connected to this gate output)

2.2. Diffusion capacitance of transistor drains connected to Diffusion capacitance of transistor drains connected to gate outputgate output

3.3. Routing capacitance of wires connected to the outputRouting capacitance of wires connected to the output

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MOSFET Parasitic CapacitancesMOSFET Parasitic Capacitances

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CapacitancesCapacitances

• CCgsgs, C, Cgdgd = = gate to channel capacitances, lumped at gate to channel capacitances, lumped at source & drainsource & drain

• CCsbsb, C, Cdbdb = = source & drain diffusion capacitances to bulk source & drain diffusion capacitances to bulk

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Approximation of Intrinsic MOS Approximation of Intrinsic MOS CapacitancesCapacitances

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Capacitance CalculationCapacitance Calculation

1.1. Off region, Off region, VVgsgs < V < Vtt, no channel so , no channel so CCgsgs = C = Cgdgd = 0 = 0

• CCgbgb = C = C00 C Cdepdep

CC00 + C + Cdepdep

2.2. Non-saturated (linear) region Non-saturated (linear) region VVgsgs = V = Vtt V Vdsds

Constant depletion layer depth, channel forms, Constant depletion layer depth, channel forms, CCgsgs, , CCgdgd become become significantsignificant

• CCgdgd = C = Cgsgs 11 00 SiO2SiO2 A A

2 2 ttoxox

• CCgb gb 00

(( ))

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Capacitance Calculation (cont’d.)Capacitance Calculation (cont’d.)

3.3. Saturated region Saturated region VVgsgs – V – Vtt < V < Vdsds

• Channel heavily inverted, drain pinched off, Channel heavily inverted, drain pinched off, CCgdgd = 0 = 0

• CCgsgs = 2 = 2 00 SiO2SiO2 A A

3 3 ttoxox

(( ))

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Long Channel C VariationLong Channel C Variation

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Short Channel C VariationShort Channel C Variation

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Saturation CapacitanceSaturation Capacitance

• CCgdgd = finite in saturation due to channel side fringing = finite in saturation due to channel side fringing fields between gate & drainfields between gate & drain

• Approximate Approximate CCgg as as CC00 = C = Coxox A A

• CCoxox = = 00 SiO2SiO2/t/toxox

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Calculation of Calculation of CC from Geometry from Geometry• Unit TransistorUnit Transistor• Diffusion capacitance to substrateDiffusion capacitance to substrate

CCdd = C = Cjaja •• ( (a ba b) ) + C+ Cjpjp • • (2(2aa + 2 + 2bb))

CCjaja = = junction C per junction C per mm22

CCjpjp = = periphery C per periphery C per mm

a =a = diffusion width diffusion width

b =b = diffusion length diffusion length

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Capacitance in TransistorCapacitance in Transistor

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CC Dependence on Junction Dependence on Junction VV

• CCjj = C = Cj0j0 1 –1 – VVj j -m-m

VVbb

• VVjj = junction voltage = junction voltage (< 0 for reverse bias) (< 0 for reverse bias)

• CCj0j0 = zero bias C = zero bias C ( (VVjj = 0 = 0))

• VVbb = built-in junction potential = built-in junction potential

• mm is constant, depends on impurity distribution near is constant, depends on impurity distribution near junction, and whether junction is bottom or sidejunction, and whether junction is bottom or side

(( ))

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A Practical MethodA Practical Method

• It is not easy to compute the RC values of deviceIt is not easy to compute the RC values of device– Rs and Cs depend on VRs and Cs depend on Vgsgs, which changes over time, which changes over time

– sRS and Cs consists of several parts in serial or parallelsRS and Cs consists of several parts in serial or parallel

• SPICE simulationSPICE simulation– Apply an input waveform of certain frequency, and Apply an input waveform of certain frequency, and

measure the current and voltage to derive average R measure the current and voltage to derive average R and Cand C

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Distributed Distributed RCRC Effects Effects• Signal propagation along wire influenced by:Signal propagation along wire influenced by:

– Distributed Distributed R R andand C C– Impedance of driverImpedance of driver– Impedance of loadImpedance of load

• Transmission line effect – very bad for poly, Transmission line effect – very bad for poly, polysilicide, diffusion, and heavily-loaded metal wirespolysilicide, diffusion, and heavily-loaded metal wires

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Delay EquationsDelay Equations

• Consider propagation time Consider propagation time ttxx of x sections. From of x sections. From discrete analysis:discrete analysis:

ttnn = RC n = RC n ( (nn + 1)/2 , + 1)/2 , nn = # wire sections = # wire sections

• In the limit as In the limit as tt = rcl= rcl2 2 / 2, / 2, where where l is l is wire lengthwire length

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Inserted Buffer in Long WireInserted Buffer in Long Wire

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Example Example • 2 mm wire with buffer of delay 2 mm wire with buffer of delay bufbuf

• ttpp = propagation delay, = propagation delay, rr = 20 = 20 / / mm• cc = 4 X 10 = 4 X 10-4-4 pF / pF / m, r c / 2 = 4 X 10m, r c / 2 = 4 X 10-15-15 sec / sec / mm22

• With buffer:With buffer: ttpp = 4 X 10 = 4 X 10-15-15 (1000) (1000)22 + + bufbuf + 4 X 10 + 4 X 10-15-15 (1000) (1000)22

= 8 nsec + = 8 nsec + bufbuf

• No buffer:No buffer: ttpp = 4 X 10 = 4 X 10-15-15 (2000) (2000)22 = 16 nsec = 16 nsec• Keep Keep bufbuf small (a buffer is 2 cascaded inverters)small (a buffer is 2 cascaded inverters) SegmentedSegmented bus with buffers can be much faster than unbuffered bus bus with buffers can be much faster than unbuffered bus

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Capacitance Design GuideCapacitance Design Guide• 1 1 m (m ( = 0.5 = 0.5 mm), ), nn-well process-well process• Double Double CC of wires to account for fringing of wires to account for fringing

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Wire Length GuideWire Length Guide

• Want Want wirewire << << gategate, so , so ll << 2 << 2 gategate

r cr c

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New VLSI Component -- InductorNew VLSI Component -- Inductor

• Appeared because Appeared because shank, shank, ff 2 GHz 2 GHz• Chip bond wire inductance is a problemChip bond wire inductance is a problem• On-chip wire inductance only a problem when:On-chip wire inductance only a problem when:

– Signal-carrying wire runs next to noisy Signal-carrying wire runs next to noisy VVDDDD/V/VSSSS supply wire – noise supply wire – noise couples inductivelycouples inductively

• Can cause logic errorsCan cause logic errors

• Inductance of cylindrical wire above ground plane:Inductance of cylindrical wire above ground plane:– L = L = lnln 4h 4h (use for wire bonds and package pins) (use for wire bonds and package pins) 22 d d– = wire magnetic permeability ( ~ 1.257 X 10= wire magnetic permeability ( ~ 1.257 X 10-8-8 H/cm) H/cm)– h = height above ground planeh = height above ground plane– d = wire diameterd = wire diameter

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Inductance of On-Chip WireInductance of On-Chip Wire• LL = = ln 8 ln 8hh + + ww 22 ww 4 4hh• ww = conductor width = conductor width• hh = height above substrate = height above substrate• Package inductance values supplied by manufacturerPackage inductance values supplied by manufacturer• Get an inductive voltage spike on a bond wire when you draw a large Get an inductive voltage spike on a bond wire when you draw a large

current in a short timecurrent in a short time• ddVV = L= L d dII ddtt• For high-speed chips, keep inductance down so that we don’t disturb For high-speed chips, keep inductance down so that we don’t disturb VVDDDD

• MUST ACCOUNT FOR THIS AT 200 MHz OR HIGHERMUST ACCOUNT FOR THIS AT 200 MHz OR HIGHER

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Inductance ExampleInductance Example

• For an on-chip wire, For an on-chip wire, hh = 1000 = 1000 mm ( (1 mm1 mm thick chip) thick chip)• LL = 1.257 X 10 = 1.257 X 10-8-8 ln 8 X 1000 + 1 ln 8 X 1000 + 1 22 1 4000 1 4000 = 1.8 x 10= 1.8 x 10-9-9 H/mm H/mm• Defeat Defeat LL by: by:

1.1. Reducing height above ground plane of wire bond (use Reducing height above ground plane of wire bond (use top metal layer as ground plane)top metal layer as ground plane)

2.2. Increasing wire diameterIncreasing wire diameter

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