mosfet fabrication: process design, artwork, fabrication

8/13/2019 MOSFET Fabrication: Process design, artwork, fabrication

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Fabrication of Metal Oxide Semiconductor Field Effect Transistors

(MOSFET) using self-aligned silicide (SALICIDE) technology

Amir Hassani

Professor: Dr. Mehmet C. Ozturk


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1. AbstractMOSFET transistors are the building blocks in semiconductor industries. They canbe found everywhere as in RF microelectronic circuits, amplifiers, and digital

circuits. In this lab, we fabricated MOSFET transistors as well as some other

structures such as MOS capacitors, gated-diodes, and comb-like structures for

sheet resistance measurements. For better contact resistance we formed self-

aligned silicide (SALICIDE) contacts of Ti by two different annealing steps using

rapid thermal annealing (RTA) for C49 and C54 phase formation. We then

characterized our devices using sheet resistance, C-V, and current-voltage

measurements. Because of an issue introduced to polysilicon layer during

deposition process, we then switched to transistor devices fabricated in previous

semester. We then characterized them for different Width to Length ratios and

tabulated the results for better comparison.

2. Wafer cleanJust like every other Si-based device fabrication, we had to clean our double-

sided polished wafers to prepare them for process. oriented Phosphorus

doped Si wafers which were about 500-550 micrometers thick were cleaned using

standard JTBaker wafer clean. The purpose of this process is to remove native

oxide layer and all other organic contaminations.

3. Oxide GrowthAs the second step towards Module 3 device fabrication (MOSFETs, Ring

MOSFETs, Capacitors, etc.) we had to grow a thermal oxide layer on our Si

wafers. This time, in contrast to Module 2 oxide growth, we used dry oxidation

because the targeted oxide layer required to be as high quality and dense as gate

oxide in MOSFET fabrication. Dry oxidation has a lower growth rate but on the

other hand a higher quality as well as a higher density oxide will be resulted after

oxidation. Cleaned wafers were loaded into dry oxide quartz tube for a target oxide

thickness of 30 nm. Six wafers were used for our main purpose of device


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fabrication and two other wafers were used for oxide thickness monitoring and wet

etch tests.Dry oxidation in general, follows the equation below.

Then monitor wafer were measured using Nanospec Nanometrics and

measurements results are listed in the Table. 1 below:

Front 345 A 349 A 348 A 350 A 349 ABack 334 A 336 A 335 A 340 A 337 A

Based on the above measurements we can see that the average thickness of the

oxide is about 23 nm both on the front and back sides of the wafer.

4. Polysilicon depositionIn order to deposit polysilicon we used Low Pressure Chemical Vapor

Deposition first which resulted in poor polysilicon properties. This was obviousthrough some random color changes on the poly-deposited wafers and

inconsistency in etch tests. As reported by staff, there had also been pressure

fluctuations in LPCVD furnace while they attempted for polysilicon deposition. As

another option we decided to use a Physical Vapor Deposition method instead of a

Chemical Vapor Deposition one. Staff crushed a Si wafer and put them in a

graphite crucible and used 4 ebeam evaporation tool. The output power provided

by this system is less than the new 6 ebeam tool and this system provided a two

wafer option. For polysilicon deposition ebeam chamber, was pumped down toapproximately Torr. A beam current of 56-80 mA was used for

polysilicon evaporation at the above mentioned pressure. The deposition rate,

controlled by a crystal quartz monitor, was kept at 0.2-0.6 A/sec for a target

polysilicon thickness of 200 nm. Then, nanometrics was used to measure the

polysilicon thickness and it was recorded to be 220 nm after polysilicon etch.

However, because there was no rotation involved in the process during ebeam

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evaporation, there was much more thickness non-uniformity of polysilicon layer in

comparison to conventional LPCVD poly.

5. Photo Lithography First stepIn order to define doping areas, we spun 1813 positive photo resist, using

headway spinner, on front side of the wafer which already had grown oxide and

deposited polysilicon layers on top. Then we baked the photoresist on a hotplate

set to 115C for one minute. To pattern the photoresist we used the mask pattern

shown in Fig. 1 using a transparency mask and then we exposed the photoresist to

UV light for 3.5sec using MA6/BA6 contact aligner. This contact aligner uses 280-

350 nm light to expose wafers up to 150mm of diameter. You can find detailed

description of zones in Fig. 2, 3, 4, and 5 below.

1 =


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The patterned photoresist was then developed in MF-319. Fig. 6 shows the

schematic diagram of the structure after oxidation, polysilicon deposition, and

photoresist development.

6. Polysilicon and oxide wet etchAfter developing photoresist, we wet etched the polysilicon layer in the defined

spots using mixture of Nitric acid, ammonium fluoride, and water. The etch time

for polysilicon layer was around 1 min. After rinsing the devices using DI water

we put them in Buffered Oxide Etch tank for etching the oxide layer underneath.

We used BOE with a 10:1 ratio of ammonium fluoride (NH4F) as the buffering

agent, and hydrofluoric acid (HF). Etch time was around1 minute. Concentrated

HF (typically 49% HF in water) etches silicon dioxide too quickly and also peels

photoresist used in lithographic patterning. Buffered oxide etch is commonly used

for more controllable etching.After etching was accomplished, resist was stripped

using NMP for 3 minutes. Fig. 7 show the schematic diagrams of the structure after

polysilicon/oxide wet etch and photoresist strip.

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7. Doping and dopant diffusionP-doped regions were formed using Boron disk doping. Boron disk doping was

achieved using Tylan Furnace D2 and GS-126 solid Boron source disks

manufactured by Techneglas. Every two wafers were placed between source disks

and doping was accomplished at 950C for 3 hours and in a 4000 sccm flow of

Nitrogen gas (N2). Then wafers were put in BOE bath for 2 and half minutes to

remove the glass layer, 160 nm thick, formed during Boron doping. Fig. 8 shows

the schematic structure of device wafers after Boron diffusion and glass etch.

7 /

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8. Deposition of second oxide layerWe deposited a second oxide layer to define our reactive areas. Reactive areas

were the places which we wanted to react with Ti layer and form our self-aligned

titanium silicide, TiSi2, contacts which will be described later. For this purpose we

used 6 ebeam evaporator. This system is a high power (6keV) system which is

equipped and modified with a cooling chuck to avoid excess baking of photoresist

(usually lift-off resist).

For oxide deposition, the system was pumped down to Torr. This low

pressure was achieved using A. Mechanical pump - Down to mTorr range, B.

Turbo pump - Quick pump down to Torr range, and C. Cryogenic pump -

down to Torr. During evaporation a 103mA emission current was kept for

a 6 A/sec deposition rate which was controlled by a quartz crystal monitor leveled

as the same height as the wafer holder. Deposition was only done on front side of

the wafer, aiming at 100 nm which was accurately measured to be 1050 A usingone monitor wafer. It is again worth to mention that we had six device wafers and

one monitoring wafer for this process.

9. Photo Lithography second stepAfter the deposition of second oxide layer, we did another photolithography

step to define areas in which we want to form Self-Aligned Silicide (SALICIDE)

contacts which will be described later. We spun 1813 positive photo resist, using

headway spinner, on front side of the wafer. Then we baked the photoresist on a

hotplate set to 115C for one minute. To pattern the photoresist we used the mask

pattern shown in Fig. 9 using a transparency mask and then we exposed the

photoresist to UV light for 3.5sec using MA6/BA6 contact aligner.


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This mask, just like Fig. 1 is consisted of 4 zones and they both together give us

artwork demonstrated in Fig. 10. We will use the comb structures of Zone 3 for

sheet resistance measurements and the snake structures represent our diodes. The

patterned photoresist was then developed in MF-319. Then oxide layer was wet

etched in BOE with a ratio of 10:1 for 30 seconds to remove the oxide layer in

places where wanted to form SALICIDE. Then the photoresist was stripped using

NMP for 3 minutes. Fig. 11 shows the device structure after A. Photoresist

development, B. Oxide etch, and C. Photoresist strip respectively.

9 =


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10 =

11 2 , ,

,


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10.DC Sputtering of TitaniumAfter defining the etch holes through the second oxide layer, it was now time to

deposit the top Ti layer. For this purpose we used DC sputtering which is

extensively used for metals deposition. It is worth to mention that DC sputtering

cannot be used for deposition of dielectric materials. RF sputtering is instead used

for deposition of both metals and dielectric materials. DC sputtering introduces the

advantage of a colder process in comparison to evaporation and is suitable for

applications where excess baking of photoresist is not desirable (e.g. lift-off).

Sputtering also provides a more conformal deposition. In this process ionic plasma

by applying a high voltage to a glow tube is created. Then, Ions bombard the target

material at the cathode (Ti target).Target atoms are then ejected (sputtered) from

the cathode by energy and momentum transfer. Sputtered atoms from the target are

then deposited on to the substrate (anode). In this process, we aimed at a 200 nm

thickness of Ti and 30 standard cubic centimeters (sccm) flow of Ar at a pressure

of 35 mTorr was used for about 6 minutes to sputter the target atoms. The DC

voltage and current measured where 350 V and 0.2 A respectively.

11.Rapid Thermal Anneal (RTA) First stepAfter DC sputtering of Ti, we annealed the deposited Ti at 650Cfor 30 seconds

to form C49 phase TiSi2 where Ti layer sees Si underneath (e.g. Source/Drainjunctions, polysilicon gate). Annealing of Ti at this temperature based on Fig. 12

gives us a C49 phase which has a higher resistivity and therefore is not suitable for

low resistivity contacts. In Table. 1, you can find the sheet resistance of C49 phase

TiSi2measured using Four-point probe. There were two big squares embedded on

the wafers for the purpose of TiSi2sheet resistance measurements.


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Applied Current Measured Voltage Measured Sheet Resistance

Right Square 1 mA 5.746 mV 26.05 /sq.

Left Square 1 mA 5.651 mV 25.6 /sq.

12.Unreacted Ti selective wet etchAfter the first annealing step, we etched the unreacted Ti layer in a mixture of

1500 mL of DI water, 300 mL of Ammonium Hydroxide, and 300 mL of

Hydrogen Peroxide which took us about 8 minutes to etch thoroughly the

unreacted Ti which was around 200 nm so it gave us an etch rate of about 25

nm/min.

12 2

1 1


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13.Rapid Thermal Anneal Second stepAfter etching the unreacted Ti we rinsed the wafers and put them in spin drier to

dry. Then, we did another anneal at 800Cfor 30 seconds to convert the C49 phase

TiSi2into a much lower resistivity C54 phase (Fig .12). In Table. 2, you can find

the values of TiSi2sheet resistance measured using Four-point probe.

Applied Current Measured Voltage Measured Sheet Resistance

Right Square 1 mA 1.132 mV 5.123 /sq.

Left Square

1 mA 1.336 mV 6.057

/sq.

Fig. 13 shows the structure after A. Ti deposition; B. TiSi2 formation, and C.

Unreacted Ti wet etch.

13 , ,

2 2 (54)


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14.Back-side Aluminum depositionFinally we deposited a 40 nm thick Al on wafers back side to serve as out

substrate contact. Al was deposited using DC Sputtering while 30 sccm of Ar was

fed into the chamber (52.3 mTorr) and deposition was achieved at a DC voltage of

425V and a DC current of 0.2A for 12 minutes.

15.MeasurementsIn order to demonstrate the four different stack-ups which existed in our wafers,

we have to take another close look at Fig. 10. I have also provided another picture

(Fig. 14) which better demonstrates the colors which I will be assigning to each

different stack-up. As you see in Fig. 14, after aligning the two layers of mask on

top of each other (First Doping, Second Silicide), we will face 4 different colors

corresponding to a specific stack-up of layers. The colors of interest are White,

Red, Purple, and Green.

14 , ,


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You can find the schematic diagram of these four different stack-ups in Fig. 15

below.

As obviously shown in Fig. 14, there are four different structures that can be used

for four-point measurements. Structures 1 and 3 (Fig. 14) can be used for P+region

sheet resistance while structure 1. Structure 1 is preferred over structure 3, becausein structure 3 there is TiSi2 layer in parallel with P

+ region over all the comb

structure and it gives us the resistance of these two layers in parallel. So for

accurate P+resistance measurement it is better to use structure 1.

Same thing is also applicable to structures 2 & 4 which are designed for

polysilicon sheet resistance measurement. In structure 4 we have polysilicon in

15 , , ,


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parallel with TiSi2all over the comb structure and if we do any measurements, we

are measuring the resistance of these two layers in parallel. With the same

reasoning, structure 2 is preferred over structure 4 for polysilicon sheet resistancemeasurement.

A.Sheet Resistance Measurement DataWe first measured sheet resistance of P+region using Structures 1 and 3. As

mentioned before we expect a lower resistance from structure 3 due the parallelism

of TiSi2 and P+ regions in this comb structure. We used SIGNATONE probe

station for our I-V measurement. The middle fingers of these structures were used

to measure the voltage and the outer fingers were used to apply a current. We then

sketched the V-I curves for 3 different spots on the wafer and measured Resistance

value from the curves. We then know that:

Based on this formula we can form 2 equations with 2 unknowns and then solve

for Rsheetand Rcontact. But just because our L/W is always constant (Middle fingers)we are essentially forming the same equation all the time which does not help us to

calculate Rsheetand Rcontact. We should have used probe configurations for different

L/W ratios instead. Any ways, we can now make an assumption that contact

resistance is negligible and we can approximate R with:

Based on the information from artworks each comb structure is consisted of 11

0.5x0.5mm squares. Based on the configuration used for probs (Fig. 16) we can

say,

3


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You can find the sheet resistance values for structure 1 (P+region covered by oxide

layer) in Table. 3 below.

Spot No. R () Rsheet (/sq.)

Spot 1 48.875 16.292

Spot 2 47.79 15.93

Spot 3 48.83 16.277

For further information, I have also included the V- I curves in Appendix A. V-I

curves are sketched using MATLAB and I have used Data Cursors to measure the

slope of the V-I curve for R (See Table. 3) calculations.

Although, I mentioned earlier that structure 3 is not a good structure for P+region

resistance measurement (P+ in parallel with TiSi2) but I have included the

measurements in Table. 4 below for comparison purposes. As obviously shown

Sheet resistance, for P+region, calculated using this structure is much lower and iscaused by parallel TiSi2layer.

Spot No. R () Rsheet (/sq.)

Spot 1 40 13.33

Spot 2 25.57 8.52

Spot 3 32.45 10.82

3 , , 1

4 , , 3

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MATLAB plots for structure 3 can be found in Appendix B.

We then attempted to measure the sheet resistance for polysilicon layer from

structures 2 and 4 but we were not able to measure the resistance. Al most all of

the curves showed a step-like V-I behavior as shown in Fig. 17.

We also attempted to measure the polysilicon layer sheet resistance using a two-

probe configuration and we were only able to measure in a single spot using

structure 2. The resulted V-I curve is shown in Fig. 18 below. This gave us an R =

97.44 and a sheet resistance of Rsheet

= 32.48 for polysilicon layer. This was

the only valid data we obtained for polysilicon layer using a two-probe

configuration.

17 4


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We also measured the I-V curve of gate-controlled snake-shaped diodes atVG = 0 (Fig. 19). As you may have noticed in Fig. 10, we have two snake

structures with different area sizes. We expect the bigger snake structure

demonstrate a much higher leakage current and our leakage current measurements

at -2 V shows 285 A and 27.1 A for big and small diodes respectively. The big

snake diode turn-on voltage was found to be around 0.7 V but on the other hand

the small snake diode showed a 0.5 V turn-on voltage. Then we attempted to

measure I-V curves of snake-shaped diodes for different spots on the wafer but in

all other spots the amount of current measured for the diodes were on the order of

1 -10 nA (Fig. 20).

18 2


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19


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We then tried to measure C-V characteristics of MOS capacitors but were not

successful in obtaining a legitimate C-V curve for all our measurement devices.

B.Transistor Measurement DataFor all transistor-related measurements we used fabricated devices from

previous semester, in which they had not used SALICIDE for their contacts.

Instead, they had used Al contacts through opened holes in oxide layer which

results in a higher contact resistance which on the other hand degrades

performance of the devices for specially smaller-scale devices. Schematic diagram

of their fabricated MOSFET can be found in Fig. 21 below.

21

20


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For Threshold voltage extraction, VT, I sketched the vs. VG which wasmeasured at a very high VDS= 4 V. We know that in saturation region,

12 12

So where

0we can say that VGS= VT.

For gm,max calculations I have calculated and then sketched this versus VGS.The peak of the graph gives us gm,max. I have also sketched ID- VDS for all of the

five transistors that we characterized. All calculated data corresponding to each

different transistor are tabulated in Table. 5. All these calculated data are based on

the graphical data which could be found in Appendix C.

Width (W)m

Length (L)m

VT(V) gm,max (S)ID,Sat(VDS= 3.2V, VGS= 2V)

(A)

10 5 0.54 24.31 376.7

20 5 0.55 53.62 815.8

80 5 0.55 217.4 3280

80 10 0.52 111.2 1745

80 3 0.54 220.3 3395

As obviously shown in Table. 5, if we keep the L constant and increase W, gmwill

increase, because gm is proportional to W/L. By the same reasoning, Saturation

current will also increase.

On the other hand, as we keep W constant and increase L, gm and ID,Sat will

decrease.

5 /


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Subthreshold IDvs. VGfor all of the five transistor devices is sketched in Fig. 22.

As you can see as L is decreasing, subthreshold voltage decreases which is not at

all desirable in switching devices which require a high OFF to ON transition.

22


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16.ConclusionAs we went through the process of MOSFET fabrication, differences of varioustechniques which lead to the same result became more and more obvious. For

example, we deposited the polysilicon layer with ebeam evaporator but the resulted

film of polysilicon did not at all provide the uniformity and quality of conventional

LPCVD polyilicon which is the common technique used in industry. Also the

differences between various metal deposition techniques such as ebeam

evaporation, resistive heated evaporation, and sputtering became more and more

obvious as went through down the fabrication road. Subthreshold slope which is an

important measure of ON-OFF characteristic of a device becomes more important

as we shrink the length of our devices. Resistivity measurement structures should

be designed for minimal effect of other parallel layer on the layer of interest.


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Appendix A

V-I curves for Structure 1.

Note: Negative slope corresponds to negative Voltage reading in the opposite

direction of current flow.


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Appendix B

V-I curves for Structure 3.

Note: Negative slope corresponds to negative Voltage reading in the opposite

direction of current flow.


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Appendix C

Graphs for transistor measurements.


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mosfet fabrication: process design, artwork, fabrication

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