mosfet notes

ECEN 325

Electronics

MOS Field-Effect Transistors

Dr. Aydın Ilker Karsılayan

Texas A&M University

Department of Electrical and Computer Engineering

NMOS Physical StructureNMOS Physical Structure

p−

��

��

Drain (D)

L

W

Body (B)

n+

n+Polysilicon

Metal

Metal��

��

Source (S)

Gate (G)

ECEN 325 Electronics - Aydın I. Karsılayan - MOS Field-Effect Transistors 1

CMOS Physical StructureCMOS Physical Structure Cross-section

PMOSNMOS

��

S G D D G S

p−

n−well

��

��

��

��

��

��

��

n+ 2 p+ p+2 n+ 2SiO SiOSiO


Physical OperationPhysical Operation NMOS

VGS

��

p−

GS D

n+ n+

VGS > Vtn

VDS = 0

VGS VDS

��

p−

GS D

n+ n+

VGS > Vtn

VDS : very small


Physical OperationPhysical Operation NMOS

VGS VDS

��

p−

GS D

n+ n+

VGS > Vtn

VDS < Vov

Vov = VGS − Vtn

VGS VDS

��

p−

GS D

n+ n+

VGS > Vtn

VDS > Vov

Vov = VGS − Vtn


ID-VDS CharacteristicsID-VDS Characteristics NMOS

ActiveGS4

VGS3

VGS2

VGS1

VDS

ID

VGS

VDS

ID

VDS <Vov VDS >VovTriode

V


ID-VSD CharacteristicsID-VSD Characteristics PMOS

Active

ID

VSG

VSD

VSG4

VSG3

VSG2

VSG1

VSD

ID

VSD <Vov VSD >VovTriode


NMOS DC OperationNMOS DC Operation

G

GS

ID

D

S

V

IG=0

Vov = VGS − Vtn

• Cutoff: VGS < Vtn , ID = 0

• Triode (linear) region: VDS < Vov

ID = k′n

W

L

VovVDS −V2

DS

2

• Active (saturation) region: VDS > Vov

ID =k′n

2

W

LV2

ov


PMOS DC OperationPMOS DC Operation

G D

S

D

I

VSG

IG=0

Vov = VSG − |Vtp|

• Cutoff: VSG < |Vtp| , ID = 0

• Triode (linear) region: VSD < Vov

ID = k′p

W

L

VovVSD −V2

SD

2

• Active (saturation) region: VSD > Vov

ID =k′p

2

W

LV2

ov


MOSFET DC BiasingMOSFET DC Biasing Resistive

RG2

−VSS

RD

−VSS

RG2 RS

RG1

VDD

RSRDRG1

VDD

V2

V1

V2 =RG2(VDD + VSS)

RG1 + RG2

V2 = VGSn + RSIDn

IDn =k′n

2

W

L(VGSn − Vtn)

2

V1 =RG1(VDD + VSS)

RG1 + RG2

V1 = VSGp + RSIDp

IDp =k′p

2

W

L(VSGp − Vtp)

2


MOSFET DC BiasingMOSFET DC Biasing NMOS Current Mirror

ID1 ID2

M2M1

Assuming VGS1 > Vtn

VGS1 = VDS1 ⇒ VDS1 > VGS1 − Vtn

⇒ M1 is ACTIVE

⇒ ID1 =k′n

2

WL

1(VGS1 − Vtn)

2

Assuming M2 is ACTIVE

ID2 =k′n

2

WL

2(VGS2 − Vtn)

2

Since VGS1 = VGS2

ID1

ID2=

WL

1W

L

2


NMOS Current MirrorNMOS Current Mirror Example

R

ID1

M1 M2 M3 M4 M5 M6

ID2 ID3 ID4 ID5 ID6

VDD

−VSS

10/0.5 2/0.5 20/0.5 5/0.5 15/0.530/0.5


NMOS Current MirrorNMOS Current Mirror Example

VDD + VSS = R1ID1 + VGS1

ID1 =k′n

2

10

0.5(VGS1 − Vtn)

2

⇒ Find ID1

Assuming that all transistors are ACTIVE:

ID2 =ID1

5ID3 = 2ID1 ID4 =

ID1

2

ID5 = 3ID1 ID6 =3

2ID1


MOSFET DC BiasingMOSFET DC Biasing PMOS Current Mirror

ID1 ID2

M1 M2

Assuming VSG1 > |Vtp|VSG1 = VSD1 ⇒ VSD1 > VSG1 − |Vtp|

⇒ M1 is ACTIVE

⇒ ID1 =k′p

2

WL

1(VSG1 − |Vtp|)2

Assuming M2 is ACTIVE

ID2 =k′p

2

WL

2(VSG2 − |Vtp|)2

Since VSG1 = VSG2

ID1

ID2=

WL

1W

L

2


PMOS Current MirrorPMOS Current Mirror Example

40/1

SS

ID1 ID2 ID3 ID4 ID5 ID6

M2 M3 M4 M5 M6M1

VDD

R

10/1 20/1 2/1 5/1 30/1

−V


PMOS Current MirrorPMOS Current Mirror Example

VDD + VSS = R1ID1 + VSG1

ID1 =k′p

2

10

1(VSG1 − |Vtp|)2

⇒ Find ID1

Assuming that all transistors are ACTIVE:

ID2 = 2ID1 ID3 =ID1

5ID4 =

ID1

2

ID5 = 4ID1 ID6 = 3ID1


Current Mirror BiasingCurrent Mirror Biasing Example 1

5/0.5

M2

10/0.5

VI

−VSS

VDD

M11

VB

M1

M3

M4

M5

M8

M7

M6

M10

M9

M12

10/1 20/1

R

30/1

15/1 5/0.5

15/1

20/0.5

5/1

30/2

20/0.5


Current Mirror BiasingCurrent Mirror Biasing Example 2

5/0.5

VDD

M8

M7

M6

M5

M4

M3

M2

M1

M10

M9VI

25/1

15/0.5

20/0.5

10/1

40/1

10/0.5

5/0.5

25/0.5

10/0.5


MOSFET Small-Signal OperationMOSFET Small-Signal Operation

iD =k′n

2

W

L(VGS + vgs − Vt)

2 =k′n

2

W

L(Vov + vgs)

2

=k′n

2

W

LV2

ov + k′n

W

LVovvgs +

k′n

2

W

Lv2gs

D

VDSVGS

vgs

i

Assume vgs � 2Vov, then

iD ≈ ID + k′n

W

LVovvgs

= ID + gmvgs

= ID + id

gm = k′n

W

LVov


Small-Signal ModelSmall-Signal Model NMOS

gm = k′n

W

LVov =

√√√√√√2k′n

W

LID

ro =VA

ID=

1

λnID

ro

T model

D

S

modelπ

gm vgsvgs

G D

S

ro

gm

1 is

is

G


Small-Signal ModelSmall-Signal Model PMOS

gm = k′p

W

LVov =

√√√√√√2k′p

W

LID

ro =|VA|ID

=1

|λp|ID

T model

S

G D

modelπ

gm

1

ro

is

is

S

D

G

vsg rogm vsg


MOS Node ResistancesMOS Node Resistances AC, ro = ∞

RD

RS

RgateRgate = ∞

RS

RG

Rdrain

Rdrain = ∞

RG

RD

Rsource

Rsource =1

gm


Common-Source AmplifierCommon-Source Amplifier Discrete

RL

vo

RG2

RG1 RD

vi

Rx

VDD

Ri

−VSS

RS

Ro

VG

In

ID = In , VG = −VSS +RG2

RG1 + RG2(VDD + VSS)


Common-Source AmplifierCommon-Source Amplifier AC equivalent, ro = ∞

RGRovi

Ri

RL

vo

RS

RD

vgRx

Ri = RG ‖ Rgate = RG1 ‖ RG2 ‖ Rgate

Ro = RD ‖ Rdrain

vg

vi=

Ri

Rx + Ri,

vo

vg= −

RD ‖ RL1

gm+ RS


Common-Drain AmplifierCommon-Drain Amplifier Discrete

RL

vovi

Rx

−VSS

VDD

RG2

RG1

Ri

Ro

VG

In




Common-Drain AmplifierCommon-Drain Amplifier AC equivalent, ro = ∞

RG

Rovo

RL

vi

Rx

Ri

vg

Ri = RG ‖ Rgate = RG1 ‖ RG2 ‖ Rgate

Ro = Rsource

vg

vi=

Ri

Rx + Ri,

vo

vg=

RL1

gm+ RL


Common-Gate AmplifierCommon-Gate Amplifier Discrete

RD

−VSSRi

Ro

vo

RL

RG1

RG2

VDD

In Rx vi

VG




Common-Gate AmplifierCommon-Gate Amplifier AC equivalent, ro = ∞

RD RL

vo

Ro

RG

Rx

Ri

vi

vs

Ri = Rsource

Ro = RD ‖ Rdrain

vs

vi=

Ri

Rx + Ri,

vo

vs=

RD ‖ RL

Rsource


MOSFET Amplifiers - SummaryMOSFET Amplifiers - Summary AC, ro = ∞

vo

RD

RS

vi

vo

RD

RG

vi

vo

RS

vi

vo

vi= −

RD

1

gm+ RS

vo

vi=

RD

Rsource

vo

vi=

RS

1

gm+ RS


MOS Node ResistancesMOS Node Resistances AC, ro finite

RD

RS

Rgate Rgate = ∞

RS

RG

Rdrain

Rdrain = gmroRS + ro + RS

RG

RD

RsourceRsource =

1

gm‖ ro

1 +

RD

ro


Common-Source AmplifierCommon-Source Amplifier Integrated

R

vO

vI

VDD

M1

M2M3

VD3

ID3 =k′p

2

WL

3(VDD − VD3 − |Vtp|)2 =

VD3

R

ID2

ID3=

WL

2W

L

3

, ID1 = ID2


Common-Source AmplifierCommon-Source Amplifier AC equivalent

M1

ro2

Ri

viRo

vo

vo

vi= −

ro1 ‖ ro21

gm1

Ri = ∞

Ro = ro1 ‖ ro2


Common-Drain AmplifierCommon-Drain Amplifier Integrated

RvI M1

M2M3

vO

VDD

VD3

ID3 =k′n

2

WL

3(VD3 − Vtn)

2 =VDD − VD3

R

ID2

ID3=

WL

2W

L

3

, ID1 = ID2


Common-Drain AmplifierCommon-Drain Amplifier AC Equivalent

M1

Ri

vi

vo

ro2

Ro

vo

vi=

ro1 ‖ ro21

gm1+ (ro1 ‖ ro2)

Ri = ∞

Ro =1

gm1‖ ro1 ‖ ro2


Two-Port Modeling of AmplifiersTwo-Port Modeling of Amplifiers

Network

Two−portVi Vo

⇓

RnviRivi voviGm

vo

vi= GmRn


Two-Port Modeling of AmplifiersTwo-Port Modeling of Amplifiers Gm & Rn

RnviRi voviGm iscvi

Gm =isc

vi

∣∣∣∣∣∣∣∣vo=0

RnviRi viGm vo

io

Rn =vo

io

∣∣∣∣∣∣∣∣vi=0


Two-Port Modeling of AmplifiersTwo-Port Modeling of Amplifiers Multistage

vi

vov3v2v1 vN−1

#1 #2 #3 #N

viii

Ri

#1 #3 #N#2

io vo

Ro

#1 #2 #3 #N

vo

vi=

v1

vi

v2

v1· · ·

vo

vN−1Ri =

vi

iiRo =

vo

io



vi

vov3v2v1 vN−1

#1 #2 #3 #N

Rn1

vi isc1

#1 #2 #3 #N

#1 #2 #3 #N

Gm1 =isc1

vi

v1

vi= Gm1Rn1



vi

vov3v2v1 vN−1

#1 #2 #3 #N

isc2v1

Rn2

#N

#N

#2 #3

#2 #3

Gm2 =isc2

v1

v2

v1= Gm2Rn2



vi

vov3v2v1 vN−1

#1 #2 #3 #N

RnN

iscNvN−1

#N

#N

GmN =iscN

vN−1

vo

vN−1= GmNRnN


Common-Gate AmplifierCommon-Gate Amplifier Integrated

R

vO

VDD

M1

M2

VB

vI

M3

VD3

ID3 =k′p

2

WL

3(VDD − VD3 − |Vtp|)2 =

VD3

R

ID2

ID3=

WL

2W

L

3

, ID1 = ID2


Common-Gate AmplifierCommon-Gate Amplifier AC Equivalent

M1

ro2

vo

viRi

Ri =

1

gm1‖ ro1

1 +

ro2

ro1

Gm = gm1 +1

ro1

Rn = ro1 ‖ ro2

vo

vi= GmRn


Common-Source Amplifier - SDCommon-Source Amplifier - SD Integrated

VDD

M3

VD3 vO

Rx

Rs

vI M1

M2

ID3 =k′p

2

WL

3(VDD − VD3 − |Vtp|)2 =

VD3

Rx

ID2

ID3=

WL

2W

L

3

, ID1 = ID2


Common-Source Amplifier - SDCommon-Source Amplifier - SD AC equivalent

ro2

Ri

vi

vo

Rs

M1

Ri = ∞

Gm =−gm1

1 + gm1Rs + (Rs/ro1)

Rn = ro2 ‖ (Rs + ro1 + gm1Rsro1)

vo

vi= GmRn


MOSFET Amplifiers- SummaryMOSFET Amplifiers- Summary AC, ro finite

vo

RD

vi

vo

vi= −

RD ‖ ro1

gm

vo

RS

vi

vo

vi=

RS ‖ ro1

gm+ (RS ‖ ro)


MOSFET Amplifiers - SummaryMOSFET Amplifiers - Summary AC, ro finite

vo

RD

RS

vi

Gm =−gm

1 + gmRS +RS

ro

Rn = RD ‖ (gmroRS + ro + RS)

vo

vi= GmRn

vo

RD

RG

vi

Gm = gm +1

ro

Rn = RD ‖ ro

vo

vi= GmRn


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