mpc8349ea powerquicc ii pro integrated host processor...

MPC8349EAPowerQUICC II Pro

Integrated Host ProcessorFamily Reference Manual

SupportsMPC8349EAMPC8347EAMPC8343EA

MPC8349EARMRev. 1

08/2006

Document Number: MPC8349EARMRev. 1, 08/2006

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Preface PRE

Overview 1

Memory Map 2

Signal Descriptions 3

Reset, Clocking, and Initialization 4

System Configuration 5

Arbiter and Bus Monitor 6

e300 Processor Core 7

Integrated Programmable Interrupt Controller (IPIC) 8

DDR Memory Controller 9

Local Bus Controller 10

Sequencer 11

DMA 12

PCI Bus Interface 13

Security Engine (SEC) 2.0 14

Three-Speed Ethernet Controllers 15

Universal Serial Bus Interface 16

I2C Interfaces 17

DUART 18

Serial Peripheral Interface 19

JTAG/Testing Support 20

General Purpose I/O (GPIO) 21

Delay Lock Loop (DLL) 22

Revision History APP

Glossary GLO

Register Index REG

General Index IND

PRE Preface

1 Overview

2 Memory Map

3 Signal Descriptions

4 Reset, Clocking, and Initialization

5 System Configuration

6 Arbiter and Bus Monitor

7 e300 Processor Core

8 Integrated Programmable Interrupt Controller (IPIC)

9 DDR Memory Controller

10 Local Bus Controller

11 Sequencer

12 DMA

13 PCI Bus Interface

14 Security Engine (SEC) 2.0

15 Three-Speed Ethernet Controller

16 Universal Serial Bus Interface

17 I2C Interface

18 DUART

19 Serial Peripheral Interface

20 JTAG/Testing Support

21 General Purpose I/O (GPIO)

22 Delay Lock Loop (DLL)

23

APP Revision History

GLO Glossary

REG Register Index

IND General Index

MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual, Rev. 1

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ContentsParagraphNumber Title

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Contents

About This Book

Audience ........................................................................................................................ lxxvOrganization................................................................................................................... lxxvSuggested Reading....................................................................................................... lxxviiConventions ................................................................................................................ lxxviiiSignal Conventions ....................................................................................................... lxxixAcronyms and Abbreviations ....................................................................................... lxxix

Chapter 1 Overview

1.1 MPC834x-Family Product Distinctions........................................................................... 1-11.2 MPC8349EA PowerQUICC II Pro Processor Overview ................................................ 1-21.3 MPC8349EA Architecture Overview.............................................................................. 1-71.3.1 PowerPC Core.............................................................................................................. 1-71.3.2 Security Engine......................................................................................................... 1-101.3.3 DDR Memory Controller........................................................................................... 1-101.3.4 Dual Three-Speed Ethernet Controllers..................................................................... 1-111.3.5 PCI Controllers .......................................................................................................... 1-121.3.5.1 PCI Bus Arbitration Unit ....................................................................................... 1-121.3.6 Universal Serial Bus (USB) 2.0................................................................................. 1-121.3.6.1 USB Dual-Role Controller .................................................................................... 1-131.3.6.2 USB Multi-Port Host Controller............................................................................ 1-141.3.7 Local Bus Controller (LBC) ...................................................................................... 1-141.3.8 Integrated Programmable Interrupt Controller (IPIC) ............................................... 1-151.3.9 Dual I2C Interfaces .................................................................................................... 1-151.3.10 DMA Controller......................................................................................................... 1-161.3.11 Dual Universal Asynchronous Receiver/Transmitter (DUART)............................... 1-161.3.12 Serial Peripheral Interface (SPI) ................................................................................ 1-171.3.13 System Timers ........................................................................................................... 1-171.4 Applications ................................................................................................................... 1-181.5 Differences Between MPC8349E and MPC8349EA .................................................... 1-18


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Chapter 2 Memory Map

2.1 Internal Memory Mapped Registers ................................................................................ 2-12.2 Accessing IMMR Memory From the Local Processor .................................................... 2-12.3 Complete IMMR Map ..................................................................................................... 2-1

Chapter 3 Signal Descriptions

3.1 Signals Overview............................................................................................................. 3-13.2 Configuration Signals Sampled at Reset ....................................................................... 3-193.3 Output Signal States During Reset ................................................................................ 3-19

Chapter 4 Reset, Clocking, and Initialization

4.1 External Signals ............................................................................................................... 4-14.1.1 Reset Signals................................................................................................................ 4-14.1.2 Clock Signals ............................................................................................................... 4-34.2 Functional Description..................................................................................................... 4-34.2.1 Reset Operations .......................................................................................................... 4-34.2.1.1 Reset Causes ............................................................................................................ 4-44.2.1.2 Reset Actions ........................................................................................................... 4-44.2.2 Power-On Reset Flow.................................................................................................. 4-54.2.3 Hard Reset Flow .......................................................................................................... 4-74.2.4 Soft Reset Flow............................................................................................................ 4-84.3 Reset Configuration ......................................................................................................... 4-84.3.1 Reset Configuration Signals ........................................................................................ 4-94.3.1.1 Reset Configuration Word Source ........................................................................... 4-94.3.1.2 CLKIN Division .................................................................................................... 4-104.3.1.3 Selecting Reset Configuration Input Signals ......................................................... 4-104.3.2 Reset Configuration Words........................................................................................ 4-114.3.2.1 Reset Configuration Word Low Register (RCWLR)............................................. 4-114.3.2.1.1 System PLL Configuration................................................................................ 4-124.3.2.2 Reset Configuration Word High Register (RCWHR)............................................ 4-144.3.2.2.1 PCI Host/Agent Configuration .......................................................................... 4-164.3.2.2.2 Boot Memory Space (BMS) .............................................................................. 4-164.3.2.2.3 Boot Sequencer Configuration .......................................................................... 4-174.3.2.2.4 Boot ROM Location .......................................................................................... 4-174.3.2.2.5 TSEC1 Mode ..................................................................................................... 4-19


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4.3.2.2.6 TSEC2 Mode ..................................................................................................... 4-204.3.2.2.7 e300 Core True Little-Endian............................................................................ 4-204.3.2.2.8 LALE Configuration.......................................................................................... 4-214.3.2.2.9 LDP Configuration ............................................................................................ 4-214.3.3 Loading the Reset Configuration Words ................................................................... 4-214.3.3.1 Loading from Local Bus EEPROM....................................................................... 4-214.3.3.1.1 Local Bus EEPROM Timing ............................................................................. 4-234.3.3.2 Loading from I2C EEPROM ................................................................................. 4-244.3.3.2.1 Using the Boot Sequencer Reset Configuration ................................................ 4-244.3.3.2.2 EEPROM Calling Address ................................................................................ 4-244.3.3.2.3 EEPROM Data Format in Reset Configuration Mode ...................................... 4-244.3.3.2.4 Reset Configuration Load Fail .......................................................................... 4-274.3.3.3 Default Reset Configuration Words....................................................................... 4-274.3.3.3.1 Hard-Coded Reset Configuration Word Low.................................................... 4-274.3.3.3.2 Hard-Coded Reset Configuration Word High Fields Values............................. 4-284.3.3.3.3 Examples for Hard-Coded Reset Configuration Words Usage ......................... 4-294.4 Clocking ........................................................................................................................ 4-294.4.1 Clocking in PCI Host Mode....................................................................................... 4-304.4.1.1 PCI Clock Outputs (PCI_CLK_OUT[0:7]) ........................................................... 4-304.4.2 Clocking In PCI Agent Mode .................................................................................... 4-304.4.3 System Clock Domains.............................................................................................. 4-304.5 Memory Map/Register Definition ................................................................................. 4-324.5.1 Reset Configuration Registers Descriptions .............................................................. 4-324.5.1.1 Reset Configuration Word Low Register (RCWLR)............................................. 4-324.5.1.2 Reset Configuration Word High Register (RCWHR)............................................ 4-324.5.1.3 Reset Status Register (RSR) .................................................................................. 4-334.5.1.4 Reset Mode Register (RMR) ................................................................................. 4-344.5.1.5 Reset Protection Register (RPR) ........................................................................... 4-354.5.1.6 Reset Control Register (RCR) ............................................................................... 4-364.5.1.7 Reset Control Enable Register (RCER)................................................................. 4-364.5.2 Clock Configuration Registers................................................................................... 4-374.5.2.1 System PLL Mode Register (SPMR) .................................................................... 4-374.5.2.2 Output Clock Control Register (OCCR)................................................................ 4-384.5.2.3 System Clock Control Register (SCCR)................................................................ 4-404.5.3 Clock Control DDR Registers ................................................................................... 4-414.5.3.1 MCK Enable Register (MCKENR) ....................................................................... 4-41


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Chapter 5 System Configuration

5.1 Introduction...................................................................................................................... 5-15.2 Local Memory Map Overview and Example .................................................................. 5-15.2.1 Address Translation and Mapping ............................................................................... 5-35.2.2 Window into Configuration Space............................................................................... 5-35.2.3 Local Access Windows................................................................................................ 5-45.2.3.1 Local Access Register Memory Map ...................................................................... 5-45.2.4 Local Access Register Descriptions ............................................................................ 5-55.2.4.1 Internal Memory Map Registers Base Address Register (IMMRBAR).................. 5-55.2.4.1.1 Updating IMMRBAR.......................................................................................... 5-65.2.4.2 Alternate Configuration Base Address Register (ALTCBAR)................................ 5-75.2.4.3 LBC Local Access Window n Base Address Registers

(LBLAWBAR0LBLAWBAR3) ........................................................................ 5-75.2.4.3.1 LBLAWBAR0[BASE_ADDR] Reset Value ....................................................... 5-85.2.4.4 LBC Local Access Window n Attributes Registers

(LBLAWAR0LBLAWAR3)............................................................................... 5-85.2.4.4.1 LBLAWAR0[EN] and LBLAWAR0[SIZE] Reset Value .................................... 5-95.2.4.5 PCI Local Access Window n Base Address Register

(PCILAWBAR0PCILAWBAR1) ...................................................................... 5-95.2.4.5.1 PCILAWBAR0[BASE_ADDR] Reset Value.................................................... 5-105.2.4.6 PCI Local Access Window n Attributes Registers

(PCILAWAR0PCILAWAR1) .......................................................................... 5-105.2.4.6.1 PCILAWAR0[EN] and PCILAWAR0[SIZE] Reset Value ................................ 5-115.2.4.7 DDR Local Access Window n Base Address Registers

(DDRLAWBAR0DDRLAWBAR1)................................................................ 5-125.2.4.7.1 DDRLAWBAR0[BASE_ADDR] Reset Value.................................................. 5-125.2.4.8 DDR Local Access Window n Attributes Registers

(DDRLAWAR0DDRLAWAR1)...................................................................... 5-135.2.4.8.1 DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value............................ 5-135.2.5 Precedence of Local Access Windows ...................................................................... 5-145.2.6 Configuring Local Access Windows ......................................................................... 5-145.2.7 Distinguishing Local Access Windows from Other Mapping Functions .................. 5-145.2.8 Outbound Address Translation and Mapping Windows............................................ 5-155.2.9 Inbound Address Translation and Mapping Windows .............................................. 5-155.2.9.1 PCI1/PCI2 Inbound Windows ............................................................................... 5-155.2.10 Internal Memory Map................................................................................................ 5-155.2.11 Accessing Internal Memory from External Masters.................................................. 5-165.3 System Configuration .................................................................................................... 5-165.3.1 System Configuration Register Memory Map........................................................... 5-16


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5.3.2 System Configuration Registers ................................................................................ 5-175.3.2.1 System General Purpose Register Low (SGPRL) ................................................. 5-175.3.2.2 System General Purpose Register High (SGPRH) ................................................ 5-175.3.2.3 System Part and Revision ID Register (SPRIDR)................................................. 5-185.3.2.3.1 SPRIDR[PARTID] Coding................................................................................ 5-185.3.2.4 System Priority and Configuration Register (SPCR) ............................................ 5-195.3.2.5 System I/O Configuration Register Low (SICRL) ................................................ 5-215.3.2.6 System I/O Configuration Register High (SICRH) ............................................... 5-245.3.2.7 Debug Configuration ............................................................................................. 5-285.3.2.7.1 DDR Debug Configuration................................................................................ 5-285.3.2.7.2 Local Bus Debug Configuration........................................................................ 5-285.3.2.8 DDR Control Driver Register (DDRCDR)............................................................ 5-285.3.2.9 DDR Debug Status Register (DDRDSR) .............................................................. 5-305.4 Software Watchdog Timer (WDT)................................................................................. 5-315.4.1 Overview.................................................................................................................... 5-315.4.2 Features...................................................................................................................... 5-325.4.3 Modes of Operation ................................................................................................... 5-325.4.4 Memory Map/Register Definition ............................................................................. 5-335.4.4.1 System Watchdog Control Register (SWCRR) ..................................................... 5-335.4.4.2 System Watchdog Count Register (SWCNR) ....................................................... 5-345.4.4.3 System Watchdog Service Register (SWSRR)...................................................... 5-345.4.5 Functional Description............................................................................................... 5-355.4.5.1 Software Watchdog Timer Unit ............................................................................. 5-355.4.5.2 Modes of Operation ............................................................................................... 5-375.4.6 Initialization/Application Information....................................................................... 5-385.4.6.1 WDT Programming Guidelines............................................................................. 5-385.5 Real Time Clock Module (RTC).................................................................................... 5-385.5.1 Overview.................................................................................................................... 5-385.5.2 Features...................................................................................................................... 5-395.5.3 Modes of Operation ................................................................................................... 5-395.5.4 External Signal Description ....................................................................................... 5-395.5.4.1 Overview................................................................................................................ 5-395.5.4.2 Detailed Signal Descriptions ................................................................................. 5-395.5.5 Memory Map/Register Definition ............................................................................. 5-405.5.5.1 Real Time Counter Control Register (RTCNR) .................................................... 5-405.5.5.2 Real Time Counter Load Register (RTLDR)......................................................... 5-415.5.5.3 Real Time Counter Prescale Register (RTPSR) .................................................... 5-415.5.5.4 Real Time Counter Register (RTCTR) .................................................................. 5-425.5.5.5 Real Time Counter Event Register (RTEVR)........................................................ 5-425.5.5.6 Real Time Counter Alarm Register (RTALR) ....................................................... 5-435.5.6 Functional Description............................................................................................... 5-43


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5.5.6.1 Real Time Counter Unit......................................................................................... 5-435.5.6.2 RTC Operational Modes ........................................................................................ 5-445.5.7 RTC Programming Guidelines................................................................................... 5-455.6 Periodic Interval Timer (PIT) ........................................................................................ 5-455.6.1 Overview.................................................................................................................... 5-455.6.2 Features...................................................................................................................... 5-465.6.3 Modes of Operation ................................................................................................... 5-465.6.4 External Signal Description ....................................................................................... 5-465.6.4.1 Overview................................................................................................................ 5-465.6.4.2 Detailed Signal Description................................................................................... 5-475.6.5 Memory Map/Register Definition ............................................................................. 5-475.6.5.1 Periodic Interval Timer Control Register (PTCNR) .............................................. 5-475.6.5.2 Periodic Interval Timer Load Register (PTLDR) .................................................. 5-485.6.5.3 Periodic Interval Timer Prescale Register (PTPSR) .............................................. 5-495.6.5.4 Periodic Interval Timer Counter Register (PTCTR).............................................. 5-495.6.5.5 Periodic Interval Timer Event Register (PTEVR) ................................................. 5-505.6.6 Functional Description............................................................................................... 5-505.6.6.1 Periodic Interval Timer Unit.................................................................................. 5-505.6.6.2 PIT Operational Modes.......................................................................................... 5-515.6.7 PIT Programming Guidelines .................................................................................... 5-515.7 General-Purpose Timers (GTMs)................................................................................... 5-525.7.1 Overview.................................................................................................................... 5-525.7.2 Features...................................................................................................................... 5-535.7.3 Modes of Operation ................................................................................................... 5-535.7.3.1 Cascaded Modes .................................................................................................... 5-535.7.3.2 Clock Source Modes.............................................................................................. 5-545.7.3.3 Reference Modes ................................................................................................... 5-545.7.3.4 Capture Modes....................................................................................................... 5-545.7.4 External Signal Description ....................................................................................... 5-545.7.4.1 Overview................................................................................................................ 5-545.7.4.2 Detailed Signal Descriptions ................................................................................. 5-555.7.5 Memory Map/Register Definition ............................................................................. 5-565.7.5.1 Global Timers Configuration Registers (GTCFRn)............................................... 5-575.7.5.2 Global Timers Mode Registers (GTMDR1GTMDR4) ........................................ 5-605.7.5.3 Global Timers Reference Registers (GTRFR1GTRFR4) .................................... 5-625.7.5.4 Global Timers Capture Registers (GTCPR1GTCPR4) ........................................ 5-625.7.5.5 Global Timers Counter Registers (GTCNR1GTCNR4) ...................................... 5-635.7.5.6 Global Timers Event Registers (GTEVR1GTEVR4) .......................................... 5-635.7.5.7 Global Timers Prescale Registers (GTPSR1GTPSR4) ........................................ 5-645.7.6 Functional Description............................................................................................... 5-655.7.6.1 General-Purpose Timer Units ................................................................................ 5-65


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5.7.6.2 Reference Modes ................................................................................................... 5-655.7.6.3 Capture Modes....................................................................................................... 5-655.7.6.4 Cascaded Modes .................................................................................................... 5-665.7.7 Initialization/Application Information....................................................................... 5-685.7.7.1 Programming Guidelines ....................................................................................... 5-685.7.7.1.1 GTM Registers................................................................................................... 5-685.8 Power Management Control .......................................................................................... 5-685.8.1 Modes of Operation ................................................................................................... 5-685.8.2 External Signal Description ....................................................................................... 5-695.8.3 Memory Map/Register Definition ............................................................................. 5-695.8.3.1 Power Management Controller Configuration Register (PMCCR)....................... 5-695.8.3.2 Power Management Controller Event Register (PMCER).................................... 5-705.8.3.3 Power Management Controller Mask Register (PMCMR) ................................... 5-715.8.4 Functional Description............................................................................................... 5-715.8.4.1 Dynamic Power Management................................................................................ 5-715.8.4.2 Shutting Down Unused Blocks.............................................................................. 5-725.8.4.3 Software-Controlled Power-Down States.............................................................. 5-725.8.4.3.1 Entering Low Power StatesCore-Only Mode ................................................ 5-725.8.4.3.2 Entering Low Power StatesCore and System Mode...................................... 5-725.8.4.4 Exiting Core and System Low Power States ......................................................... 5-735.8.4.4.1 Exiting Low Power StatesCore-Only Mode .................................................. 5-735.8.4.4.2 Exiting Low Power StatesCore and System Mode........................................ 5-735.8.5 Initialization/Application Information....................................................................... 5-745.8.5.1 Core Disable in Low Power Mode ........................................................................ 5-74

Chapter 6 Arbiter and Bus Monitor

6.1 Overview.......................................................................................................................... 6-16.1.1 Coherent System Bus Overview.................................................................................. 6-16.2 Arbiter Memory Map/Register Definition ....................................................................... 6-26.2.1 Arbiter Configuration Register (ACR) ........................................................................ 6-26.2.2 Arbiter Timers Register (ATR) .................................................................................... 6-46.2.3 Arbiter Event Register (AER)...................................................................................... 6-56.2.4 Arbiter Interrupt Definition Register (AIDR).............................................................. 6-66.2.5 Arbiter Mask Register (AMR)..................................................................................... 6-76.2.6 Arbiter Event Attributes Register (AEATR)................................................................ 6-76.2.7 Arbiter Event Address Register (AEADR).................................................................. 6-96.2.8 Arbiter Event Response Register (AERR)................................................................. 6-106.3 Functional Description................................................................................................... 6-116.3.1 Arbitration Policy ...................................................................................................... 6-11


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6.3.1.1 Address Bus Arbitration with PRIORITY[0:1] ..................................................... 6-126.3.1.2 Address Bus Arbitration with REPEAT ................................................................ 6-136.3.1.3 Address Bus Arbitration after ARTRY.................................................................. 6-136.3.1.4 Address Bus Parking.............................................................................................. 6-136.3.1.5 Data Bus Arbitration.............................................................................................. 6-136.3.2 Bus Error Detection ................................................................................................... 6-146.3.2.1 Address Time Out .................................................................................................. 6-146.3.2.2 Data Time Out ....................................................................................................... 6-146.3.2.3 Transfer Error ........................................................................................................ 6-146.3.2.4 Address Only Transaction Type............................................................................. 6-156.3.2.5 Reserved Transaction Type.................................................................................... 6-156.3.2.6 Illegal (eciwx/ecowx) Transaction Type................................................................ 6-166.4 Initialization/Applications Information ......................................................................... 6-166.4.1 Initialization Sequence............................................................................................... 6-166.4.2 Error Handling Sequence........................................................................................... 6-17

Chapter 7 e300 Processor Core Overview

7.1 Overview.......................................................................................................................... 7-17.1.1 Features........................................................................................................................ 7-37.1.2 Instruction Unit ............................................................................................................ 7-67.1.2.1 Instruction Queue and Dispatch Unit ...................................................................... 7-67.1.2.2 Branch Processing Unit (BPU)................................................................................ 7-77.1.3 Independent Execution Units....................................................................................... 7-77.1.3.1 Integer Unit (IU) ...................................................................................................... 7-77.1.3.2 Floating-Point Unit (FPU) ....................................................................................... 7-77.1.3.3 Load/Store Unit (LSU) ............................................................................................ 7-87.1.3.4 System Register Unit (SRU).................................................................................... 7-87.1.4 Completion Unit .......................................................................................................... 7-87.1.5 Memory Subsystem Support........................................................................................ 7-87.1.5.1 Memory Management Units (MMUs)..................................................................... 7-97.1.5.2 Cache Units............................................................................................................ 7-107.1.6 Bus Interface Unit (BIU) ........................................................................................... 7-107.1.7 System Support Functions ......................................................................................... 7-117.1.7.1 Power Management ............................................................................................... 7-117.1.7.2 Time Base/Decrementer ........................................................................................ 7-117.1.7.3 JTAG Test and Debug Interface............................................................................. 7-127.1.7.4 Clock Multiplier..................................................................................................... 7-127.2 PowerPC Architecture Implementation ........................................................................ 7-127.3 Implementation-Specific Information............................................................................ 7-12


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7.3.1 Register Model........................................................................................................... 7-137.3.1.1 UISA Registers ...................................................................................................... 7-157.3.1.1.1 General-Purpose Registers (GPRs) ................................................................... 7-157.3.1.1.2 Floating-Point Registers (FPRs)........................................................................ 7-157.3.1.1.3 Condition Register (CR).................................................................................... 7-157.3.1.1.4 Floating-Point Status and Control Register (FPSCR) ....................................... 7-157.3.1.1.5 User-Level SPRs................................................................................................ 7-157.3.1.2 VEA Registers ....................................................................................................... 7-167.3.1.3 OEA Registers ....................................................................................................... 7-167.3.1.3.1 Machine State Register (MSR).......................................................................... 7-167.3.1.3.2 Segment Registers (SRs) ................................................................................... 7-187.3.1.3.3 Supervisor-Level SPRs...................................................................................... 7-187.3.2 Instruction Set and Addressing Modes ...................................................................... 7-257.3.2.1 PowerPC Instruction Set and Addressing Modes.................................................. 7-257.3.2.2 Implementation-Specific Instruction Set ............................................................... 7-267.3.3 Cache Implementation ............................................................................................... 7-277.3.3.1 PowerPC Cache Characteristics ............................................................................ 7-277.3.3.2 Implementation-Specific Cache Implementation .................................................. 7-277.3.3.3 Instruction and Data Cache Way-Locking............................................................. 7-297.3.4 Interrupt Model .......................................................................................................... 7-297.3.4.1 PowerPC Interrupt Model...................................................................................... 7-297.3.4.2 Implementation-Specific Interrupt Model ............................................................. 7-307.3.5 Memory Management................................................................................................ 7-337.3.5.1 PowerPC Memory Management............................................................................ 7-337.3.5.2 Implementation-Specific Memory Management ................................................... 7-337.3.6 Instruction Timing ..................................................................................................... 7-347.3.7 Core Interface ............................................................................................................ 7-357.3.7.1 Memory Accesses.................................................................................................. 7-367.3.7.2 Signals.................................................................................................................... 7-367.3.8 Debug Features ......................................................................................................... 7-377.3.8.1 Breakpoint Signaling ............................................................................................. 7-377.4 Differences Between Cores............................................................................................ 7-38

Chapter 8 Integrated Programmable Interrupt Controller (IPIC)

8.1 Introduction...................................................................................................................... 8-18.2 Features ............................................................................................................................ 8-48.3 Modes of Operation ......................................................................................................... 8-48.3.1 Core Enable Mode ....................................................................................................... 8-48.3.2 Core Disable Mode ...................................................................................................... 8-5


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8.4 External Signal Description ............................................................................................. 8-58.4.1 Overview...................................................................................................................... 8-58.4.2 Detailed Signal Descriptions ....................................................................................... 8-68.5 Memory Map/Register Definition ................................................................................... 8-68.5.1 System Global Interrupt Configuration Register (SICFR) .......................................... 8-88.5.2 System Global Interrupt Vector Register (SIVCR)...................................................... 8-98.5.3 System Internal Interrupt Pending Registers (SIPNR_H and SIPNR_L).................. 8-118.5.4 System Internal Interrupt Group A Priority Register (SIPRR_A)............................. 8-148.5.5 System Internal Interrupt Group D Priority Register (SIPRR_D)............................. 8-148.5.6 System Internal Interrupt Mask Register (SIMSR_H and SIMSR_L) ...................... 8-158.5.7 System Internal Interrupt Control Register (SICNR) ................................................ 8-168.5.8 System External Interrupt Pending Register (SEPNR).............................................. 8-188.5.9 System Mixed Interrupt Group A Priority Register (SMPRR_A)............................. 8-188.5.10 System Mixed Interrupt Group B Priority Register (SMPRR_B) ............................. 8-198.5.11 System External Interrupt Mask Register (SEMSR) ................................................. 8-208.5.12 System External Interrupt Control Register (SECNR).............................................. 8-218.5.13 System Error Status Register (SERSR) ..................................................................... 8-228.5.14 System Error Mask Register (SERMR)..................................................................... 8-238.5.15 System Error Control Register (SERCR) .................................................................. 8-248.5.16 System Internal Interrupt Force Registers (SIFCR_H and SIFCR_L) ...................... 8-258.5.17 System External Interrupt Force Register (SEFCR).................................................. 8-268.5.18 System Error Force Register (SERFR)...................................................................... 8-268.5.19 System Critical Interrupt Vector Register (SCVCR) ................................................. 8-278.5.20 System Management Interrupt Vector Register (SMVCR) ....................................... 8-278.6 Functional Description................................................................................................... 8-288.6.1 Interrupt Types ........................................................................................................... 8-288.6.2 Interrupt Configuration.............................................................................................. 8-298.6.3 Internal Interrupts Group Relative Priority................................................................ 8-308.6.4 Mixed Interrupts Group Relative Priority.................................................................. 8-308.6.5 Highest Priority Interrupt........................................................................................... 8-318.6.6 Interrupt Source Priorities.......................................................................................... 8-318.6.7 Masking Interrupt Sources......................................................................................... 8-348.6.8 Interrupt Vector Generation and Calculation ............................................................. 8-358.6.9 Machine Check Interrupts.......................................................................................... 8-35

Chapter 9 DDR Memory Controller

9.1 Introduction...................................................................................................................... 9-19.2 Features ............................................................................................................................ 9-29.2.1 Modes of Operation ..................................................................................................... 9-3


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9.3 External Signal Descriptions ........................................................................................... 9-39.3.1 Signals Overview......................................................................................................... 9-39.3.2 Detailed Signal Descriptions ....................................................................................... 9-59.3.2.1 Memory Interface Signals........................................................................................ 9-59.3.2.2 Clock Interface Signals............................................................................................ 9-89.3.2.3 Debug Signals.......................................................................................................... 9-99.4 Memory Map/Register Definition ................................................................................... 9-99.4.1 Register Descriptions................................................................................................. 9-109.4.1.1 Chip Select Memory Bounds (CSn_BNDS).......................................................... 9-109.4.1.2 Chip Select Configuration (CSn_CONFIG).......................................................... 9-119.4.1.3 DDR SDRAM Timing Configuration 3 (TIMING_CFG_3)................................. 9-139.4.1.4 DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)................................. 9-149.4.1.5 DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)................................. 9-169.4.1.6 DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)................................. 9-189.4.1.7 DDR SDRAM Control Configuration (DDR_SDRAM_CFG)............................. 9-209.4.1.8 DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)...................... 9-229.4.1.9 DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)............................ 9-249.4.1.10 DDR SDRAM Mode 2 Configuration (DDR_SDRAM_MODE_2)..................... 9-249.4.1.11 DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)................. 9-259.4.1.12 DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) ................. 9-279.4.1.13 DDR SDRAM Data Initialization (DDR_DATA_INIT) ....................................... 9-289.4.1.14 DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) ............................. 9-289.4.1.15 DDR Initialization Address (DDR_INIT_ADDR)................................................ 9-299.4.1.16 DDR IP Block Revision 1 (DDR_IP_REV1)........................................................ 9-309.4.1.17 DDR IP Block Revision 2 (DDR_IP_REV2)........................................................ 9-309.4.1.18 Memory Data Path Error Injection Mask High (DATA_ERR_INJECT_HI) ........ 9-319.4.1.19 Memory Data Path Error Injection Mask Low (DATA_ERR_INJECT_LO)........ 9-319.4.1.20 Memory Data Path Error Injection Mask ECC (ERR_INJECT)........................... 9-329.4.1.21 Memory Data Path Read Capture High (CAPTURE_DATA_HI)......................... 9-329.4.1.22 Memory Data Path Read Capture Low (CAPTURE_DATA_LO) ........................ 9-339.4.1.23 Memory Data Path Read Capture ECC (CAPTURE_ECC).................................. 9-339.4.1.24 Memory Error Detect (ERR_DETECT)................................................................ 9-339.4.1.25 Memory Error Disable (ERR_DISABLE)............................................................. 9-349.4.1.26 Memory Error Interrupt Enable (ERR_INT_EN).................................................. 9-359.4.1.27 Memory Error Attributes Capture (CAPTURE_ATTRIBUTES).......................... 9-369.4.1.28 Memory Error Address Capture (CAPTURE_ADDRESS) .................................. 9-379.4.1.29 Single-Bit ECC Memory Error Management (ERR_SBE) ................................... 9-379.5 Functional Description................................................................................................... 9-389.5.1 DDR SDRAM Interface Operation............................................................................ 9-439.5.1.1 Supported DDR SDRAM Organizations............................................................... 9-439.5.2 DDR SDRAM Address Multiplexing........................................................................ 9-45


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9.5.3 JEDEC Standard DDR SDRAM Interface Commands ............................................. 9-499.5.4 DDR SDRAM Interface Timing................................................................................ 9-519.5.4.1 Clock Distribution ................................................................................................. 9-549.5.5 DDR SDRAM Mode-Set Command Timing............................................................. 9-559.5.6 DDR SDRAM Registered DIMM Mode ................................................................... 9-569.5.7 DDR SDRAM Write Timing Adjustments ................................................................ 9-569.5.8 DDR SDRAM Refresh .............................................................................................. 9-579.5.8.1 DDR SDRAM Refresh Timing.............................................................................. 9-589.5.8.2 DDR SDRAM Refresh and Power-Saving Modes ................................................ 9-589.5.8.2.1 Self-Refresh in Sleep Mode............................................................................... 9-609.5.9 DDR Data Beat Ordering........................................................................................... 9-619.5.10 Page Mode and Logical Bank Retention ................................................................... 9-619.5.11 Error Checking and Correcting (ECC) ...................................................................... 9-629.5.12 Error Management ..................................................................................................... 9-649.6 Initialization/Application Information ........................................................................... 9-659.6.1 Programming Differences Between Memory Types.................................................. 9-669.6.2 DDR SDRAM Initialization Sequence ...................................................................... 9-699.6.3 Using Forced Self-Refresh Mode to Implement a Battery-Backed

RAM System ......................................................................................................... 9-699.6.3.1 Hardware Based Self-Refresh Scheme.................................................................. 9-699.6.3.2 Software Based Self-Refresh Scheme ................................................................... 9-709.6.3.3 Bypassing Re-initialization During Battery-Backed Operation ............................ 9-70

Chapter 10 Local Bus Controller

10.1 Introduction.................................................................................................................... 10-110.1.1 Features...................................................................................................................... 10-210.1.2 Modes of Operation ................................................................................................... 10-310.1.2.1 LBC Bus Clock and Clock Ratios ......................................................................... 10-310.1.2.2 Source ID Debug Mode ......................................................................................... 10-310.2 External Signal Descriptions ......................................................................................... 10-410.3 Memory Map/Register Definition ................................................................................. 10-910.3.1 Register Descriptions............................................................................................... 10-1010.3.1.1 Base Registers (BR0BR7) ................................................................................. 10-1110.3.1.2 Option Registers (OR0OR7).............................................................................. 10-1210.3.1.2.1 Address Mask .................................................................................................. 10-1210.3.1.2.2 Option Registers (ORn)GPCM Mode ......................................................... 10-1310.3.1.2.3 Option Registers (ORn)UPM Mode ............................................................ 10-1610.3.1.2.4 Option Registers (ORn)SDRAM Mode ...................................................... 10-1710.3.1.3 UPM Memory Address Register (MAR)............................................................. 10-18


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10.3.1.4 UPM Mode Registers (MnMR) ........................................................................... 10-1910.3.1.5 Memory Refresh Timer Prescaler Register (MRTPR) ........................................ 10-2110.3.1.6 UPM Data Register (MDR) ................................................................................. 10-2210.3.1.7 Local Bus SDRAM Machine Mode Register (LSDMR)..................................... 10-2210.3.1.8 UPM Refresh Timer (LURT)............................................................................... 10-2410.3.1.9 SDRAM Refresh Timer (LSRT).......................................................................... 10-2510.3.1.10 Transfer Error Status Register (LTESR).............................................................. 10-2610.3.1.11 Transfer Error Check Disable Register (LTEDR)................................................ 10-2710.3.1.12 Transfer Error Interrupt Enable Register (LTEIR) .............................................. 10-2710.3.1.13 Transfer Error Attributes Register (LTEATR) ..................................................... 10-2810.3.1.14 Transfer Error Address Register (LTEAR).......................................................... 10-2910.3.1.15 Local Bus Configuration Register (LBCR) ......................................................... 10-2910.3.1.16 Clock Ratio Register (LCRR).............................................................................. 10-3010.4 Functional Description................................................................................................. 10-3110.4.1 Basic Architecture.................................................................................................... 10-3210.4.1.1 Address and Address Space Checking ................................................................ 10-3210.4.1.2 External Address Latch Enable Signal (LALE) .................................................. 10-3310.4.1.3 Data Transfer Acknowledge (TA) ....................................................................... 10-3410.4.1.4 Data Buffer Control (LBCTL)............................................................................. 10-3510.4.1.5 Parity Generation and Checking (LDP)............................................................... 10-3510.4.1.6 Bus Monitor ......................................................................................................... 10-3510.4.2 General-Purpose Chip-Select Machine (GPCM)..................................................... 10-3510.4.2.1 Timing Configuration .......................................................................................... 10-3710.4.2.2 Chip-Select Assertion Timing ............................................................................. 10-4010.4.2.2.1 Programmable Wait State Configuration......................................................... 10-4110.4.2.2.2 Chip-Select and Write Enable Negation Timing ............................................. 10-4110.4.2.2.3 Relaxed Timing ............................................................................................... 10-4210.4.2.2.4 Output Enable (LOE) Timing.......................................................................... 10-4510.4.2.2.5 Extended Hold Time on Read Accesses .......................................................... 10-4510.4.2.3 External Access Termination (LGTA) ................................................................. 10-4610.4.2.4 Boot Chip-Select Operation................................................................................. 10-4710.4.3 SDRAM Machine .................................................................................................... 10-4810.4.3.1 Supported SDRAM Configurations..................................................................... 10-4810.4.3.2 SDRAM Power-On Initialization ........................................................................ 10-4910.4.3.3 Intel PC133 and JEDEC-Standard SDRAM Interface Commands ..................... 10-5010.4.3.4 Page Hit Checking ............................................................................................... 10-5110.4.3.5 Page Management................................................................................................ 10-5110.4.3.6 SDRAM Address Multiplexing ........................................................................... 10-5110.4.3.7 SDRAM Device-Specific Parameters.................................................................. 10-5210.4.3.7.1 Precharge-to-Activate Interval......................................................................... 10-5210.4.3.7.2 Activate-to-Read/Write Interval ...................................................................... 10-53


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10.4.3.7.3 Column Address to First Data OutCAS Latency......................................... 10-5310.4.3.7.4 Last Data In to PrechargeWrite Recovery ................................................... 10-5410.4.3.7.5 Refresh Recovery Interval (RFRC) ................................................................. 10-5410.4.3.7.6 External Address and Command Buffers (BUFCMD).................................... 10-5510.4.3.8 SDRAM Interface Timing ................................................................................... 10-5510.4.3.9 SDRAM Read/Write Transactions....................................................................... 10-5710.4.3.10 SDRAM MODE-SET Command Timing............................................................ 10-5810.4.3.11 SDRAM Refresh.................................................................................................. 10-5810.4.3.11.1 SDRAM Refresh Timing ................................................................................. 10-5810.4.4 User-Programmable Machines (UPMs)................................................................... 10-5910.4.4.1 UPM Requests ..................................................................................................... 10-6010.4.4.1.1 Memory Access Requests................................................................................ 10-6110.4.4.1.2 UPM Refresh Timer Requests ......................................................................... 10-6110.4.4.1.3 Software RequestsRUN Command ............................................................. 10-6210.4.4.1.4 Exception Requests.......................................................................................... 10-6210.4.4.2 Programming the UPMs ...................................................................................... 10-6210.4.4.2.1 UPM Programming Example (Two Sequential Writes to the

RAM Array) ................................................................................................ 10-6310.4.4.2.2 UPM Programming Example (Two Sequential Reads from the

RAM Array) ................................................................................................ 10-6410.4.4.3 UPM Signal Timing............................................................................................. 10-6410.4.4.4 UPM RAM Array ................................................................................................ 10-6510.4.4.4.1 UPM RAM Words ........................................................................................... 10-6610.4.4.4.2 Chip-Select Signal Timing (CSTn) ................................................................. 10-6910.4.4.4.3 Byte Select Signal Timing (BSTn) .................................................................. 10-6910.4.4.4.4 General-Purpose Signals (GnTn, GOn)........................................................... 10-7010.4.4.4.5 Loop Control (LOOP) ..................................................................................... 10-7010.4.4.4.6 Repeat Execution of Current RAM Word (REDO)......................................... 10-7110.4.4.4.7 Address Multiplexing (AMX) ......................................................................... 10-7110.4.4.4.8 Data Valid and Data Sample Control (UTA) ................................................... 10-7210.4.4.4.9 LGPL[0:5] Signal Negation (LAST)............................................................... 10-7310.4.4.4.10 Wait Mechanism (WAEN)............................................................................... 10-7310.4.4.5 Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge ............ 10-7410.4.4.6 Extended Hold Time on Read Accesses .............................................................. 10-7410.4.4.7 Memory System Interface Example Using UPM ................................................ 10-7410.5 Initialization/Application Information ......................................................................... 10-8010.5.1 Interfacing to Peripherals in Multiplexed Address/Data Mode ............................... 10-8010.5.1.1 Multiplexed Address/Data Bus and Unmultiplexed Address Signals ................. 10-8010.5.1.2 Peripheral Hierarchy on the Local Bus................................................................ 10-8110.5.1.3 Peripheral Hierarchy on the Local Bus for Very High Bus Speeds..................... 10-8110.5.1.4 GPCM Timings.................................................................................................... 10-82


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10.5.2 Bus Turnaround ....................................................................................................... 10-8310.5.2.1 Address Phase after Previous Read ..................................................................... 10-8310.5.2.2 Read Data Phase after Address Phase ................................................................. 10-8310.5.2.3 Read-Modify-Write Cycle for Parity Protected Memory Banks ......................... 10-8410.5.2.4 UPM Cycles with Additional Address Phases..................................................... 10-8410.5.3 Interface to Different Port-Size Devices.................................................................. 10-8410.5.4 Interfacing to SDRAM............................................................................................. 10-8610.5.4.1 Basic SDRAM Capabilities of the Local Bus...................................................... 10-8610.5.4.2 Maximum Amount of SDRAM Supported.......................................................... 10-8710.5.4.3 SDRAM Machine Limitations............................................................................. 10-8810.5.4.3.1 Analysis of Maximum Row Number Due to Bank Select

Multiplexing ................................................................................................ 10-8810.5.4.3.2 Bank Select Signals ......................................................................................... 10-8810.5.4.3.3 128-Mbyte SDRAM ........................................................................................ 10-8910.5.4.3.4 256-Mbyte SDRAM ........................................................................................ 10-9110.5.4.3.5 512-Mbyte SDRAM ........................................................................................ 10-9110.5.4.4 Parity Support for SDRAM ................................................................................. 10-9310.5.5 Interfacing to ZBT SRAM....................................................................................... 10-9410.5.6 Interfacing to DSP Host Ports.................................................................................. 10-9510.5.6.1 Interfacing to MSC8122 DSI............................................................................... 10-9510.5.6.2 DSI in Asynchronous SRAM-Like Mode ........................................................... 10-9610.5.6.3 DSI in Synchronous Mode................................................................................... 10-9810.5.6.3.1 Synchronous Single Write ............................................................................. 10-10110.5.6.3.2 Synchronous Single Read.............................................................................. 10-10210.5.6.3.3 Synchronous Burst Write............................................................................... 10-10310.5.6.3.4 Synchronous Burst Read ............................................................................... 10-10410.5.6.4 Broadcast Accesses............................................................................................ 10-104

Chapter 11 Sequencer

11.1 Overview........................................................................................................................ 11-111.1.1 Features...................................................................................................................... 11-211.2 External Signal Description ........................................................................................... 11-211.3 Memory Map/Register Definition ................................................................................. 11-211.4 Register Descriptions ..................................................................................................... 11-311.4.1 PCI Outbound Translation Address Registers (POTARn)......................................... 11-311.4.2 PCI Outbound Base Address Registers (POBARn) .................................................. 11-311.4.3 PCI Outbound Comparison Mask Registers (POCMRn) .......................................... 11-411.4.4 Power Management Control Register (PMCR) ......................................................... 11-511.4.5 Discard Timer Control Register (DTCR) .................................................................. 11-6


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11.5 Functional Description................................................................................................... 11-611.5.1 Transaction Forwarding ............................................................................................. 11-611.5.1.1 Transactions from the Coherency System Bus (CSB) Port ................................... 11-711.5.1.2 Transactions from the PCI Ports............................................................................ 11-711.5.1.3 Transactions from the DMA Port .......................................................................... 11-711.5.2 PCI Outbound Address Translation ........................................................................... 11-711.5.3 Transaction Ordering ................................................................................................. 11-8

Chapter 12 DMA/Messaging Unit

12.1 Features .......................................................................................................................... 12-212.2 External Signal Description ........................................................................................... 12-212.2.1 Detailed Signal Descriptions ..................................................................................... 12-212.3 Memory Map/Register Definition ................................................................................. 12-312.4 Register Descriptions ..................................................................................................... 12-412.4.1 Outbound Message Interrupt Status Register (OMISR) ............................................ 12-412.4.2 Outbound Message Interrupt Mask Register (OMIMR)............................................ 12-612.4.3 Inbound Message Registers ....................................................................................... 12-712.4.4 Outbound Message Registers (OMR0OMR1)......................................................... 12-712.4.5 Doorbell Registers ..................................................................................................... 12-812.4.5.1 Outbound Doorbell Register (ODR)...................................................................... 12-812.4.5.2 Inbound Doorbell Register (IDR).......................................................................... 12-912.4.6 Inbound Message Interrupt Status Register (IMISR) ................................................ 12-912.4.7 Inbound Message Interrupt Mask Register (IMIMR).............................................. 12-1112.4.8 DMA Registers ........................................................................................................ 12-1112.4.8.1 DMA Mode Register (DMAMRn) ...................................................................... 12-1212.4.8.2 DMA Status Register (DMASRn) ....................................................................... 12-1412.4.8.3 DMA Current Descriptor Address Register (DMACDARn) .............................. 12-1512.4.8.4 DMA Source Address Register (DMASARn)..................................................... 12-1612.4.8.5 DMA Destination Address Register (DMADARn)............................................. 12-1612.4.8.6 DMA Byte Count Register (DMABCRn) ........................................................... 12-1712.4.8.7 DMA Next Descriptor Address Register (DMANDARn)................................... 12-1712.4.8.8 DMA General Status Register (DMAGSR)......................................................... 12-1812.5 Functional Description................................................................................................. 12-1812.5.1 Message Unit ........................................................................................................... 12-1812.5.1.1 Messaging Registers (IMR0IMR1) ................................................................... 12-1912.5.1.2 Doorbell Registers (IDR and ODR) .................................................................... 12-1912.5.2 DMA Controller....................................................................................................... 12-1912.5.3 DMA Operation ....................................................................................................... 12-2012.5.3.1 External Control................................................................................................... 12-21


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12.5.3.2 DMA Coherency.................................................................................................. 12-2212.5.3.3 Halt and Error Conditions.................................................................................... 12-2212.5.4 DMA Segment Descriptors...................................................................................... 12-2212.5.4.1 Descriptor in Big-Endian Mode........................................................................... 12-2312.5.4.2 Descriptor in Little-Endian Mode........................................................................ 12-2412.6 Initialization/Application Information ......................................................................... 12-2412.6.1 Initialization Steps in Direct Mode.......................................................................... 12-2412.6.2 Initialization Steps in Chaining Mode ..................................................................... 12-2412.6.3 Initialization Steps in Direct Mode with External Control ...................................... 12-2512.6.4 Initialization Steps in Chaining Mode with External Control ................................. 12-25

Chapter 13 PCI Bus Interface

13.1 Introduction.................................................................................................................... 13-213.1.1 Features...................................................................................................................... 13-313.1.2 Modes of Operation ................................................................................................... 13-313.1.2.1 Host/Agent Mode Configuration ........................................................................... 13-413.1.2.2 Single 64-Bit/Dual 32-Bit Interface Configuration ............................................... 13-413.1.2.3 PCI Arbiter Configuration ..................................................................................... 13-413.2 External Signal Description ........................................................................................... 13-413.3 Memory Map/Register Definitions .............................................................................. 13-1413.3.1 PCI Configuration Access Registers........................................................................ 13-1613.3.1.1 PCI_CONFIG_ADDRESS.................................................................................. 13-1613.3.1.2 PCI_CONFIG_DATA.......................................................................................... 13-1813.3.1.3 PCI Interrupt Acknowledge Register (PCI_INT_ACK)...................................... 13-1813.3.2 PCI Memory-Mapped Control and Status Registers ............................................... 13-1813.3.2.1 PCI Error Status Register (PCI_ESR) ................................................................. 13-1813.3.2.2 PCI Error Capture Disable Register (PCI_ECDR).............................................. 13-1913.3.2.3 PCI Error Enable Register (PCI_EER)................................................................ 13-2013.3.2.4 PCI Error Attributes Capture Register (PCI_EATCR) ........................................ 13-2113.3.2.5 PCI Error Address Capture Register (PCI_EACR) ............................................. 13-2313.3.2.6 PCI Error Extended Address Capture Register (PCI_EEACR) .......................... 13-2313.3.2.7 PCI Error Data Low Capture Register (PCI_EDLCR)........................................ 13-2413.3.2.8 PCI Error Data High Capture Register (PCI_EDHCR)....................................... 13-2413.3.2.9 PCI General Control Register (PCI_GCR).......................................................... 13-2413.3.2.10 PCI Error Control Register (PCI_ECR) .............................................................. 13-2513.3.2.11 PCI General Status Register (PCI_GSR)............................................................. 13-2613.3.2.12 PCI Inbound Translation Address Registers (PITARn)....................................... 13-2613.3.2.13 PCI Inbound Base Address Registers (PIBARn)................................................. 13-2713.3.2.14 PCI Inbound Extended Base Address Registers (PIEBARn) .............................. 13-27


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13.3.2.15 PCI Inbound Window Attribute Registers (PIWARn)......................................... 13-2813.3.3 PCI Configuration Space Registers ......................................................................... 13-2913.3.3.1 Vendor ID Configuration Register....................................................................... 13-3113.3.3.2 Device ID Configuration Register ....................................................................... 13-3113.3.3.3 PCI Command Configuration Register................................................................ 13-3213.3.3.4 PCI Status Configuration Register....................................................................... 13-3313.3.3.5 Revision ID Configuration Register .................................................................... 13-3413.3.3.6 Standard Programming Interface Configuration Register ................................... 13-3413.3.3.7 Subclass Code Configuration Register ................................................................ 13-3513.3.3.8 Base Class Code Configuration Register............................................................. 13-3513.3.3.9 Cache Line Size Configuration Register ............................................................. 13-3613.3.3.10 Latency Timer Configuration Register ................................................................ 13-3613.3.3.11 Header Type Configuration Register ................................................................... 13-3713.3.3.12 BIST Control Configuration Register.................................................................. 13-3713.3.3.13 PIMMR Base Address Configuration Register ................................................... 13-3713.3.3.14 GPL Base Address Register 0.............................................................................. 13-3813.3.3.15 GPL Base Address Registers 12 ........................................................................ 13-3813.3.3.16 GPL Extended Base Address Registers 12........................................................ 13-3913.3.3.17 Subsystem Vendor ID Configuration Register .................................................... 13-3913.3.3.18 Subsystem Device ID Configuration Register..................................................... 13-4013.3.3.19 Capabilities Pointer Configuration Register........................................................ 13-4013.3.3.20 Interrupt Line Configuration Register ................................................................. 13-4113.3.3.21 Interrupt Pin Configuration Register ................................................................... 13-4113.3.3.22 Minimum Grant Configuration Register ............................................................. 13-4113.3.3.23 Maximum Latency Configuration Register ......................................................... 13-4213.3.3.24 PCI Function Configuration Register .................................................................. 13-4213.3.3.25 PCI Arbiter Control Register (PCIACR)............................................................. 13-4313.3.3.26 Hot Swap Register Block..................................................................................... 13-4413.4 Functional Description................................................................................................. 13-4513.4.1 PCI Bus Arbitration ................................................................................................. 13-4513.4.1.1 Bus Parking.......................................................................................................... 13-4513.4.1.2 Arbitration Algorithm.......................................................................................... 13-4513.4.1.3 Broken Master Lock-Out ..................................................................................... 13-4613.4.1.4 Master Latency Timer.......................................................................................... 13-4713.4.2 Bus Commands ........................................................................................................ 13-4713.4.3 PCI Protocol Fundamentals ..................................................................................... 13-4813.4.3.1 Basic Transfer Control......................................................................................... 13-4813.4.3.2 Addressing ........................................................................................................... 13-4813.4.3.3 Device Selection .................................................................................................. 13-4913.4.3.4 Byte Enable Signals............................................................................................. 13-4913.4.3.5 Bus Driving and Turnaround ............................................................................... 13-50


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13.4.3.6 Bus Transactions.................................................................................................. 13-5013.4.3.7 Read and Write Transactions ............................................................................... 13-5013.4.3.8 Transaction Termination ...................................................................................... 13-5213.4.4 Other Bus Operations............................................................................................... 13-5513.4.4.1 Fast Back-to-Back Transactions .......................................................................... 13-5513.4.4.2 Dual Address Cycles............................................................................................ 13-5513.4.4.3 Data Streaming .................................................................................................... 13-5513.4.4.4 Host Mode Configuration Access........................................................................ 13-5613.4.4.5 Agent Mode Configuration Access ..................................................................... 13-5713.4.4.6 Special Cycle Command................

mpc8349ea powerquicc ii pro integrated host processor...

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