mpi 8237.ppt

8/18/2019 mpi 8237.ppt

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DIRECT MEMORYDIRECT MEMORYACCESSACCESS

82378237

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OVERVIEWOVERVIEW Introduction to DMAIntroduction to DMA

Basic process o DMABasic process o DMA

I!p"e!entin# DMA in a co!puter s$ste!I!p"e!entin# DMA in a co!puter s$ste!

Data transer usin# DMA contro""erData transer usin# DMA contro""er Interna" con%#uration o a DMA contro""erInterna" con%#uration o a DMA contro""er

8237 &"oc' dia#ra!8237 &"oc' dia#ra!

(rocess o DMA transer(rocess o DMA transer

DMA transer !odesDMA transer !odes 8237 pins8237 pins

Re#istersRe#isters

Su!!ar$Su!!ar$

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Direct Me!or$ AccessDirect Me!or$ Access IntroductionIntroduction

An i!portant aspect #o)ernin# t*eAn i!portant aspect #o)ernin# t*e

Co!puter S$ste! peror!ance is t*eCo!puter S$ste! peror!ance is t*etranser o data &et+een !e!or$ and I,Otranser o data &et+een !e!or$ and I,Ode)ices-de)ices-

T*e operation in)o")es "oadin# pro#ra!s or T*e operation in)o")es "oadin# pro#ra!s or

data %"es ro! dis' into !e!or$. sa)in# %"edata %"es ro! dis' into !e!or$. sa)in# %"eon dis'. and accessin# )irtua" !e!or$on dis'. and accessin# )irtua" !e!or$pa#es on an$ secondar$ stora#e !ediu!-pa#es on an$ secondar$ stora#e !ediu!-

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Basic process of DMABasic process of DMAIn maximum mode:In maximum mode:

/ands*a'in# (ins0 R1,T and R1,T4/ands*a'in# (ins0 R1,T and R1,T4 DMA re5uest and ac'no+"ed#eDMA re5uest and ac'no+"ed#e

Se5uences0Se5uences0

6 (erip*era" asserts one o t*e re5uest pins. e-#- R1,T or R1,T46 (erip*era" asserts one o t*e re5uest pins. e-#- R1,T or R1,T4

R1,T4 *as *i#*er priorit$6R1,T4 *as *i#*er priorit$6

26 C( co!p"etes its current &us c$c"e and enters into a /O9D state26 C( co!p"etes its current &us c$c"e and enters into a /O9D state

36 C( #rants t*e ri#*t o &us contro" &$ assertin# a #rant si#na" )ia36 C( #rants t*e ri#*t o &us contro" &$ assertin# a #rant si#na" )iat*e sa!e pin as t*e re5uest si#na"-t*e sa!e pin as t*e re5uest si#na"-

:6 DMA operation starts:6 DMA operation starts;6 pon co!p"etion o t*e DMA operation. t*e perip*era" asserts t*e;6 pon co!p"etion o t*e DMA operation. t*e perip*era" asserts t*ere5uest,#rant pin a#ain to re"in5uis* &us contro"-re5uest,#rant pin a#ain to re"in5uis* &us contro"-

In minimum mode:In minimum mode:

T*e /O9D and /9DA pins are used or *ands*a'in# T*e /O9D and /9DA pins are used or *ands*a'in#

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Co!puter S$ste! +it*Co!puter S$ste! +it*

DMADMA

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Consider a t$pica" s$ste! consistin# o a C(Consider a t$pica" s$ste! consistin# o a C(.!e!or$ and one or !ore input,output.!e!or$ and one or !ore input,outputde)ices as s*o+n in %#- Assu!e one o t*ede)ices as s*o+n in %#- Assu!e one o t*e

I,O de)ices is a dis' dri)e and t*at t*eI,O de)ices is a dis' dri)e and t*at t*eco!puter !ust "oad a pro#ra! ro! t*isco!puter !ust "oad a pro#ra! ro! t*isdri)e into !e!or$-dri)e into !e!or$-

T*e C( +ou"d read t*e %rst &$te o t*e T*e C( +ou"d read t*e %rst &$te o t*e

pro#ra! and t*en +rite t*at &$te to !e!or$-pro#ra! and t*en +rite t*at &$te to !e!or$- T*en it +ou"d do t*e sa!e or t*e second T*en it +ou"d do t*e sa!e or t*e second&$te. unti" it *ad "oaded t*e entire pro#ra!&$te. unti" it *ad "oaded t*e entire pro#ra!into !e!or$-into !e!or$- contcont

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T*is process pro)es to &e ine<cient- T*is process pro)es to &e ine<cient-9oadin# data into. and t*en +ritin# data out9oadin# data into. and t*en +ritin# data outo t*e C( si#ni%cant"$ s"o+s do+n t*eo t*e C( si#ni%cant"$ s"o+s do+n t*e

transer- T*e C( does not !odi$ t*e datatranser- T*e C( does not !odi$ t*e dataat a"". so it on"$ ser)es as an additiona" stopat a"". so it on"$ ser)es as an additiona" stopor data on t*e +a$ to it=s %na" destinaion-or data on t*e +a$ to it=s %na" destinaion-

T*e process +ou"d &e !uc* 5uic'er i +e T*e process +ou"d &e !uc* 5uic'er i +e

cou"d &$pass t*e C( > transer datacou"d &$pass t*e C( > transer datadirect"$ ro! t*e I,O de)ice to !e!or$-direct"$ ro! t*e I,O de)ice to !e!or$-

Direct Me!or$ Access does e?act"$ t*at-Direct Me!or$ Access does e?act"$ t*at-

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I!p"e!entin# DMA in aI!p"e!entin# DMA in a

Co!puter S$ste!Co!puter S$ste! A DMA contro""er i!p"e!ents direct !e!or$A DMA contro""er i!p"e!ents direct !e!or$

access in a co!puter s$ste!-access in a co!puter s$ste!- It connects direct"$ to t*e I,O de)ice at oneIt connects direct"$ to t*e I,O de)ice at one

end and to t*e s$ste! &uses at t*e ot*erend and to t*e s$ste! &uses at t*e ot*erend- It a"so interacts +it* t*e C(. &ot* )iaend- It a"so interacts +it* t*e C(. &ot* )iat*e s$ste! &uses and t+o ne+ directt*e s$ste! &uses and t+o ne+ directconnections-connections-

It is so!eti!es reerred to as a c*anne"- InIt is so!eti!es reerred to as a c*anne"- Inan a"ternate con%#uration. t*e DMAan a"ternate con%#uration. t*e DMAcontro""er !a$ &e incorporated direct"$ intocontro""er !a$ &e incorporated direct"$ intot*e I,O de)ice-t*e I,O de)ice-

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Data Transer usin# DMAData Transer usin# DMA

Contro""erContro""er To transer data ro! an I,O de)ice to To transer data ro! an I,O de)ice to

!e!or$. t*e DMA contro""er %rst sends a Bus!e!or$. t*e DMA contro""er %rst sends a BusRe5uest to t*e C( &$ settin# BR to - W*enRe5uest to t*e C( &$ settin# BR to - W*en

it is read$ to #rant t*is re5uest. t*e C( setsit is read$ to #rant t*is re5uest. t*e C( setsit=s Bus #rant si#na". B to -it=s Bus #rant si#na". B to -

T*e C( a"so tri@states it=s address.data. and T*e C( a"so tri@states it=s address.data. andcontro" "ines t*us tru"$ #rantin# contro" o t*econtro" "ines t*us tru"$ #rantin# contro" o t*e

s$ste! &uses to t*e DMA contro""er-s$ste! &uses to t*e DMA contro""er- T*e C( +i"" continue to tri@state it=s outputs T*e C( +i"" continue to tri@state it=s outputs

as "on# as BR is asserted-as "on# as BR is asserted-contcont

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Con%#urationCon%#uration T*e DMA contro""er inc"udes se)era" re#isters 0@ T*e DMA contro""er inc"udes se)era" re#isters 0@

T*e DMA Address Re#ister contains t*e !e!or$ T*e DMA Address Re#ister contains t*e !e!or$address to &e used in t*e data transer- T*e C(address to &e used in t*e data transer- T*e C(treats t*is si#na" as one or !ore output ports-treats t*is si#na" as one or !ore output ports-

T*e DMA Count Re#ister. a"so ca""ed Word Count T*e DMA Count Re#ister. a"so ca""ed Word CountRe#ister. contains t*e no- o &$tes o data to &eRe#ister. contains t*e no- o &$tes o data to &etranserred- 9i'e t*e DMA address re#ister. it too istranserred- 9i'e t*e DMA address re#ister. it too is

treated as an O,( port +it* a di- Address6 &$ t*etreated as an O,( port +it* a di- Address6 &$ t*eC(-C(-

T*e DMA Contro" Re#ister accepts co!!ands ro! T*e DMA Contro" Re#ister accepts co!!ands ro!t*e C(- It is a"so treated as an O,( port &$ t*e C(-t*e C(- It is a"so treated as an O,( port &$ t*e C(-

contcont

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!ost DMA contro""ers a"so *a)e a!ost DMA contro""ers a"so *a)e aStatus Re#ister- T*is re#isterStatus Re#ister- T*is re#ister

supp"ies inor!ation to t*e C(.supp"ies inor!ation to t*e C(.+*ic* accesses it as an I,( port-+*ic* accesses it as an I,( port-

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Interna" Con%#uration oInterna" Con%#uration o

DMADMA Contro""erContro""er

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8237 &"oc' dia#ra!8237 &"oc' dia#ra!

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(rocess o DMA(rocess o DMA Transer Transer To initiate a DMA transer. t*e C( "oads t*e To initiate a DMA transer. t*e C( "oads t*eaddress o t*e %rst !e!or$ "ocation o t*eaddress o t*e %rst !e!or$ "ocation o t*e!e!or$ &"oc' to &e read or +ritten ro!6 into!e!or$ &"oc' to &e read or +ritten ro!6 into

t*e DMA address re#ister- It does *is )ia an I,Ot*e DMA address re#ister- It does *is )ia an I,Ooutput instruction. suc* as t*e OT(T instructionoutput instruction. suc* as t*e OT(T instructionor t*e re"ati)e"$ si!p"e C(-or t*e re"ati)e"$ si!p"e C(-

It t*en +rites t*e no- o &$tes to &e transerredIt t*en +rites t*e no- o &$tes to &e transerredinto t*e DMA count re#ister in t*e sane !anner-into t*e DMA count re#ister in t*e sane !anner-

ina""$. it +rites one or !ore co!!ands to t*eina""$. it +rites one or !ore co!!ands to t*eDMA contro" re#ister-DMA contro" re#ister-contcont

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T*ese co!!ands !a$ speci$ transer T*ese co!!ands !a$ speci$ transeroptions suc* as t*e DMA transer !ode. &utoptions suc* as t*e DMA transer !ode. &uts*ou"d a"+a$s speci$ t*e direction o t*es*ou"d a"+a$s speci$ t*e direction o t*etranser. eit*er ro! I,O to !e!or$ or ro!transer. eit*er ro! I,O to !e!or$ or ro!!e!or$ to I,O-!e!or$ to I,O-

T*e "ast co!!and causes t*e DMA T*e "ast co!!and causes t*e DMA

contro""er to initiate t*e transer- T*econtro""er to initiate t*e transer- T*econtro""er t*en sets BR to and. once Bcontro""er t*en sets BR to and. once B&eco!es . seies contro" o t*e s$ste!&eco!es . seies contro" o t*e s$ste!&uses-&uses-

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DMA Transer ModesDMA Transer Modes

Modes )ar$ &$ *o+ t*e DMA contro""erModes )ar$ &$ *o+ t*e DMA contro""er

deter!ines +*en to transer data. &ut t*edeter!ines +*en to transer data. &ut t*e

actua" data transer process is t*e sa!e or a""actua" data transer process is t*e sa!e or a""

t*e !odes-t*e !odes-

BRST !odeBRST !ode So!eti!es ca""ed B"oc' Transer Mode-So!eti!es ca""ed B"oc' Transer Mode- An entire &"oc' o data is transerred in one conti#uous se5uence-An entire &"oc' o data is transerred in one conti#uous se5uence-

Once t*e DMA contro""er is #ranted access to t*e s$ste! &uses &$ t*eOnce t*e DMA contro""er is #ranted access to t*e s$ste! &uses &$ t*eC(. it transers a"" &$tes o data in t*e data &"oc' &eore re"easin#C(. it transers a"" &$tes o data in t*e data &"oc' &eore re"easin#contro" o t*e s$ste! &uses &ac' to t*e C(-contro" o t*e s$ste! &uses &ac' to t*e C(-

T*is !ode is useu" or "oadin# pro#ra!s or data %"es into !e!or$. T*is !ode is useu" or "oadin# pro#ra!s or data %"es into !e!or$.

&ut it does render t*e C( inacti)e or re"ati)e"$ "on# periods o ti!e-&ut it does render t*e C( inacti)e or re"ati)e"$ "on# periods o ti!e-contcont

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CYC9E STEA9I ModeCYC9E STEA9I Mode Via&"e a"ternati)e or s$ste!s in +*ic* t*e C( s*ou"d notVia&"e a"ternati)e or s$ste!s in +*ic* t*e C( s*ou"d not

&e disa&"ed or t*e "en#t* o ti!e needed or Burst transer&e disa&"ed or t*e "en#t* o ti!e needed or Burst transer!odes-!odes-

DMA contro""er o&tains access to t*e s$ste! &uses as inDMA contro""er o&tains access to t*e s$ste! &uses as in&urst !ode. usin# BR > B si#na"s- /o+e)er. it transers&urst !ode. usin# BR > B si#na"s- /o+e)er. it transersone &$te o data and t*en deasserts BR. returnin# contro" oone &$te o data and t*en deasserts BR. returnin# contro" ot*e s$ste! &uses to t*e C(- It continua""$ issues re5uestst*e s$ste! &uses to t*e C(- It continua""$ issues re5uests)ia BR. transerrin# one &$te o data per re5uest. unti" it *as)ia BR. transerrin# one &$te o data per re5uest. unti" it *astranserred it=s entire &"oc' o data-transerred it=s entire &"oc' o data-contcont

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B$ continua""$ o&tainin# and re"easin# contro" oB$ continua""$ o&tainin# and re"easin# contro" ot*e s$ste! &uses. t*e DMA contro""er essentia""$t*e s$ste! &uses. t*e DMA contro""er essentia""$inter"ea)es instruction > data transers- T*e C(inter"ea)es instruction > data transers- T*e C(processes an instruction. t*en t*e DMA contro""erprocesses an instruction. t*en t*e DMA contro""ertransers a data )a"ue. and so on-transers a data )a"ue. and so on-

T*e data &"oc' is not transerred as 5uic'"$ as in T*e data &"oc' is not transerred as 5uic'"$ as in&urst !ode. &ut t*e C( is not id"ed or as "on# as&urst !ode. &ut t*e C( is not id"ed or as "on# asin t*at !ode-in t*at !ode-

seu" or contro""ers !onitorin# data in rea" ti!e-seu" or contro""ers !onitorin# data in rea" ti!e-

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TRAS(ARET Mode TRAS(ARET Mode T*is re5uires t*e !ost ti!e to transer a &"oc' o data. T*is re5uires t*e !ost ti!e to transer a &"oc' o data.

$et it is a"so t*e !ost e<cient in ter!s o o)era""$et it is a"so t*e !ost e<cient in ter!s o o)era""s$ste! peror!ance-s$ste! peror!ance-

T*e DMA contro""er on"$ transers data +*en t*e C( is T*e DMA contro""er on"$ transers data +*en t*e C( isperor!in# operations t*at do not use t*e s$ste!peror!in# operations t*at do not use t*e s$ste!&uses-&uses-

or e?a!p"e. t*e Re"ati)e"$ si!p"e C( *as se)era"or e?a!p"e. t*e Re"ati)e"$ si!p"e C( *as se)era"states t*at !o)e or process data so"e"$ +it*in t*e C(0states t*at !o)e or process data so"e"$ +it*in t*e C(0

O(0 o operation6O(0 o operation6

9DAC;0 AC9DAC;0 ACDRDR

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8237 pins8237 pins

C9F0 S$ste! c"oc'C9F0 S$ste! c"oc' CSCSGG0 C*ip se"ect decoder output60 C*ip se"ect decoder output6 RESET0 C"ears re#isters. sets !as' re#isterRESET0 C"ears re#isters. sets !as' re#ister READY0 4 or insertin# +ait statesREADY0 4 or insertin# +ait states /9DA0 Si#na"s t*at t*e/9DA0 Si#na"s t*at t*e HHp *as re"in5uis*ed &usesp *as re"in5uis*ed &uses DRE13 DRE140 DMA re5uest input or eac* c*anne"DRE13 DRE140 DMA re5uest input or eac* c*anne" DB7@DB40 Data &us pinsDB7@DB40 Data &us pins IORIORGG0 Bidirectiona" pin used durin# pro#ra!!in#0 Bidirectiona" pin used durin# pro#ra!!in#and durin# a DMA +rite c$c"eand durin# a DMA +rite c$c"e IOWIOWGG0 Bidirectiona" pin used durin# pro#ra!!in#0 Bidirectiona" pin used durin# pro#ra!!in#and durin# a DMA read c$c"eand durin# a DMA read c$c"e

EO(EO(GG0 End o process is a &idirectiona" si#na" used as input to ter!inate a DMA0 End o process is a &idirectiona" si#na" used as input to ter!inate a DMAprocess or as output to si#na" t*e end o t*e DMA transerprocess or as output to si#na" t*e end o t*e DMA transer A3@A40 Address pins or se"ectin# interna" re#istersA3@A40 Address pins or se"ectin# interna" re#isters A7@A:0 Outputs t*at pro)ide part o t*e DMA transer addressA7@A:0 Outputs t*at pro)ide part o t*e DMA transer address /R10 DMA re5uest output/R10 DMA re5uest output DACF3@DACF40 DMA ac'no+"ed#e or eac* c*anne"-DACF3@DACF40 DMA ac'no+"ed#e or eac* c*anne"- AE0 Address ena&"e si#na"AE0 Address ena&"e si#na"

ADSTB0 Address stro&eADSTB0 Address stro&e MEMRMEMRGG0 Me!or$ read output used in DMA read c$c"e0 Me!or$ read output used in DMA read c$c"e

GG

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8237 re#isters8237 re#isters

CAR Current Address Re#ister60 *o"ds t*eCAR Current Address Re#ister60 *o"ds t*e

J@&it !e!or$ address used or t*eJ@&it !e!or$ address used or t*e

DMA transerDMA transer

one or eac* c*anne"6. eit*er incre!ented orone or eac* c*anne"6. eit*er incre!ented or

decre!ented durin# t*e operationdecre!ented durin# t*e operation

CWCR Current Word Count Re#ister60 (ro#ra!sCWCR Current Word Count Re#ister60 (ro#ra!s

a c*anne" or t*e nu!&er o &$tes up to J:F6a c*anne" or t*e nu!&er o &$tes up to J:F6

transerred durin# a DMA operationtranserred durin# a DMA operation BA Base Address6 and WC Word Count60 sed +*enBA Base Address6 and WC Word Count60 sed +*en

auto@initia"iation is se"ected or a c*anne". to re"oad t*eauto@initia"iation is se"ected or a c*anne". to re"oad t*eCAR and CWCR +*en DMA is co!p"ete-CAR and CWCR +*en DMA is co!p"ete-

CR Co!!and Re#ister60 (ro#ra!s t*e operation o t*eCR Co!!and Re#ister60 (ro#ra!s t*e operation o t*e

contro""ercontro""er

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8237 re#isters8237 re#isters MR Mode Re#ister60 (ro#ra!s t*eMR Mode Re#ister60 (ro#ra!s t*e

!ode o operation or a c*anne"!ode o operation or a c*anne"one or eac* c*anne"6-one or eac* c*anne"6-

RR Re5uest Re#ister60 sed toRR Re5uest Re#ister60 sed tore5uest DMA transer )ia sot+arere5uest DMA transer )ia sot+are!e!or$@to@!e!or$ transers6!e!or$@to@!e!or$ transers6

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8237 re#isters8237 re#isters MR Mas' Re#ister60MR Mas' Re#ister60TheThe

mode register,mode register, programsprograms

the mode of operation forthe mode of operation for

achannel. Each channelsachannel. Each channels

has its own mode registerhas its own mode register

(RD!R"I#$DE$..%(RD!R"I#$DE$..%

SR Status Re#ister60SR Status Re#ister60S*o+s t*e status oS*o+s t*e status oeac* DMA c*anne"eac* DMA c*anne"

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Su!!ar$Su!!ar$ Ad)anta#es o DMAAd)anta#es o DMA

Co!puter s$ste! peror!ance is i!pro)ed &$ directCo!puter s$ste! peror!ance is i!pro)ed &$ directtranser o data &et+een !e!or$ and I,O de)ices.transer o data &et+een !e!or$ and I,O de)ices.

&$passin# t*e C(-&$passin# t*e C(- C( is ree to peror! operations t*at do not useC( is ree to peror! operations t*at do not uses$ste! &uses-s$ste! &uses-

Disad)anta#es o DMADisad)anta#es o DMA

In case o Burst Mode data transer. t*e C( isIn case o Burst Mode data transer. t*e C( isrendered inacti)e or re"ati)e"$ "on# periods o ti!e-rendered inacti)e or re"ati)e"$ "on# periods o ti!e-

mpi 8237.ppt

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