mpmc unit3.pdf

Microprocessor Microcontroller Unit III (16 Marks) Page

Om Sakthi

ADHIPARASAKTHIENGINEERINGCOLLEGE

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

EC2304-MICROPROCESSORS AND MICROCONTROLLERS

UNIT- III

MICROPROCESSOR PERIPHERAL INTERFACING

1. With neat block diagram explain the 8255 Programmable Peripheral Interface.(OR)Parallel communication Interface

• 8255 has three registers of 8 bits each and are called as Port A, Port B and Port C. • The port A and upper 4 bits of Port C are grouped and called as Group A. • Similarly, Port B and lower 4 bits of Port C are grouped as Group B. • In addition to three registers A, B and C, there is another register called control register. • The contents written into the control register decides the operating modes of the three

parallel ports. • In order to identify the four registers, 8255 uses two address lines A0 and A1.

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Pin diagram of 8255

• PA0 – PA7, PB0 – PB7, PC0 – PC7 - These three ports of 8255 needs 8 lines each and so 24 pins are allotted for ports and connected to external Input or output devices.

• A0 and A1 – These pins are allotted for selecting one of the 4 registers available in 8255. • D0-D7 - Data lines are connected to the data bus of the processor. • RD and WR - Active low control signals for reading and writing to the registers, • CS – It is made to low for chip select CS , This signal is obtained from the decoder which

decodes the address lines and identifies the 8255 addressing. • RESET - Reset 8255 • VCC - +5 v power supply • GND – connected to Ground

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These are two basic modes of operation of 8255 • I/O mode

Three modes of operation in I/O Mode, Mode 0 Mode 1 Mode 2.

• Bit Set-Reset mode (BSR) In BSR mode only port C (PC0-PC7) can be used to set or reset its individual port

bits. BSR Control Word Format

Control Word Format of 8255

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2. Explain the programming and various operating modes of 8255 PPI in detail.

These are two basic modes of operation of 8255 • I/O mode

Three modes of operation in I/O Mode, Mode 0 Mode 1 Mode 2.

• Bit Set-Reset mode (BSR) In BSR mode only port C (PC0-PC7) can be used to set or reset its individual port

bits. BSR Control Word Format

Control Word Format of 8255

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MODE 0 – Basic Input/ Output

Mode 0 provides simple input and output operations for each of the three ports

There are two 8 bit ports (A and B) and two 4 bit ports (C lower) and (C upper)

Any port can be input or an output port

Mode 1: (Strobed input/output mode)

The 8-bit data port is either Port A or Port B and can be either input or output.

Both inputs and outputs are latched.

The 4-bit control port is either Port C upper or Port C lower bits and can be used for control and status of the 8-bit port.

MODE1 – INPUT PORT

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Input control and opération (mode 1 ): Step 1

The input device places data in the data lines i.e., the Port A or Port B lines. This is communicated to 8255 by making STB (Strobe Input) low.

Step 2 8255 acknowledges the receipt of the data to the input by making IBF

(Input Buffer Full) high. This also indicates that the data has been latched into the input port.

Step 3 8255 then makes INTR line (Interrupt Request) high and applies an

interrupt to the processor. This signal is applied with a condition that INTE (Interrupt Enable) must be high. INTE for Port A is controlled by bit set/reset of PC4 and INTE for port B is controlled by bit set/reset of PC2. PC2 and PC4 can be controlled using BSR mode.

Step 4 The processor in the interrupt service routine reads the data from the corresponding input port. Reading from the port is done by selecting the 8255 port and applying RD active low signal.

Step 5 During Read operation the RD signal low. When RD signal goes low, INTR signal is reset. IBF is reset by the rising edge of the RD input.

MODE – 1 OUTPUT PORT

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Output control signal and operation (mode 1) : The control signals or handshake signals used for the output in mode 1 of 8255 are OBF,

ACK and INTR.

Step 1 The processor will initiate the data transmission by writing the data to be

transmitted to the output device to the corresponding port of 8255. Step 2

To transfer the data to the output device, 8255 will make OBF (Output Buffer Full- active low signal) “low” to indicate that the CPU has written data to be given to the specified port.

The OBF flip flop will be set by the rising edge of the WR input. Step 3

The data available on the output port pins are then read by the output device.

After receiving data from the port pins, ACK is an active low input signal to 8255 from the peripheral device indicating that it is accepting data.

OBF output signal of 8255 is reset by ACK input being low. Step 4

8255 will now inform to the processor that data has been transferred to the output device by making INTR (Interrupt Request) line high.

A “high” on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU.

INTR is set when ACK is a “one”, OBF is a “one” and INTE is a “one”. Step 5

In the interrupt Service routine, the processor writes the next data to be transmitted to the output device to the output port of 8255.

INTR signal is reset by the falling edge of WR. Mode 2 (Strobed bidirectional I/O):

In mode 2, data is transmitted and received via port A pins (bi-directional bus I/O) with handshaking capability.

Only Port A can be configured in Mode 2 and is used as a bi-directional port while port C is used for handshaking signals.

Meanwhile, Port B can be configured to be in Mode 0 or 1 and Port B cannot be configured for mode2.

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Control signals and operations:

The input and output operation of 8255 in mode is similar to the operation in mode 1 except that the Port A is bidirectional port.

The data is transmitted and received through the Port A lines. For the output operation, as in mode 1, the data transfer is initiated by the processor by

making the active low signal OBF low. This indicates that the processor has written data to output port. The output device after reading the data will give an acknowledgement by making ACK

(Acknowledge signal – Active low signal) low. The processor will then be interrupted by 8255 to indicate that the output data port is

ready for next data output or transmission. Here, the interrupt can be applied to processor only if INTE 1 flip flop associated with

OBF and controlled by PC4 is set by the processor earlier The input operation is also similar to mode 1 operation. Here the data transfer is

initiated by the input device by placing the data on the port pins. Then an active low control signal STB is given to 8255 by the input device for taking

data. 8255 will now latch up the data to its port and then give an active high signal IBF to the

input device. 8255 will then issue an interrupt signal to the processor to indicate that a data is readily

available for read operation. Here, the interrupt can be applied to processor only if INTE2 flip flop associated with IBF

and controlled by PC4 is set by the processor earlier.

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3. Show how two 8255 chip can be connected in an connected in an 8086-based system to form a 16-bit port.

• Interfacing of 8255 with 8086 requires two 8255 chips for 16 bit input and output • M/IO will be inverted before connecting to the decoder • RD and WR are directly connected to 8086

4. Explain serial communication Interface USART (8251) with neat diagram 8251 is Universal Synchronous Asynchronous Receiver Transmitter (USART) is used for

serial data communication.

8251 receives parallel data from the CPU and transmits the same in serial form. This device also receives serial data from the outside and converts them into parallel data and sends it to the CPU.

8251 can support both synchronous and asynchronous transmission formats and is programmable. It supports full duplex serial transmission and reception and variable baud rates.

Basically it consists of a parallel to serial shift register for the transmitting over TXD line from buffer and a serial to parallel converter for data received on the RXD line.

Block diagram of the 8251 USART

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Microprocessor Microcontroller Unit III (16 Marks)

• D0 to D7- Data bus: A group of Bidirectional data bus that is used for data and control word transfer between CPU and 8251.

• RESET: A logic High applied on this pin pits 8251 into “"reset status." The time duration required for reset signal is six clock pulses.

• CLK: Clock signal is used to generate internal device timing. CLK signal is independent of RXC (receive clock) or TXC (Transmit clock). In general, the CLK frequency must be much higher than the RXC and TXC frequencies.

• WR - Write Data/Command: It is an active low input signal for writing data and control words from the CPU into the 8251.

• RD- Read Data: It is an active low input signal for reading data and status words from the 8251.

• C/D - Control/Data: It is an input signal for selecting data or command words and status words when the 8251 is accessed by the CPU. If C/D = low, data will be accessed. If C/D = high, command word or status word will be accessed.

• CS - Chip Select: It is an "Active low" input signal which selects the 8251 for CPU accesses.

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• TXD - Transmit Data line: It is an output signal for transmitting serial converted data from 8251.

• TXRDY - Transmitter Ready: It is an output signal which indicates 8251is ready to accept a transmitted data character. But the terminal is always at low level if CTS = high

• TXEMPTY - Transmitter Empty: It is an output signal that indicates that the 8251 has transmitted all the characters and had no data character to be transmission.

• TXC - Transmitter Clock: This is a clock input signal that determines the transfer speed of transmitted data or in other words, the baud rate for transmission.

• In "synchronous mode," the baud rate will be the same as the frequency of TXC.

• In "asynchronous mode", it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16 or 1/64 the TXC.

• RXD- Receive Data: A signal line that receives serial data.

• RXRDY - Receiver Ready: It is a signal that indicates that the 8251 contains a character that is ready to READ and CPU can read the data.

• RXC - Receiver Clock: This is a clock input signal that determines the transfer speed of received data or the baud rate of reception.

• In "synchronous mode," the baud rate is the same as the frequency of RXC.

• In "asynchronous mode," it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16, 1/64 the RXC.

• SYNDET/BD - Sync detect/break detect

• DSR - Data Set Ready: This is an input port for MODEM interface.

• DTR - Data Terminal Ready: This is an output port for MODEM interface.

• CTS - Clear to Send data: This is an input signal for MODEM interface which is used for controlling a transmit circuit.

• RTS - Request to Send: This is an output port for MODEM interface.

5. Explain the 8279 keyboard and display controller with neat sketch. The major features of 8279 are listed below.

Supports up to a maximum of 64 key matrix with 2-key lockout or N-key rollover options

Supports up to 16 digit display interface with many options Simultaneous keyboard and display operations

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8 character FIFO memory to store codes of keys pressed 16 byte display-RAM to store display data to 16 digits

IC8279 basically has three sections. The first section is the display section with its own display RAM. The next section is keyboard scan section with FIFO registers. The last one is the control logic with signals for interfacing to the processor.

The control section basically consists of data bus buffer for interfacing to the processor.

The I/O section uses the control signals such as A0, CS, RD and WR. CS is used to select the IC and this is an active low signal. Similarly RD and WR are the active low control signals for indication of

direction of data transfer on the data bus, DB0-DB7. A logic 1 on A0 line means the data bus content is a command or status. A

logic 0 means the data bus content is the data for the IC8279.

Keyboard section

• 8279 has four scan lines SL0 – SL3and eight return lines RL0 – RL7, a shift line and a control line. Scan lines are connected to rows of the keyboard. Return lines are connected to column of the keyboard. Shift line and control lines are connected to shift

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and control keys. IRQ: Interrupt request, becomes 1 when a key is pressed, data is available.

• The scan counter has two modes to scan the key matrix Encoded scan Decoded scan

• In keyboard encoded scan, row is output on the low order three lines and it is decoded by 3 to 8 decoder to provide 8 x 8 keyboard

• In keyboard decoded scan, four lines are connected to four rows of keyboard to provide 4x8 keyboard

• Data format generated for each key pressed is

• This information is stored in FIFO (First In First Out) RAM. The status logic generates an

interrupt after each FIFO read operation till the FIFO is empty. Modes of Keyboard section • Encoded scan keyboard – 2 key lock out • Encoded scan keyboard - N key roll over • Decoded scan keyboard – 2 key lock out • Decoded scan keyboard - N key roll over • Encoded scan sensor Matrix • Decoded scan sensor Matrix • Strobed input Two types of Debouncing

• 2 key Lock out In this mode of operation, If two keys are pressed within a debounce cycle

(simultaneously), no key is recognized till one of them remains closed and the other is released. The last key that remains depressed is considered as single valid key depression.

• N-Key Rollover : In this mode, each key depression is treated independently. When a key is

pressed, the debounce circuit waits for 2 keyboards scans and then checks whether the key is still depressed. If it is still depressed, the code is entered in FIFO RAM.

• Scanned Sensor Matrix : In this mode, a sensor array can be interfaced with 8279 using either encoded or

decoded scans. With encoded scan 8*8 sensor matrix or with decoded scan 4*8 sensor matrix can be interfaced. The sensor codes are stored in the CPU addressable sensor RAM.

• Strobed input:

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In this mode, if the control line goes low, the data on return lines is stored in the FIFO byte by byte.

FIFO Status FIFO status is used in keyboard and strobed input modes to indicate the number

of characters in the FIFO and to indicate error. Overrun error occurs when the entry of another character into a full FIFO is

attempted. Underrun error occurs when the CPU tries to read an empty FIFO.

Display Section

• It consist of four scan lines SL0 – SL3, two 4 bit output ports(A0 – A3 and B0 – B3), 16 x 8 display RAM and Blank display line for display operation.

• For BCD type seven segment LED display, only 4 bit codes are needed. Both right and left entry display formats are possible.

• Display RAM can be loaded or read by the CPU after the correct mode and address is set. When the keyboard is in the decoded scan, display will automatically be in decoded mode, i.e 4 characters will be displayed.

• BD is used to blank display during digit switching • OUT A3-A0/B3-B0: Outputs that sends data to the most significant/least significant

nibble of display. Display Mode

• Left Entry Mode : In the left entry mode, the data is entered from left side of the display unit. The first entry is displayed on the leftmost display and the sixteenth entry on the rightmost display. The seventeenth entry is again displayed at the leftmost display position.

• Right Entry Mode : In the right entry mode, the first entry to be displayed is entered on the rightmost display. The next entry is also placed in the right most display but after the previous display is shifted left by one display position.

6. Explain the command words of 8279 Keyboard Display Mode – The format of the command word to select different modes of operation are

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b) Programmable clock: The clock for operation of 8279 is obtained by dividing the external clock input signal by a programmable constant called prescaler.

c) Read FIFO / Sensor RAM: In sensor matrix mode, the bits AAA select one of the 8rows of RAM. If AI flag is set, each successive read will be from the subsequent RAM location.

d) Read Display RAM: This command enables a programmer to read the display RAM data. AI is the auto increment flag for display RAM and AAAA is the address of the character to be read.

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e) Write Display RAM: This command enables a programmer to write the display RAM data. AI is the auto increment flag for display RAM and AAAA is the address of the character to be write.

f) Display Write Inhibit/Blanking :

The IW (inhibit write flag) bits are used to mask the individual A or B nibble. The blank display bit flags (BL) are used for blanking A and B nibbles.

g) Clear Display RAM:

The CD2, CD1, CD0 is a selectable blanking code to clear all the rows of the display RAM CD – Clear display RAM CF – Clear FIFO status CA – Clear All

h) End Interrupt / Error mode Set:

For the sensor matrix mode, this command lowers the IRQ line and enables further writing into the RAM.

For N-Key roll over mode, if the E bit is programmed to be ‘1’, the 8279 operates in special Error mode.

7. Explain the block diagram of 8253 Programmable Interval timer with neat sketch. 8254 can be operated at frequency of up to 8MHz whereas 8253 can be

operated only up to a maximum frequency of 2.6MHz.

Features of IC 8253.

Generation of accurate time delay

Three independent 16-bit down counters called as channels

Six different programmable operating modes

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Timer or counter operation.

Can count in binary or BCD

Can be used to interrupt the processor.

Single +5V supply

Can operate from DC to 2.6MHz.

Block diagram of 8253

The three independent 16-bit timers named as Counter 0, Counter 1 and Counter 2.

These counters are programmed to start counting and stop counting using software

instructions written to the control register.

The count value can also be read using the data bus to the microprocessor.

The three independent 16-bit timers named as Counter 0, Counter 1 and Counter 2.

These counters are programmed to start counting and stop counting using software

instructions written to the control register.

The count value can also be read using the data bus to the microprocessor.

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CS – Active low Chip select control signal is used to select the chip.

A0 and A1 address lines are used to select one of four registers in the 8253 – Three

counters and one control register.

RD and WR - Active low control signals are issued by the processor to indicate whether it

is reading or writing to 8253 registers.

GATE - The control input line is used to start or stop the counting operation.

OUT signal from each counter can be used to indicate the completion of required

counting or timing operation and also to interrupt the processor.

D0 – D7: An 8-bit data bus is available on the 8253 pins to interface the IC with the

microprocessor.

CLK – Clock signal used to count

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Operating Modes of 8253 Mode - 0 : Interrupt on terminal Count

Mode - 1 : Programmable one shot

Mode - 2 : Rate Generator

Mode - 3 : Square wave Generator

Mode - 4 : Software Triggered Strobe

Mode - 5 : Hardware Triggered Strobe

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8. Explain the Operating modes of 8253 timer with necessary diagram

MODE 0: INTERRUPT ON TERMINAL COUNT

After the Control Word is written, OUT is initially low, and will remain low until the

Counter reaches zero.

OUT then goes high and remains high until a new count or a new Mode 0 Control Word

is written into the Counter.

GATE = 1 enables counting; GATE = 0 disables counting.

GATE has no effect on OUT.

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MODE 1: PROGRAMMABLE ONE-SHOT

GATE input is used as trigger input. OUT will be initially high.

OUT will go low on the CLK pulse following a trigger to begin the one-shot pulse and

will remain low until the Counter reaches zero.

OUT will then go high and remain high until the CLK pulse after the next trigger.

A trigger results in loading the Counter and setting OUT low on the next CLK pulse,

thus starting the one-shot pulse


MODE 2: RATE GENERATOR

This Mode functions like a divide-by-N counter.

OUT will initially be high. When the initial count has decremented to 1, OUT goes

low for one CLK pulse.

OUT then goes high again, the Counter reloads the initial count and the process is

repeated.

Mode 2 is periodic; the same sequence is repeated indefinitely. For an initial count

of N, the sequence repeats every N CLK cycles.


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MODE 3: SQUARE WAVE GENERATOR

Mode 3 is similar to Mode 2 except for the duty cycle of OUT.

OUT will initially be high. It remains high for n/2 counts and low for n/2 counts, if n is

even. It remains high for (n+1)/2 counts and low for (n-1)/2 counts, if n is odd

Mode 3 is periodic; the sequence above is repeated indefinitely. An initial count of N

results in a square wave with a period of N CLK cycles.


MODE 4: SOFTWARE TRIGGERED STROBE

OUT will be initially high. When the initial count expires, OUT will go low for one CLK

pulse and then go high again.

The counting sequence is ``triggered‘’ by writing the initial count.



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MODE 5: HARDWARE TRIGGERED STROBE

OUT will initially be high. Counting is triggered by a rising edge of GATE.

When the initial count has expired, OUT will go low for one CLK pulse and then go high

again.

GATE has no effect on OUT

9. Explain 8259 Programmable Interrupt Controller (PIC) interface with diagram

The main features of 8259 are listed below.

8 levels of interrupts.

Can be cascaded in master-slave configuration to handle up to 64 interrupts.

Internal priority resolver- Fixed priority mode and rotating priority mode.

Individually maskable interrupts.

Polled and vectored mode.

Starting address of ISR or vector number is programmable.

No clock required.

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Block Diagram of 8259

Using the Read / Write logic, 8259 is interfaced with the processor.

The data bus lines D0-D7 are connected to the data lines of the processor. 8259 chip will

be selected using the line.

Address line A0 is used to select the control word or the data word. If A0 =0, then the

controller selects writing a command word / reading a status. If A0 =1, then the

controller selects another register for writing the initialization words.

The Control logic has INT and INTA.

The INT output pin is used to interrupt the CPU.

The 8259 receives the interrupt acknowledge INTA pulse from the CPU through its input.

8259 can receive interrupt signals from eight different sources on the lines IR0-IR7.

There are three registers,

An Interrupt Mask Register (IMR)

An Interrupt Request Register (IRR) and

An In-Service Register (ISR).

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When IRO – IR7 lines go high, the requests are stored in the Interrupt Request Register.

The Interrupt Service Register (ISR) stores all the levels that are currently being serviced

The Interrupt Mask Register (IMR) stores the masking bits of the interrupt lines to be

masked.

The Priority Resolver examines the interrupt registers and determines whether the INT

should be sent to the microprocessor or not.

The Cascade buffer or Comparator is used to expand the number of interrupt levels by

cascading two or more 8259s.

8259 can be used in cascaded mode. Up to eight slave 8259s may be cascaded to a

master 8259 to provide up to 64 IRQs.

8259s are cascaded by connecting the INT line of one slave 8259 to the IRQ line of one

master 8259.

Operation of 8259

The following steps show how interrupt handling is done when an external device

places interrupt request on the IR lines of 8259.

One or more of the IR lines may go high. Corresponding IRR bit is set.

8259 evaluates the request based masking and priority and sends interrupt request - INT

to the CPU.

CPU in turn sends INTA to 8259

Highest priority ISR is set and IRR is reset in 8259.

8259 releases CALL instruction on data bus.

CALL causes CPU to initiate two mores. The Processor will send two interrupt

acknowledge pulses on its pin to the pin of 8259.

The pulses tell 8259 to send desired interrupt type to the processor onto the data bus.

8259 releases the subroutine address, first lower byte and then higher byte.

The Interrupt service routine is executed in the processor with the following steps.

o Push the flags into stack.

o Clear Interrupt Flag and Trap Flag of the processor.

o Push the return address on to the stack.

o Load that interrupt vector address in the Program counter / Instruction pointer.

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Execute the Interrupt service routine

ISR bit is reset depending on mode in 8259.

10. Draw the block diagram of a DMA controller (8237) and explain its operation.

DMA is a method of data transfer between Memory and I/O devices without the

intervention of microprocessor. This method is often used when large block of data is to

be transferred.

To start the DMA process, the microprocessor loads an external register in the DMA

controller with the starting address and secondly the Terminal count register with the

total number of bytes to be transferred.

DMA controller has finished transferring data into or out of memory; the DMA

controller gives control back to the microprocessor.

The microprocessor cannot accomplish any other function during that time a DMA

transfer is taking place.

The main features of 8237 are listed below:

Four Independent DMA channels

Enable and disable control of individual requests

Possibility for Memory to memory transfer

Address Increment or decrement

Cascading and expandable to any number of DMA channels

Block Diagram or Architecture of 8237

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The data bus buffer, timing and control block, DMA channels, corresponding priority

block, Read/write control logic and internal registers are the main components.

The data bus consists of 8-bit tristate pins DB0-DB7. These pins are connected to the

system data bus.

A0-A3 pins are used to select one of the internal registers when 8237 is acting in the

slave mode under the control of the processor.

A4-A7 lines along with A0-A3 lines are used to send the higher order 8-bit addresses

when 8237 is acting as master and doing DMA data transfer.

The timing and control block derives internal timing from clock input, and generates

external control signals.

8237 has 4 separate DMA channels and each channel includes two 16-bit registers, a

DMA register and a Count register.

DRQ0-DRQ3 are the four DMA request signals input to 8237 by external peripheral

devices. These four requests can be prioritized.

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The Priority Encoder block resolves priority contention between DMA channels

requesting service simultaneously.

Registers in DMA

Current Address Register

Each channel has a 16-bit Current Address register. This register holds the value of the

address used during DMA transfers. The address is automatically incremented or

decremented by one after each transfer

Current Word Count Register

Each channel has a 16-bit Current Word Count register. This register determines the

number of transfers to be performed.

The word count is decremented after each transfer. When the value in the register goes

from zero to FFFFH, a terminal Count (TC) will be generated.

Base Address and Base Word Count Registers

Each channel has a pair of Base Address and Base Word Count registers. These 16-bit

registers store the original value of their associated current registers.

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Command Register

This 8-bit register controls the operation of the 8237. It is programmed by the

microprocessor and is cleared by RESET or a Master Clear instruction.

Mode Register

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Request Register

Each channel has a request bit associated with it in the 4-bit Request register. Each

register bit is set or reset separately under software control. The entire register is

cleared by a Reset or Master Clear instruction.

Mask Register

Each mask bit is set when its associated channel produces an EOP if the channel is not

programmed to Autoinitialize.

Each bit of the 4-bit Mask register may also be set or cleared separately or

simultaneously under software control.

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Status Register

The Status register contains information about the status of the devices.

This information includes which channels have reached a terminal count and which

channels have pending DMA requests.

Temporary Register

The Temporary register is used to hold data during memory-to-memory transfers. The

Temporary register always contains the last byte transferred in the previous memory to

memory operation, if not cleared by a Reset or Master Clear.

11. Explain the different modes of operation of DMA controller 8237

DMA controller operates in four modes

Single Transfer Mode

Block Transfer Mode

Demand Transfer Mode

Cascade Mode

Single Transfer Mode

In Single Transfer mode, the device is programmed to make one transfer only.

The word count will be decremented and the address decremented or

incremented following each transfer.

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When the word count roll over from zero to FFFFH, a terminal count bit in the

status register is set, an EOP pulse is generated. DREQ must be held active until

DACK becomes active.

Block Transfer Mode

In Block Transfer mode, the device is activated by DREQ or software request

continues making transfers during the service until a TC, caused by word count

going to FFFFH, or an external End of Process (EOP) is encountered. DREQ need

only be held active until DACK becomes active.

Demand Transfer Mode

In Demand Transfer mode the device continues making transfers until a TC or

external EOP is encountered, or until DREQ goes inactive.

The data transfer continues until the I/O device has exhausted its data capacity.

Higher priority channels may intervene in the demand process, once DREQ has

gone inactive. EOP is generated either by TC or by an external signal.

Cascade Mode

This mode is used to cascade more than one 8237 for simple system expansion.

The HRQ and HLDA signals from the additional 8237 are connected to the DREQ

and DACK signals respectively of a channel for the initial 8237.

This allows the DMA requests of the additional device to propagate through the

priority network circuitry of the preceding device.

12. Show how a DMA controller can be connected in an 8086-based system.

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• The block diagram shows how a DMA transfer takes place between Memory and I/O

device with the help of DMA controller. Here the microprocessor and the DMA

controller timeshare the use of address, data and control buses.

• The 8237 Address, Control outputs and data bus pins are connected in parallel with the

system busses. An external latch is required for the upper address byte.

13. Explain the DMA operation process

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The following sequences explain the DMA method of data transfer in detail.

• The starting address of the data is loaded into the 8237 Current and Base Address

registers for a particular channel, and the length of the block is loaded into the channel’s

Word Count Register.

• The corresponding Mode register is programmed for a memory-to-I/O operation (read

transfer), and various options are selected by the Command register and the other

Mode register bits.

• The channel’s mask bit is cleared to enable recognition of a DMA request (DREQ). The

DREQ can either be a hardware signal or a software command.

• When the peripheral device has the first byte of data ready, it sends a DMA request -

DREQ signal to the DMA controller.

• If the input (channel) of the DMA controller is unmasked, the DMA controller will send a

hold-request - HRQ signal to the microprocessor HOLD input.

• The microprocessor will respond to this input by floating its buses and sends a hold-

acknowledge signal, to the DMA controller.

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14. Draw and explain the block diagram of A/D converter?

The basic function of the analog to digital converter is to convert the input analog

voltage levels in to corresponding discrete digital signals.

There are many types of ADC. They are counter ramp type ADC, dual slope ADC,

Flash type ADC and Successive Approximation type ADC.

Successive Approximation type ADC is commonly available ADC. This ADC has fixed

conversion time for any analog input voltage level.

The analog input voltage can be either unipolar or bipolar.

a. Unipolar means (0 to +5V) or (0 to +10V).

b. Bipolar means (-5V to +5V) or (-10V to +10V).

ADCs are available with 8 bits or 10 bits or 12 bits or 16 bits digital outputs.

The resolution can be defined as the range of input voltage divided by the number of

levels at the output.

For example, an ADC with the input voltage range of (0 to+5V) with 8 bits at the

output will have a resolution of (5/256) i.e., approximately 19.5mV.

The ADC chips also have a sample and hold circuit. The sample and hold circuit is

used to maintain the analog input voltage constant when the conversion is in

progress.

Interfacing ADC0816 with 8255

In the interfacing diagram the Port A of 8255 is used to output or send the channel

select lines and the related control signals.

Port B lines are used to get or input the digital result data from the ADC chip.

Port C LSB is used to check the end of conversion signal. With this hardware

arrangement, the ADC chip can only be interfaced with software polling method.

For interrupt driven interface, the EOC signal can be connected to any interrupt input.

Analog inputs can be applied to the analog input pins of ADC 0816.

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• The ADC conversion process can be started after applying the analog input to any of the

channels.

• The conversion process is started by initializing 8255 with the proper control word.

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• Then the Channel selection and Start conversion is done simultaneously as these two

control bits are tied together in the hardware.

• The start conversion must be issued as a pulse for a minimum duration only. Then the

conversion takes place in the ADC chip, if it is properly powered and clock pulses given.

• After the conversion, the logic high ‘End of conversion’ signal is issued by ADC chip. This

is sensed in the software.

• Then the data is read from the data lines after issuing the logic high ‘Output Enable’

signal.

15. With diagram, explain the operation or R-2R method of D/A converter.

Digital to analog converters are used to get a proportional analog voltage or

current for the digital data given out by the microprocessor.

Basically there are two types of DAC.

They are R-2R ladder network and weighted resistor network.

The number of bits and the full scale output voltage both will determine the

resolution. For example, an 8 bit DAC can have 256 input combinations and so

has a resolution of (1/256) or 0.39 percentage of the full scale output.

Linearity is a measure of how straight the output is when the output is changed

from minimum value to the maximum value.

The settling time is defined as the time take for the output to settle within pre-

specified band after the input digital value is applied. Normally, pre-specified

band is [final value±(1/2)*Minimum possible output].

Interfacing DAC 0800 with 8086

• DAC 0800 is a common digital to analog converter chip that can be easily interfaced to

8086 through 8255.

• As the DAC chip can only be connected to an output port of a processor, the 8255 PPI is

essential in the interface. Any one port is enough to interface an 8-bit DAC with 8255.

• The other control signals are directly correspondingly connected to either logic 0 or logic

1. The DAC chip gives a proportional current output.

• This current output in most cases is difficult to measure and so a current to voltage (I to

V) converter is used at the output. DAC chips have an inbuilt latch.

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• This latch stores the digital input given by the port A and gives out a proportional

voltage.

16. Draw the block diagram to interface a keyboard and a 7 segment LED using 8255

programmable peripheral interface

Driver Circuit for single seven segment display

• The BCD to seven segment display decoder IC 7447 converts the four bit BCD code

applied at its input in to the patterns required to display the BCD number.

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• The patterns generated are active low outputs, meaning that logic 0 is given as output

when a particular segment is to be illuminated. So, the common anode display is

suitable for use with 7447.

• We can connect two seven segment displays to single eight bit port. One 7447 IC can be

connected to lower four bits and another 7447 can be connected to the higher order 4

bits of the Port A.

• So with single 8255 which has 3 parallel I/O ports, we can connect 6 seven segment

displays. This results in more complicated circuit.

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17. Explain how to interface the and 7- segment LEDs and Hex Key pad (Keyboard ) using

8279.

• The number of display devices used in the above scheme is six.

• The seven segment displays are all common anode type and a transistor driver is used

with each display device.

• A PNP transistor drive is used to switch between the common anode and +5V.

• A logic low is required to turn on the transistor driver and the same is generated using

the decoder IC. Common decoder ICs like 74138 can be used as this IC gives an active

low output on any of its outputs.

• The segments of the display devices are all connected together on a common bus and

connected to A3-A0 and B3-B0 outputs of 8279. As the displays are all common anodes,

the data output for illuminating a LED must be logic low.

• This means that the logic 1 on all the data lines A3-A0 and B3-B0 will blank the display

and logic 0 in all these lines will display all the segments.

• The software part for the display interface consists of initializing the 8279 for the

encoded output and for eight digit display.

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• Then writing the data for display into the display RAM will make the display in the digits.

8279 will automatically keeps the displays refreshed without the help from the

processor.

Keyboard interface using 8279

• The keyboard matrix that can be interfaced using 8279 can be of any size from 2x2 to

8x8. Pins SL3-SL0 sequentially scans each column through a counting operation.

• The 74LS138 decoder IC can drive 0's on one line at a time from the SL3-SL0 lines.

• The 8279 scans RL pins synchronously with the scan. RL pins incorporate internal pull-

ups, no need for external resistor pull-ups. 8279 does the three jobs of key board scan –

putting a low in a scan line, checking a low on the return lines and detecting the key

pressed and then debouncing.

• Three column select lines SL0-SL2 are used to apply a low on any one column line and do

consecutive scanning on all column lines.

• Any key pressed can be sensed by a low on the return lines. 8279 does this scanning

automatically and stores the key code format into the FIFO RAM.

• In this example, the CNTL and SHIFT lines are not used and are connected to logic low.

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18. Draw and explain the block diagram to interface a keyboard and a 7 segment LED

using 8255 programmable peripheral interface. (or) Draw and explain how a keyboard

and a seven segment LED display is connected with 8086.

8086 interfacing with keyboard

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8086 interfacing with Seven Segment LED display

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19. Explain the physical memory organization of 8086.

20. Draw and explain the block diagram of traffic light control system.

21. Draw and explain the block diagram of Alarm control system.

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