I SEMESTER VLSI Design and Embedded System Lab -1

I SEMESTER VLSI Design and Embedded System Lab -1

EXPERIMENT 1Verilog code for the design of 8-bit Carry Ripple Adder, download the program on FPGA board and perform testing using Pattern generator/Chip scope pro.

8-bit Carry Ripple AdderVerilog Code (Top Module)module ripple_carry (a, b, cin, sum, cout);input [07:0] a;input [07:0] b;input cin;output [7:0] sum;output cout;wire [6:0] c;fulladd a1(a[0],b[0],cin,sum[0],c[0]);fulladd a2(a[1],b[1],c[0],sum[1],c[1]);fulladd a3(a[2],b[2],c[1],sum[2],c[2]);fulladd a4(a[3],b[3],c[2],sum[3],c[3]);fulladd a5(a[4],b[4],c[3],sum[4],c[4]);fulladd a6(a[5],b[5],c[4],sum[5],c[5]);fulladd a7(a[6],b[6],c[5],sum[6],c[6]);fulladd a8(a[7],b[7],c[6],sum[7],cout);endmoduleVerilog Code (Full Adder)module fulladd (a, b, cin, sum, cout);input a;input b;input cin;output sum;output cout;assign sum = (a^b^cin);assign cout = ((a&b)|(b&cin)|(a&cin));endmoduleTop Filemodule TOP (input clk);

wire [35:0] CONTROL0;wire [35:0] CONTROL1;

wire [8:0] TRIG0;

wire [8:0] SYNC_IN;wire [16:0] SYNC_OUT;

wire [7:0] a;wire [7:0] b;wire cin;

wire [7:0] sum;wire cout;

assign a= SYNC_OUT [7:0];assign b= SYNC_OUT [15:8];assign cin= SYNC_OUT [16];

assign SYNC_IN [8:0] = {cout, sum};assign TRIG0 [8:0] = {cout, sum};

ICON L1 ( .CONTROL0 (CONTROL0), // INOUT BUS [35:0] .CONTROL1 (CONTROL1) // INOUT BUS [35:0]);

ILA L2 ( .CONTROL (CONTROL0), // INOUT BUS [35:0] .CLK (clk), // IN .TRIG0 (TRIG0) // IN BUS [8:0]);

VIO L3 ( .CONTROL (CONTROL1), // INOUT BUS [35:0] .CLK (clk), // IN .SYNC_IN (SYNC_IN), // IN BUS [8:0] .SYNC_OUT (SYNC_OUT) // OUT BUS [16:0]);

ripple_carry L4 ( .a(a), .b(b), .cin(cin), .sum(sum), .cout(cout) );endmoduleOutput

EXPERIMENT 2Verilog code for the design of 8-bit Carry Look ahead Adder, download the program on FPGA board and perform testing using Pattern generator/Chip scope pro.

8-bit Carry Look ahead AdderVerilog Code (Top Module)module carry_lookahead (A, B, Cin, Sum, Cout);output [7:0] Sum;output Cout;input [7:0] A, B;input Cin;wire [7:0] G, P, C;assign G = A & B; //Generateassign P = A ^ B; //Propagateassign C[0] = Cin;assign C[1] = G[0] | (P[0] & C[0]);assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0]);assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C[0]);assign C[4] = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) | (P[3] & P[2] & P[1] & P[0] & C[0]);assign C[5] = G[4] | (P[4] & G[3]) | (P[3] & P[4] & G[2]) | (P[3] & P[2] & P[4] & G[1]) | (P[3] & P[2] & P[1] & P[4] & G[0]) | (P[4] & P[3] & P[2] & P[1] & P[0] & C[0]);assign C[6] = G[5] | (P[5] & G[4]) | (P[4] & P[5] & G[3]) | (P[5] & P[3] & P[2] & P[4] & G[1]) | (P[3] &P[2] & P[1] & P[4] & P[5] & G[0]) | (P[5] & P[4] & P[3] & P[2] & P[1] & P[0] & C[0]);assign C[7] = G[6] | (P[6] & G[5]) | (P[6] & P[5] & G[4]) | (P[4] & P[5] & P[6] & G[3]) | (P[3] & P[4] & P[6] & G[5]) | (P[6] & P[5] & P[4] & P[3] & P[2] & G[1]) | ( P[6] & P[5] & P[4] & P[3] & P[2] & P[1] & G[0]) | ( P[6] & P[5] & P[4] & P[3] & P[2] & P[1] & P[0] & C[0]);assign Cout = G[7] | (P[7] & G[6]) | (P[6] & P[7] & G[5]) | (P[7] & P[5] & P[6] & G[4]) |(P[4] & P[5] & P[6] & P[7] & G[3]) | (P[7] & P[6] & P[4] & P[3] & G[5]) | ( P[7] & P[6] & P[5] & P[4] & P[3] & P[2] & G[1]) | ( P[7] & P[6] & P[5] & P[4] & P[3] & P[2] & P[1] & G[0]) | (P[7] & P[6] & P[5] & P[4] & P[3] & P[2] & P[1] & P[0] & G[0]);assign Sum = P ^ C;endmoduleTop Filemodule TOP(input clk);

wire [35:0] CONTROL0;wire [35:0] CONTROL1;

wire [8:0] TRIG0;

wire [16:0] SYNC_OUT;wire [8:0] SYNC_IN;

wire [7:0] A;wire [7:0] B;wire Cin;wire [7:0] Sum;wire Cout;

assign A=SYNC_OUT[7:0];assign B=SYNC_OUT[15:8];assign Cin=SYNC_OUT[16];assign SYNC_IN[8:0]={Cout,Sum};assign SYNC_IN[8:0]={Cout,Sum};

ICON L1 ( .CONTROL0(CONTROL0), // INOUT BUS [35:0] .CONTROL1(CONTROL1) // INOUT BUS [35:0]);

ILA L2( .CONTROL(CONTROL0), // INOUT BUS [35:0] .CLK(clk), // IN .TRIG0(TRIG0) // IN BUS [8:0]);

VIO L3( .CONTROL(CONTROL1), // INOUT BUS [35:0] .CLK(clk), // IN .SYNC_IN(SYNC_IN), // IN BUS [8:0] .SYNC_OUT(SYNC_OUT) // OUT BUS [15:0]);carry_lookahead L4 ( .A(A), .B(B), .Cin(Cin), .Sum(Sum), .Cout(Cout) );endmoduleOutput

EXPERIMENT 3Verilog code for the design of 8-bit Booth Multiplication (Radix-4), download the program on FPGA board and perform testing using Pattern generator/Chip scope pro.

Verilog Code (Top Module)module Booth_mul (p, a, b, clk);input clk;input [7:0] a, b;output [15:0] p;reg [15:0] p, ans;integer i;integer operate;initial beginp= 16'b0; // initilaising the product to zeroans= 16'b0;endalways @ (posedge clk)beginp= 16'b0;for (i=1; i