MAHAMAYA TECHNICAL UNIVERSITY NOIDA

M.TECH. FIRST YEAR

Syllabus

FOR 1. Advance Electronics and Communication Engineering 2. VLSI 3. VLSI Design 4. VLSI System Design 5. VLSI and Embedded System

[Effective from the Session: 2012-13]

STUDY AND EVALUATION SCHEME

Advance Electronics and Communication Engineering/VLSI/VLSI Design/VLSI System Design/VLSI and Embedded System.

Semester - I

S No

Sub Code

Subject Name L T P

Evaluation Scheme Total

Cred

its

Sessional ESE

CT AT TA TOT P TH P

1 VL-910 CMOS VLSI Design 3 0 3 30 10 10 50 20 100 30 200 4

2 VL-911 Modeling of Digital System Design

3 0 3 30 10 10 50 20 100 30 200 4

3 VL-912 Embedded System Design

3 0 3

30 10 10 50 20 100 30 200 4

4 VL-913 Analog VLSI Design 3 1 0

40 15 15 70 - 130 - 200 4

5 VL-91? Elective-I 3 0 0 30 10 10 50 - 100 - 150 3

6 VL-919 Field Work/Industrial visit

- - - - - - - 50 - - 50 1

Total 15 1 9 270 110 530 90 1000 20

CT: Class Test AT: Attendance TA: Teacher’s Assessment TOT: Total P: Practical TH: Theory L: Lecture T: Tutorial NOTE:

1. Wherever the question is of 130 marks, 15 short answer questions of 2 marks each

shall be asked in the question paper.

2. A student shall be offered any one of the elective subjects given at the end depending

upon the availability of the faculty member in the College / Institute.

3. An elective subject offered once in a semester shall not be repeated during the entire

M. Tech. programme.

4. Minimum number of students required to run an elective subject is 8.

MAHAMAYA TECHNICAL UNIVERSITY, NOIDA STUDY AND EVALUATION SCHEME (effective from 2012-13)

M. TECH (Advance Electronics and Communication Engineering Specialization in VLSI Design)/M TECH (VLSI Design)

Semester II

S No

Sub Code

Subject Name L T P

Evaluation Scheme Total

Cred

its

Sessional ESE

CT AT TA TOT P TH P

1 VL-920 VLSI Design Automation 3 0 3 30 10 10 50 20 100 30 200 4

2 VL-921 Low Power VLSI Design 3 0 3 30 10 10 50 20 100 30 200 4

3 VL-922 SOC Design 3 1 0 40 15 15 70 - 130 - 200 4

4 VL-92? Elective-II 3 1 0

40 15 15 70 - 130 - 200 4

5 AS-920 Research Methodology 2 0 0 30 10 10 50 - 50 - 100 2

6 VL-927 Seminar 0 0 3 - - - - 50 - - 50 1

7 VL-928 Field Work/Industrial visit/ Minor Project

50 50 1

Total 14 2 9 1000 20

CT: Class Test AT: Attendance TA: Teacher’s Assessment TOT: Total P: Practical TH: Theory L: Lecture T: Tutorial NOTE: 1. Wherever the question is of 130 marks, 15 short answer questions of 2 marks each shall be asked in the question paper. 2. A student shall be offered any one of the elective subjects given at the end depending upon the availability of the faculty member in the College / Institute. 3. An elective subject offered once in a semester shall not be repeated during the entire M. Tech. programme. 4. Minimum number of students required to run an elective subject is 8.

ELECTIVE-I

1. VL-914: Solid State Devices 2. VL-915: Real Time Operating Systems. 3. VL-916: Data Structures Using C 4. VL-917: Advanced Computer Architecture 5. VL-918: VLSI Technology

Elective-II

1. VL-923: ASIC Design 2. VL-924: Advanced Microcontrollers & Applications 3. VL-925: Embedded Networking with CAN and CANopen 4. VL-926: Synthesis & Optimization of Digital Circuits

VL-910: CMOS VLSI DESIGN 3 0 3

Unit Topic Text

Book Lectures

I Introduction: Historical Perspective, Overview of VLSI Design Methodologies, VLSI Design Flow, Design Hierarchy, Concepts of Regularity, Modularity and Locality. Fabrication of MOSFETs – Introduction, Fabrication Process Flow: Basic Steps, The CMOS n-well process. MOS Transistor : MOS Structure, The MOS System under external bias, Operation of MOSFET, MOSFET - Current /Voltage Characteristics, Scaling and Small geometry effects and capacitances.

1 8

II

MOS Inverters: Introduction, Resistive Load Inverter, Inverters with n-type MOSFET load, CMOS Inverter. MOS Inverters - Switching Characteristics: Introduction, Delay – Time Definitions, Calculation of Delay Times, and Inverter Design with Delay Constraints.

1 8

III

Combinational MOS Logic Circuits – Introduction, MOS circuits with Depletion nMOS loads, CMOS logic circuits, Complex Logic circuits, CMOS Transmission Gates. Sequential MOS Logic Circuits – Introduction, Behaviour of Bi-stable Elements, SR Latch Circuit, Clocked Latch and Flip-Flop Circuits. CMOS D-latch & Edge Triggered Flip-Flop.

1 8

IV Dynamic Logic Circuits – Basic Principles of Pass Transistor Circuits, Voltage Boot Strapping, Synchronous Dynamic Circuit Techniques,, Dynamic CMOS Circuit Techniques, High Performance Dynamic CMOS Circuits. Semiconductor Memories – DRAM, SRAM, Non-volatile Memory, Flash Memory

1 8

V

Circuit Characterization and Performance Estimation : Introduction, Delay Estimation, Logical Effort and Transistor Sizing, Power Dissipation, Interconnect, Design margin and Reliability

2

8

Text books: 1. Sung-Mo Kang & Yosuf Leblebici - “CMOS Digital Integrated Circuits: Analysis & Design”- TATA

McGraw Hill – 3rd Edition. 2. Neil H.E. Weste, David Harris & Ayan Banerjee – “CMOS VLSI Design – A Circuits and Systems

Perspective” – Pearson Education – 3rd Edition. Reference books:

1. W.Wolf, Modern VLSI Design: System on Chip, Third Edition, PH/Pearson , 2002. 2. J.M.Rabaey, A.P.Chandrakeshan and B.Nikolic, Digital Integrated Circuits: A Design Perspective,

Second Edition, P.H.Pearson,2003. 3. D.A.Puckneli and K.Eshraghian, Basic VLSI Design: Systems and Circuits, Third Edition, PHI,1994. 4. J.P.Uyemura, CMOS Logic Circuit Design, Kluwer,1999. 5. J.P.Uyemura, Introduction to VLSI Circuits and Systems,Wiley,2002. 6. R.J.Baker, H.W.Li and D.E.Boyce, CMOS Circuit Design, Layout and Simulation, PH, 1997. 7. http://www.cmosvlsi.com 8. http://www.slideserve.com/gwen/introduction-to-cmos-vlsi-design-lecture-3-cmos-transistor-

theory 9. http://www.ee.mut.ac.th/home/theerayod/lecture_files/EEET0413/

VL-910P: CMOS VLSI DESIGN LAB 0 0 3

SOFTWARE TOOL: CADENCE – Tool Bundle Consisting of: ANALOG & MIXED SIGNAL DESIGN FRONT END TOOLS

Virtuoso(R) Spectre(R) Simulator REL MMSIM 7.1 Virtuoso(R) Schematic Editor XL REL IC 6.1.0

ANALOG BACK END TOOL

Virtuoso(R) Layout Suite XL REL IC 6.1.0

DIGITAL DESIGN FRONT END SIMULATION AND VERIFICATION Incisive Enterprise Simulator - XL REL IES 8.2

SYNTHESIS Encounter RTL Compiler - XL REL RC 9.1

PHYSICAL DOMAIN SOC Encounter - XL (aka Cadence (R) SOC Encounter - GPS)

1. Design an Inverter completing the design flow mentioned below:

(a) Draw the schematic and verify the following – (i) DC Analysis (ii) Transient Analysis

(b) Draw the Layout and verify the DRC, ERC (c) Check for LVS (d) Extract RC and back annotate the same and verify the design (e) Verify & optimize for time, power and area to the given constraint.

2. Design the following circuits with given specifications, completing the design flow mentioned below:

(a) Draw the schematic and verify the following – (i) DC Analysis (ii) AC Analysis

(iii) Transient Analysis (b) Draw the Layout and verify the DRC, ERC (c) Check for LVS (d) Extract RC and back annotate the same and verify the design

• Latch • D Flip - Flop • Transmission Gate

3. Design a simple NAND/NOR gate completing the design flow mentioned below:

(a) Draw the schematic and verify the following –

(i) DC Analysis (ii) Transient Analysis (b) Draw the Layout and verify the DRC, ERC (c) Check for LVS (d) Extract RC and back annotate the same and verify the design (e) Verify & optimize for time, power and area to the given constraint.

VL-911: MODELING OF DIGITAL SYSTEM DESIGN 3 0 3

Unit Topic Text

Book Lectures

I VHDL Methodology: Requirements Analysis & Specification, VHDL Design Description, Verification Using Simulation, Test Benches, Functional Simulation. Entities, Architectures, and Coding Styles: Design Units, Library Units, and Design Entities, Entity Declaration, VHDL Syntax Definitions, Port Modes, Architecture Body, Coding Styles, Synthesis Results Vs. Coding Style, Levels of Abstraction & Synthesis, Design Hierarchy and Structural Style.

T1 8

II

Signals and Data Types: Object Classes and Object Types, Signal Objects, Scalar Types, Type Std_Logic, Scalar Literals and Scalar Constants, Composite Types, Arrays, Types Unsigned and Signed, Composite Literals and Composite Constants, Integer Types, Port Types for Synthesis, Operators and Expressions. Dataflow Style Combinational Design – Signal Assignments in Data-Flow Style Architectures , Selected Signal Assignment, Conditional Signal Assignment.

T1 8

III

Behavioral Style Combinational Design – Behavioral Style Architecture, Process Statement, Sequential Statements, Case Statement, IF Statement, Loop Statement, Variables. Event –Driven Simulation – Simulator Approaches, Elaboration, Signal Drivers, Simulator Kernel Process, Simulation Initialization, Simulation Cycles, Signals Vs. Variables, Delta Delays, Delta Delays and Combinational Feedback, Multiple Drivers, Signal Attributes.

T1 8

IV Digital Blocks : A BCD Adder, 32 –Bit Adders, Add – and Shift Multiplier, Array Multiplier, A Signed Integer /Fraction Multiplier, Binary Dividers SM CHARTS and Microprogramming: State Machine Charts, Derivation of SM Charts, Realization of SM Charts, Implementation of Dice Game, Micro-programming, and Linked State Machines.

T2 8

V

Finite State Machines – FSM State Diagrams, Three Process FSM VHDL Template, State Diagram Development, Decoder for Optical Shaft Encoder, State Encoding and State Assignment, Supposedly Safe FSMs, Inhibit Logic FSM Example, Counters as Moore FSMs.

T1 8

TEXT BOOKS: 1. Kenneth L Short, “VHDL for Engineers” Pearson LPE. 2. Roth – John, “Principles of Digital System Design using VHDL”, Cengage Learning. India Edition. REFERENCE BOOKS: 1. J.F. Wakerly, “Digital Design-Principles and Practices”, PHL 2. Douglas Perry, “VHDL”, MGH 3. Michae John Sebastian Smith, “Application-Specific Integrated Circuits”, Addison-Wesley. 4. Z. Navabi, “ VHDL-Analysis and Modeling of Digital Systems”, MGH 5. http://users.ece.utexas.edu/~roth/book/book.htm 6.http://www.cse.sc.edu/~jimdavis/Courses/2004Fall%20CSCE%20612/F04_csce_612_lectures.htm 7. http://web.cecs.pdx.edu/~mperkows/CLASS_VHDL_99/slides.html

VL-911P: MODELING OF DIGITAL SYSTEM DESIGN LAB 0 0 3 Write VHDL code for the following circuits and their Test Bench for verification. Observe the waveform and synthesize the code with technological library with given constraints. Do the initial timing verification with gate level simulation. SOFTWARE TOOLS: MENTOR GRAPHICS DESIGN, VERIFICATION & TEST PACKAGE - HEP 2:

• HDL Designer – A graphical HDL design environment that enables scalable RTL design, spanning FPGAs to multimillion gate ASICs. HDL Designer creates & manages complex Verilog, VHDL, & mixed-language ASIC & FPGA designs.

• ModelSim SE™ – The industry’s most widely used verification environment. ModelSim’s single kernel architecture supports all the industry’s standard languages including VHDL, Verilog & SystemC.

• Precision Synthesis – Delivers outstanding quality of results for FPGA synthesis from VHDL & Verilog 2001.

• Precision Physical Synthesis – An integrated RTL & physical FPGA synthesis solution, built on a single data model, simultaneously optimizes gate & interconnect delay.

• Seamless FPGA – Verification of hardware & software in an embedded system, Seamless FPGA provides a single button, automated set up for FPGA verification.

• LeonardoSpectrum™ ASIC – A push-button easy-to-use for solution for synthesizing ASICs, in VHDL or Verilog.

• Design for Test - Mentor Graphics’ Design-for-Test products provide a complete solution for achieving high test quality, low test cost for the whole chip.

• FormalPro™ – A high-capacity equivalence checking solution for gate-level regression testing of designs from small to multi-million gate designs.

• Seamless– Verification of hardware & software in an embedded system. XILINX FPGA DEVELOPMENT BOARDS:

• XA Spartan FPGA Family / Virtex FPGA Family List of Experiments:

1. An Inverter 2. A Buffer 3. Transmission Gate 4. Basic/Universal gates 5. Flip flop – SR, D, JK, T 6. Serial & Parallel adder 7. 4-bit counter (Synchronous and Asynchronous counter) 8. Successive approximation register (SAR)

VL-912/EC-917: EMBEDDED SYSTEM DESIGN 3 0 3

Unit Topic Text

Book Lectures

I Typical Embedded System : Core of the Embedded System, Memory, Sensors and Actuators, Communication Interface, Embedded Firmware, Other System Components Characteristics and Quality Attributes of Embedded Systems Hardware Software Co-Design and Program Modelling: Fundamental Issues in Hardware Software Co-Design, Computational Models in Embedded Design, Introduction to Unified Modelling Language, Hardware Software Trade-offs.

8

II

Designing Embedded System with 8 bit Microcontrollers – Factors to be Considered in Selecting a Controller, Why 8051 Microcontroller, Designing with 8051, The 8052 Microcontroller, 8051/52 Variants.

8

III

Embedded Firmware Design and Development: Embedded Firmware Design Approaches, Embedded Firmware Development Languages, Real-Time Operating System (RTOS) based Embedded System Design. Operating System Basics, Types of OS, Tasks, Process and Threads, Multiprocessing and Multitasking, Task Scheduling, Threads, Processes and Scheduling: Putting them altogether, Task Communication, Task Synchronization, Device Drivers, How to Choose an RTOS

8

IV The Embedded System Development Environment: The Integrated Development Environment (IDE), Types of Files Generated on Cross-compilation, Disassembler/Decompiler, Simulators, Emulators and Debugging, Target Hardware Debugging, Boundary Scan.

8

V

The Embedded Product Development Life Cycle (EDLC): Introduction, Objectives of EDLC, Different Phases of EDLC, EDLC Approaches. Trends in the Embedded Industry: Processor Trends in Embedded System Embedded OS Trends, Development Language Trends, Open Standards, Frameworks and Alliances, Bottlenecks.

8

Text books/ Reference books: 1. Shibu K V, “Introduction to Embedded Systems”, Tata McGraw Hill Education Private Limited, 2009 2. James K Peckol “Embedded Systems – A contemporary Design Tool”, , John Weily, 2008.

3. David E. Simon, “An Embedded Software Primer” by Pearson Education 4. John Catsoulis, O’reilly “Designing Embedded Hardware” 5. Frank Vahid, Tony Givargis, “Embedded System Design” , John Wiley & Sons, 6. Alan C. Shaw, “Real-time systems & software” John Wiley & sons, Inc. 7. http://www.tik.ee.ethz.ch/education/lectures/ES/

8. http://www.ida.liu.se/~TDDI08/LectureNotes/ 9. http://patricklam.ca/teaching/ 10. http://www.learnerstv.com/Free-Engineering-Video-lectures-ltv118-Page1.htm 11. http://microcontroller.com/ 12. http://esd.cs.ucr.edu/

VL-912P: EMBEDDED SYSTEM DESIGN LAB 0 0 3

HARDWARE / SOFTWARE Requirements: • 8051 trainer kits • 8051 IDE (KEIL)

1. a. Write a program to generate and store Fibonacci terms which are less than FF h.

b. To write a program to find the average of a set of hex data. c. To examine the 8051 division and multiplication instructions.

2. a. BCD to HEX conversion b. HEX to ASCII conversion

3. a. To test the 8051 system and its ports. b. Write a program to transfer a letter ‘Y’ serially at 9600 baud continuously and also to send letter ‘N’ through port 0, which is connected to a display device.

4. Write a program to check if the character string of length 7 stored in RAM location 50H onwards is a palindrome. If it is then output ‘Y’ on P1.

5. Write a program to toggle all the bits of port P1 every 200ms.Given crystal

frequency=11.0593MHz

6. Create a square wave of 66% duty cycle on bit 3 of P1.

7. Interface LCD to 8051 and write program for sending information to LCD with MOVC instruction.

8. Interface ADC 0808/0809 chip with 8 analog channels to 8051 microcontroller and program it.

9. Write a program to generate saw tooth waveform with DAC interfaced to 8051 microcontroller.

10. Design a system to accept a data from an analog device and display the digital data on LED port using 8255 in mode 0.

VL-913: ANALOG VLSI DESIGN 3 1 0

Unit Topic Text

Book Lectures

I Introduction to analog design - Levels of abstraction, Robust analog design, MOS Device Models, MOS Device Capacitances, MOS small signal model, long channel vs. short channel, Single stage amplifier- Basic concepts, Common Source Stage, Source follower, Common Gate stage, Cascode Stage

8

II

Differential amplifiers - Single ended and Differentials Operation, Common Mode Response Differential pair with MOS loads, Gilbert Cell. Passive and Active Current Mirrors – Basic current mirrors, Cascode Current Mirrors, Active Current Mirrors

8

III

Frequency Response of Amplifiers – General Considerations, CS stage, Source Followers, CG stage, Cascode stage, Differential Pair. Feed Back – General Considerations, Feedback Topologies, Effect of Loading.

8

IV Operational Amplifiers – General Considertions, One stage and two stage Op Amps, Gain boosting, Comparison, Common-mode Feedback, Input Range limitations, Slew Rate, Power Supply Rejection, Stability and Frequency compensations – General Considerations, Multipole System, Phase Marging, Frequency Compensation, Compensation of Two Stage Op-Amp.

8

V

Voltage controlled oscillator, Phase Locked Loops (PLL) – Simple PLL, Charge Pump PLLs, Introduction to Switched - Capacitor Circuits – General Considerations, Sampling Switches, Switched Capacitor Amplifiers, Switched Capacitor Integrator, Switched Capacitor Common Mode Feedback.

8

TEXT BOOKS:

1. Design of Analog CMOS integrated circuits Behzad Razavi McGraw-Hill International edition - ISBN-0-07-118815-0.

2. “Analysis and Design of Analog Integrated Circuits”. Paul B Gray and Robert G Meyer,

REFERENCE BOOKS:

1. D. A. Johns and Martin, Analog Integrated Circuit Design, John Wiley, 1997. 2. R Gregorian and G C Temes, Analog MOS Integrated Circuits for Signal Processing, John Wiley,

1986. 3. R L Geiger, P E Allen and N R Strader, VLSI Design Techniques for Analog & Digital Circuits,

McGraw Hill, 1990. 4. Gray and Meyer,” Analysis and Design of Analog IC ”, Wiley international,1996. 5. Gray, Wooley, Brodersen, “Analog MOS Integrated circuits”, IEEE press, 1989. 6. Kenneth R. Laker, Willy M.C. Sensen, “ Design of Analog Integrated circuits and systems”, McGraw

Hill, 1994. 7. www.erc.msstate.edu/mpl/education/classes/ee8223/index.html 8. http://ecee.colorado.edu/~ecen4827/lectures.html 9. www.eit.lth.se/course/eti063 10. www.ee.iitm.ac.in/~ani/ee5390/lectures.html

ELECTIVE-I VL-914: SOLID STATE DEVICES 3 0 0

Unit Topic Text

Book Lectures

I Semi-conductor materials- Crystal lattices, bulk crystal growth, epitaxial growth, Physical models-bohr model, quantum mechanics, atomic structure, energy bands & charge carriers in semi-conductors, carrier concentration, drift of carriers in electric and magnetic fields, diffusion of carriers

8

II

Fabrication of P-N junctions, equilibrium conditions, forward and reverse biased junctions, steady state conditions, reverse bias breakdown, transient and a.c. condition, deviation from simple theory, metal semi-conductor junction, hetero-junction

8

III

P-N junction diodes, tunnel diode, photo diode, light emitting diodes and lasers. BJTs: amplification & switching: Fundamental of BJT operation, BJT fabrication, minority carrier distribution & terminal currents, generalized biasing, switching, frequency limitation of transistors, hetero-junction bipolar transistor, FETs: junction FET-metal semi-conductor FET-Metal insulator semiconductor FET

8

IV Integrated circuits: fabrication of monolithic circuits, monolithic device elements, charge transfers devices, very large scale integration, testing, bonding and packaging

8

V

Lasers: stimulated emission: ruby lasers, semi-conductor lasers, other lasers, p-n-p-n switching devices, switching mechanism: semiconductor controller rectifier, negative conductance, Microwave devices: Transit time devices: Gunn effect and related devices.

8

Text books: 1. Ben G Steetman, “Solid State Electronic Devices” PHI Reference books: 1. S M Sze, “Physics of semiconductor Devices”, Willey Pub. 2. Kittel C, “Introduction to Solid State Physics”, Willey Pub. 3. http://my.ece.ucsb.edu/mishra/ece132.htm 4. http://www.utdallas.edu/~goeckner/devices_class/EE3310_fl02_3_marked.pdf 5. http://www.utdallas.edu/~goeckner/devices_class/EE3310_classnotes_fl02_1.pdf 6. http://hanyangocw.hanyang.ac.kr/ocw/fusion-materials/solid-state-electronic-devices-2/Course_listing 7. http://hanyangocw.hanyang.ac.kr/ocw/fusion-materials/solid-state-electronic-devices-1/lecture-notes-readings/skinless_view 8. https://nanohub.org/resources/5221

VL=915: REAL TIME OPERATING SYSTEMS 3 0 0

Unit Topic Text

Book Lectures

I Introduction to Real-Time Embedded Systems: Brief history of Real Time Systems, A brief history of Embedded Systems. System Resources: Resource Analysis, Real-Time Service Utility, Scheduling Classes, The Cyclic Executive, Scheduler Concepts, Pre-emptive Fixed Priority Scheduling Policies, Real-Time OS, Thread Safe Re-entrant Functions..

8

II

Processing: Pre-emptive Fixed-Priority Policy, Feasibility, Rate Montonic least upper bound, Necessary and Sufficient feasibility, Deadline – Monotonic Policy, Dynamic priority policies. I/O Resources: Worst-case Execution time, Intermediate I/O, Execution efficiency, I/O Architecture. Memory: Physical hierarchy, Capacity and allocation, Shared Memory, ECC Memory, Flash file systems.

8

III

Multiresource Services: Blocking, Deadlock and livestock, Critical sections to protect shared resources, priority inversion. Soft Real-Time Services: Missed Deadlines, QoS, Alternatives to rate monotonic policy, Mixed hard and soft real-time services. Embedded System Components: Firmware components, RTOS system software mechanisms, Software application components.

8

IV Debugging Components: Execptions assert, Checking return codes, Single-step debugging, kernel scheduler traces, Test access ports, Trace ports, Power-On self test and diagnostics, External test equipment, Application-level debugging. Performance Tuning: Basic concepts of drill-down tuning, hardware – supported profiling and tracing, Building performance monitoring into software, Path length, Efficiency, and Call frequency, Fundamental optimizations.

8

V

High availability and Reliability Design: Reliability and Availability, Similarities and differences, Reliability, Reliable software, Available software, Design tradeoffs, Hierarchical applications for Fail-safe design

8

Text books:

1. “Real-Time Embedded Systems and Components”, Sam Siewert, Cengage Learning India Edition, 2007.

2. “ Programming and Customizing the PIC microcontroller” , Myke Predko, 3rd Ed, TMH, 2008 3. http://home.iitj.ac.in/~sk/RTOS.html 4. www.learnerstv.com/Free-Computers-Video-lectures-ltv468-Page1.htm 5. www.isi.edu/~faber/cs402/notes/ 6. http://abstract.cs.washington.edu/~shwetak/classes/ee472/notes/472_note_pack.pdf

VL-916: DATA STRUCTURES USING C 3 0 0

Unit Topic Text

Book Lectures

I Introduction: Time and Space analysis of Algorithms - Order Notations. Linear Data Structures - Sequential representations - Arrays and Lists, Stacks, Queues and De-queues, strings, Application.

8

II

Linear Data Structures, Link Representation - Linear linked lists, circularly linked lists. Doubly linked lists, Application. Recursion -- Design of recursive algorithms, Tail Recursion, When not to use recursion, Removal of recursion.

8

III

Non-linear Data Structure: Trees - Binary Trees, Traversals and Threads, Binary Search Trees, Insertion and Deletion algorithms, Height-balanced and weight-balanced trees, B-trees, B+ -trees, Application of trees;

8

IV Graphs - Representations, Breadth-first and Depth-first Search. Sorting & Searching : Sorting and Searching Algorithms- Bubble sort, Selection Sort, Insertion Sort, Quick Sort, Merge Sort, Heap sort and Radix Sort; Linear Search and Binary Search. Hashing - Hashing Functions, collision Resolution Techniques.

8

V

Files : File Structures - Sequential and Direct Access. Relative Files, Indexed Files - B+ tree as index. Multi-indexed Files, Inverted Files, Hashed Files.

8

Text books:

1. Tanenbaum, A. S., “Data Structures using ‘C’”, PHI References:

1. Weiss Mark Allen, “Algorithms, Data Structures, and Problem Solving with C++”, Addison Wesley, Pearson.

2. Horowitz Ellis & Sartaj Sahni, “Fundamentals of Data Structures”, Galgotia Pub. 3. Aho Alfred V., Hopperoft John E., UIlman Jeffrey D., “Data Structures and Algorithms”, Addison

Wesley 4. Drozdek- Data Structures and Algorithms, Vikas 5. http://archives.evergreen.edu/webpages/curricular/2001-2002/dsa01/dsa-resources.html 6. http://ourcecodemania.com/advanced-data-structures-tutorial-using-cpp/ 7. https://sites.google.com/site/atulkg/courses/es-103-data-structure-and-algorithms-2012

VL-917: ADVANCED COMPUTER ARCHITECTURE 3 0 0

Unit Topic Text

Book Lectures

I Parallel Computer Models: The state of Computing, Multiprocessors and Multi-computers, Multi-vector and SIMD Computers. PRAM and VLSI Models, Architectural Development Tracks. Program and Network Properties: Conditions of Parallelism, Program Partitioning and Scheduling, Program flow Mechanisms, System Interconnect Architectures.

8

II

Principles of Scalable Performance – Performance Metrics and Measures, Parallel Processing Applications, Speedup Performance Laws, Scalability Analysis and Approaches. Advanced processors: Advanced Processor Technology, Superscalar and Vector Processors.

8

III

Memory Hierarchy: Memory Hierarchy Technology, Virtual Memory Technology. Bus, Cache, and Shared Memory: Backplane Bus Systems, Cache Memory Organization, Shared Memory Organizations, Sequential and Weak Consistency Models.

8

IV Pipelining and Superscalar Techniques: Linear Pipeline Processors, Nonlinear Pipeline Processors, Instruction Pipeline Design, Arithmetic Pipeline Design, Superscalar and Super pipeline Design. Multiprocessors and Multi-computers : Multiprocessor System Interconnects, Cache Coherence and Synchronization Mechanisms, Three Generations of Multi-computers, Messaging-Passing Mechanisms

8

V

Multi-vector and SIMD Computers: Vector Processing Principles, Multi-vector Multi-processors, Compound Vector Processing, SIMD Computer Organizations, The Connection Machine CM-5. Scalable, Multithreaded, and Dataflow Architectures: Latency – Hiding Techniques, Principles of Multithreading, Fine – Grain Multi-computers, Scalable and Multithreaded Architectures, Data Flow and Hybrid Architectures.

8

Text books: 1. Kai Hwang, “Advanced computer architecture”; TMH. 2. D. A. Patterson and J. L. Hennessey, “Computer organization and design,” Morgan Kaufmann, 2nd Ed. Reference books:

1. J. P. Hayes, “Computer Architecture and organization”; MGH. 2. Harvey G. Cragon,”Memory System and Pipelined processors”; Narosa Publication. 3. V.Rajaranam & C.S.R.Murthy, “Parallel computer”; PHI. 4. R. K. Ghose, Rajan Moona & Phalguni Gupta, “Foundation of Parallel Processing”; Narosa Publications. 5. Kai Hwang and Zu, “Scalable Parallel Computers Architecture”; MGH. 6. Stalling W, “Computer Organisation & Architecture”;PHI. 7. D. Sima, T. Fountain, P. Kasuk, “Advanced Computer Architecture-A Design space Approach,” Addison Wesley, 1997. 8. M.J Flynn, “Computer Architecture, Pipelined and Parallel Processor Design”; Narosa Publishing. 9. D. A. Patterson, J. L.Hennessy, “Computer Architecture: A quantitative approach”; Morgan Kauffmann feb,2002. 10. Hwan and Briggs, “ Computer Architecture and Parallel Processing”; MGH.VLSI 11. www.seas.gwu.edu/~bhagiweb/cs211/lectures/lectures.html 12.www.doc.ic.ac.uk/~phjk/AdvancedCompArchitecture/Lectures/ 13. http://cse.unl.edu/~jiang/cse430/Lecture%20Notes/index.html 14. http://in.docsity.com/en-docs/Advanced_Computer_Architecture__Lecture_notes__Newar

VL-918: VLSI TECHNOLOGY 3 0 0

Unit Topic Text

Book Lectures

I Clean room technology - Clean room concept – Growth of single crystal Si, surface contamination, cleaning & etching. & wafer preparation. Processing considerations: Chemical cleaning, getting the thermal Stress factors etc.

1 8

II

Oxidation Growth mechanism & kinetics, Silicon oxidation model, interface considerations, orientation dependence of oxidation rates thin oxides. Oxidation technique & systems dry & wet oxidation. Masking properties of SiO2. Epitaxy General Considerations, Molecular Beam Epitaxy, Vapor – Phase Epitaxy, Liquid – Phase Epitaxy, LPE Systems, Hetero-Epitaxy.

1

2

8

III

Diffusion The Nature of Diffusion, Diffusion in a Concentration Gradient, the Diffusion Equation, and Impurity Behavior: Silicon, Impurity Behavior: Gallium Arsenide, Diffusion Systems. Ion Implantation: Penetration Range, Implantation Damage, Annealing, Ion Implantation Systems.

2 8

IV Lithography Optical Lithography: optical resists, contact & proximity printing, projection printing, electron lithography: resists, mask generation. Electron optics: roster scans & vector scans, variable beam shape. X-ray lithography: resists & printing, X ray sources & masks. Ion lithography.

1 8

V

Etching Wet Chemical Etching, Dry Physical Etching, Dry Chemical Etching, Reactive Ion Etching, Chemically Assisted Ion Beam Techniques, Etching Induced Damage, Cleaning. Metallisation - Different types of metallisation, uses & desired properties

2

1

8

TEXT BOOKS: 1. S. M. Sze, “Modern Semiconductor Device Physics”, John Wiley & Sons, 2000. 2. Sorab K Ghandhi, “VLSI Fabrication Principles” 2nd Edition, Wiley Student Edition. 3. http://www.southalabama.edu/engineering/ece/faculty/akhan/Courses/EE539-Fall04/EE539.htm 4. http://www.youtube.com/watch?v=YtOILsvFonM 5. http://ai.eecs.umich.edu/people/conway/VLSI/ShortIntensiveCourses/VTI/VTI.Course.pdf 6. http://www-inst.eecs.berkeley.edu/~ee243/sp10/lectures.html 7. http://homepages.wmich.edu/~zandim/ECE524-page.html 8. http://www.eet.unsw.edu.au/sites/default/files/

SEMESTER-II VL-920 ALGORITHM FOR VLSI DESIGN AUTOMATION 3 0 3

Unit

Topic Text Book

Lectures

1. Logic synthesis & verification Introduction to combinational logic synthesis, Binary Decision Diagram, Hardware models for High-level synthesis.

8

2.

VLSI automation Algorithms: Partitioning: problem formulation, classification of partitioning algorithms, Group migration algorithms, simulated annealing & evolution, other partitioning algorithms.

8

3.

Placement, floor planning & pin assignment: problem formulation, simulation base placement algorithms, other placement algorithms, constraint based floor planning, floor planning algorithms for mixed block & cell design. General & channel pin assignment.

8

4. Global Routing: Problem formulation, classification of global routing algorithms, Maze routing algorithm, line probe algorithm, Steiner Tree based algorithms, ILP based approaches. Detailed routing: problem formulation, classification of routing algorithms, single layer routing algorithms, two layer channel routing algorithms, three layer channel routing algorithms, and switchbox routing algorithms.

8

5.

Over the cell routing & via minimization: two layers over the cell routers, constrained & unconstrained via minimization Compaction: problem formulation, one-dimensional compaction, two dimension based compaction, hierarchical compaction

8

TEXT BOOKS: 1. Naveed Shervani, “Algorithms for VLSI physical design Automation”, Kluwer Academic Publisher, Second edition. REFERENCE BOOKS: 1. Christophn Meinel & Thorsten Theobold, “Algorithm and Data Structures for VLSI Design”, KAP, 2002. 2. Rolf Drechsheler : “Evolutionary Algorithm for VLSI”, Second edition 3. Trimburger,” Introduction to CAD for VLSI”, Kluwer Academic publisher, 2002

VL-920P: ALGORITHMS FOR VLSI DESIGN AUTOMATION LAB:

1. Write a C program for the following algorithms in GRAPHS a. DFS ( Depth First Search) b. BFS ( Breadth First Search) c. Dijkstra’s

2. Write a C programs for the following CAD Algorithms

a. Partitioning b. Placement c. Routing

VL-921: LOW POWER VLSI DESIGN 3 1 0 Unit

Topic

Text Book

Lectures

1. Introduction: Needs for low power VLSI chips, Charging & Discharging Capacitance, Short–circuit Current in CMOS Circuit. CMOS Leakage Current. Static Current. Basic principles of Low Power Design. Device & Technology Impact on Low Power: Dynamic dissipation in CMOS, Effects of VDD & VT on Speed, Constraints on Reduction, Transistor sizing & Optimal Gate Oxide Thickness, Impact of Technology Scaling, Technology & Device Innovations.

T1

T2

8

2.

Simulation Power Analysis: SPICE Circuit Simulation, Gate level Logic Simulation, Architecture-level Analysis, Data Correlation Analysis in DSP systems. Monte Carlo Simulation. Probabilistic Power Analysis: Random Logic Signals, Probability & Frequency, Probabilistic Power Analysis Techniques, Signal Entropy.

T1

8

3.

Low Power Techniques: Circuit level: Transistor and Gate Sizing, Equivalent Pin Ordering, Network Restructuring and Reorganization. Special Latches & Flip-Flops, Low Power Digital Cell Library. Logic level: Gate Reorganization, Signal Gating, Logic Encoding, State Machine Encoding, Pre-computation Logic.

T1

8

4. Low power Architecture & System: Power & Performance Management, Switching Activity Reduction, Parallel Architecture with Voltage Reduction, Flow Graph Transformation. Low Power Clock Distribution: Power Dissipation in Clock Distribution, Single Driver vs. Distributed Buffers, Buffers and Devices Sizing under Process Variations, Zero Skew vs. Tolerable Skew, Chip & Package co-design of clock network.

T1

T2

8

5.

Low Power Arithmetic Components: Introduction, Circuit Design Style, Adders, Multipliers, Division. Low Power Memory Design: Introduction, Sources and Reduction of Power Dissipation in Memory Subsystem, Sources of Power Dissipation in DRAM and SRAM, Low Power DRAM circuits, Low Power SRAM circuits.

T2

T2

8

TEXT BOOKS: T1. Gary K. Yeap, “Practical Low Power Digital VLSI Design”, KAP, 2002 T2. Rabaey, Pedram, “Low power design methodologies” Kluwer Academic, 1997 REFERENCE BOOKS: R1. Kaushik Roy, Sharat Prasad, “Low-Power CMOS VLSI Circuit Design” Wiley, 2000

VL-921P: LOW POWER VLSI DESIGN LAB:

1. Simulate and analyze I-V characteristics of long and short-channel MOSFET transistors in CMOS technology.

2. Simulate and analyze the gate capacitance of an MOS transistor. (Gate Capacitance v/s VGS). 3. Simulate and analyze the impact of device variations on static CMOS inverter VTC. 4. Simulate and analyze the VTC of CMOS inverter as a function of supply voltage and substrate

bias. 5. Simulate and analyze dynamic power dissipation due to charging and discharging capacitances. 6. Simulate and analyze short-circuit currents during transients and impact of load capacitance on

short-circuit current in a CMOS inverter. 7. Simulate and analyze VTC of a two-input NAND & NOR data dependency. 8. Simulate and analyze a variable-threshold CMOS inverter and Combinational circuit. 9. Simulate and analyze low-power / low voltage D-Latch circuit. 10. Simulate and analyze following low-power circuits

a. The Full Adder b. The Binary Adder c. The Multiplier d. The Shifter.

VL-922 SOC Design 3 1 0

Unit

Topic Text Book

Lectures

1. Logic Gates. Introduction. Combinational Logic Functions. Static Complementary Gates. Switch Logic. Alternative Gate Circuits. Low-Power Gates. Delay Through Resistive Interconnect. Delay Through Inductive Interconnect.

T1

8

2.

Combinational Logic Networks. Introduction. Standard Cell-Based Layout. Simulation. Combinational Network Delay. Logic and Interconnect Design. Power Optimization. Switch Logic Networks. Combinational Logic Testing.

T1

8

3.

Sequential Machines Introduction. Latches and Flip-Flops. Sequential Systems and Clocking Disciplines. Sequential System Design. Power Optimization. Design Validation. Sequential Testing.

T1

8

4. Subsystem Design Introduction. Subsystem Design Principles. Combinational Shifters. Adders. ALUs. Multipliers. High-Density Memory. Field-Programmable Gate Arrays. Programmable Logic Arrays. References. Problems.

T1

8

5.

Floor-planning Introduction, Floor-planning Methods – Block Placement & Channel Definition, Global Routing, Switchbox Routing, Power Distribution, Clock Distributions, Floor-planning Tips, Design Validation. Off-Chip Connections – Packages, The I/O Architecture, PAD Design.

T1

8

TEXT BOOKS: T1. Wayne Wolf, “Modern VLSI Design – System – on – Chip Design”, Prentice Hall, 3rd Edition , 2008. REFERENCE BOOKS: R1. Wayne Wolf , “ Modern VLSI Design – IP based Design”, Prentice Hall, 4th Edition , 2008.

Elective-II VL-923: ASIC DESIGN 3 1 0

Unit

Topic Text Book

Lectures

1. Types of ASICs – Design flow – Economics of ASICs – ASIC cell libraries. CMOS logic: Sequential Logic Cells, Data Path Logic Cells – I/O Cells – Cell Compilers.

8

2.

ASIC Library Design: Transistors as Resistors, Transistor Parasitic Capacitance, Logical Effort, Library – Cell Design, Library Architecture, Gate – Array Design, Standard – Cell Design, Data-path-Cell Design. Programmable ASICs : The Anti-fuse, Static RAM, EPROM and EEPROM technology, Practical Issues, Specifications, PREP Benchmarks, FPGA Economics.

8

3.

Low Level Design Entry: Schematic Entry – low level design languages – PLA tools. An overview of Verilog HDL

8

4. Logic Synthesis: A logic Synthesis Example, A Comparators/ MUX, Inside a Logic Synthesizer, Verilog and Logic Synthesis.

8

5.

ASIC construction: Physical Design, CAD Tools, System Partitioning, Estimating ASIC Size, Power Dissipation, FPGA Partitioning, Partitioning Methods. Overview of Floor Planning & Placement, Routing

8

TEXT BOOKS: 1. J.S. Smith, “Application specific Integrated Circuits”, Addison Wesley, 1997.

VL-924: ADVANCED MICROCONTROLLERS & APPLICATIONS 3 1 0

Unit

Topic Text Book Lectures

1. Motivation for advanced microcontrollers – Low Power embedded systems, On-chip peripherals, low-power RF capabilities. Examples of applications.

8

2.

MSP430 – 16-bit Microcontroller family. CPU architecture, Instruction set, Interrupt mechanism, Clock system, Memory subsystem, bus –architecture. The assembly language and ‘C’ programming for MSP-430 microcontrollers.

8

3.

On-chip peripherals. WDT, Comparator, Op-Amp, Timer, Basic Timer, Real Time Clock (RTC), ADC, DAC, Digital I/O. Using the low-power features of MSP430. Clock system, low-power modes, Clock request feature, Low-power programming and interrupts.

8

4. ARM -32 bit Microcontroller family. Architecture of ARM Cortex M3 – General Purpose Registers, Stack Pointer, Link Register, Program Counter, Special Register,. Nested Vector Interrupt Controller. Interrupt behavior of ARM Cortex M3.

8

5.

Exceptions Programming. Advanced Programming Features. Memory Protection. Debug Architecture. Applications – Wireless Sensor Networking with MSP430 and Low-Power RF circuits; Pulse Width Modulation(PWM) in Power Supplies.

8

TEXT BOOKS:

1. Joseph Yiu “ The Definitive Guide to the ARM Cortex-M3, , Newnes, (Elsevier), 2008. 2. John Davies, “ MSP430 Microcontorller Basics”, Newnes (Elsevier Science), 2008. 3. MSP430 Teaching CD-ROM, Texas Instruments, 2008. 4. Sample Programs for MSP430 downloadable from msp430.com 5. David Patterson and John L. Henessay, “Computer Organization and Design”, (ARM Edition),

Morgan Kauffman.

VL-925: EMBEDDED NETWORKING WITH CAN AND CANOPEN 3 1 0

Unit

Topic Text Book

Lectures

1. Understanding Embedded Networking Requirements : Embedded Networking for Beginners, Code Requirements for Embedded Systems, Communication Requirements for Embedded Networking, Introduction to CANopen from the Application Level.

8

2.

The CAN Standard: Using Identifiers and Objects, The CANopen Object Dictionary, The Electronic Data Sheets and Device Configurations, Accessing the CANopen Object Dictionary with Service Data Objects, Handling Process Data with Process Data Objects, Network Management (NMT).

8

3.

CANopen Beyond DS301: About Masters and Managers (DS302), Device Profile for Encoder (DS406), Device Profile for Generic I/O (DS401), Safety - Relevant Communication (DSP304, DSP307).

8

4. CANopen Configuration Example: Evaluating the System Requirements, Choosing the Device and Tools, Configuring Single Devices, Overall Network Configuration, Network Simulation, Network Commissioning, Advanced Features and Testing.

8

5.

Underlying Technology: CAN - CAN Overview, An Introduction to CAN, Selecting a CAN Controller, CAN Development Tools. Implementing CANopen: Communication Layout and Requirements, Comparison of Implementation methods.

8

TEXT BOOKS:

1. Olaf Pfeiffer, Andrew Ayre, and Christian Keydel – “Embedded Networking with CAN and CANopen”, RTC Books.

2. http://www.kvaser.com/ High performance CAN interfaces. http://www.amplicon.com/ PC CANbus interface, Gateway, cards & Converters. Free

VL-926: SYNTHESIS & OPTIMIZATION OF DIGITAL CIRCUITS 3 1 0 Unit

Topic

Text Book

Lectures

1. Introduction: Microelectronics, semiconductor technologies and circuit taxonomy, Microelectronic design styles, computer aided synthesis and optimization. Graphs: Notation, undirected graphs, directed graphs, combinatorial optimization, Algorithms, tractable and intractable problems, algorithms for linear and integer programs, graph optimization problems and algorithms, Boolean algebra and Applications.

8

2.

Hardware Modeling: Hardware Modeling Languages, distinctive features, structural hardware language, Behavioral hardware language, HDLs used in synthesis, abstract models, structures logic networks, state diagrams, data flow and sequencing graphs, compilation and optimization techniques.

8

3.

Two Level Combinational Logic Optimization: Logic optimization, principles, operation on two level logic covers, algorithms for logic minimization, symbolic minimization and encoding property, minimization of Boolean relations. Multiple Level Combinational Optimizations: Models and transformations for combinational networks, algebraic model, Synthesis of testable network, algorithm for delay evaluation and optimization, rule based system for logic optimization.

8

4. Sequential Circuit Optimization: Sequential circuit optimization using state based models, sequential circuit optimization using network models. Schedule Algorithms: A model for scheduling problems, Scheduling with resource and without resource constraints, Scheduling algorithms for extended sequencing models, Scheduling Pipe lined circuits.

8

5.

Cell Library Binding: Problem formulation and analysis, algorithms for library binding, specific problems and algorithms for library binding (lookup table F.P.G.As and Antifuse based F.P.G.As), rule based library binding. Testing: Simulation, Types of simulators, basic components of a simulator, fault simulation Techniques, Automatic test pattern generation methods (ATPG), design for Testability (DFT) Techniques.

8

TEXT BOOKS:

1. Giovanni De Micheli, “Synthesis and Optimization of Digital Circuits”, Tata McGraw-Hill, 2003. 2. Srinivas Devadas, Abhijit Ghosh, and Kurt Keutzer, “Logic Synthesis”, McGraw-Hill, USA, 1994. 3. Neil Weste and K. Eshragian, “Principles of CMOS VLSI Design: A System Perspective,” 2nd

edition, Pearson Education (Asia) Pte. Ltd., 2000. 4. Kevin Skahill, “VHDL for Programmable Logic,” Pearson Education (Asia) Pvt. Ltd., 2000.

AS-920: RESEARCH METHODOLOGY L T P 2-0-0

Objectives: To enable the students to understand:

• Some basic concepts of research and its methodologies. • To select and define appropriate research problem and parameters. • The issues involved in planning, designing, executing, evaluating and reporting

research. • The technical aspects of how to do empirical research using some of the main data

collection and analysis of techniques used by researchers. • The meaning and techniques of sampling.

UNIT - I Introduction: Research objective and motivation. Types of research. Research approaches. Significance. Research method vs. methodology. Research process. UNIT - II Formulating a research problem: Literature review. Formulation of objectives. Establishing operational definitions. Identifying variables. Constructing hypotheses. UNIT - III Research design and data collection: Need and characteristics. Types of research design. Principles of experimental research design. Method of data collection. Ethical issues in collecting data. UNIT - IV Sampling and analysis of data: Need of sampling. Sampling distributions. Central limit theorem. Estimation: mean and variance. Selection of sample size. Statistics in research. Measures of central tendency. Dispersion. Asymmetry and relationships. Correlation and regression analysis. Displaying data. UNIT - V Hypothesis testing: Procedure. Hypothesis testing for difference in mean. Variance limitations. Chi-square test. Analysis of variance (ANOVA). Basic principles and techniques. Writing a research proposal. Text Books:

1. R. C. Kothari, Research Methodology: Methods and Techniques, 2nd edition, New Age International Publisher, 2009

2. Ranjit Kumar, Research Methodology: A Step-by-Step Guide for Beginners, 2nd Edition, SAGE, 2005

References: 1. Trochim, William M. The Research Methods Knowledge Base, 2nd Edition. Internet

WWW page, at URL: <http://www.socialresearchmethods.net/kb/> (version current as of October 20, 2006).

2. (Electronic Version): StatSoft, Inc. (2012). Electronic Statistics Textbook. Tulsa, OK: StatSoft. WEB: http://www.statsoft.com/textbook/. (Printed Version): Hill, T. & Lewicki, P. (2007). STATISTICS: Methods and Applications. StatSoft, Tulsa, OK.