# m.tech voltage reference thesis presentation

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- 1. Electrical Engineering, School of Engineering Shiv Nadar University Design and Performance Evaluation of Sub-1 V Voltage Reference Generator at 45 nm CMOS Technology Node M.Tech Thesis Presentation Presented By Rohit Singh AAA663 Supervisor Dr. Sonal Singhal

2. Acknowledgement 2 I truly acknowledge Dr. Sonal Singhal for her valuable guidance and support in this research work. I wish to thank Mr. Anurag Tiwari (senior analog designer at STMicroelectronics Pvt. Ltd. Greater Noida) for his technical support. 18 May 2014 3. Contents Introduction Objective Literature Review Performance parameters of voltage reference Methodology Design of CTAT-PTAT action based sub-1V reference generator Design of VTH based sub-1V reference generator Conclusion Future work References 3 18 May 2014 4. Introduction 4 A voltage reference circuit generates constant output voltage which does not depend on the operating voltage, temperature and process parameters. Voltage references are broadly used in ADC, DAC, flash memory, digital meters, smart sensors etc. Almost every analog devices have at least one voltage reference circuit. Voltage reference circuit 18 May 2014 5. Objective 5 To design a voltage reference circuit which should be nearly independent of following parameters Temperature Supply voltage variation Process corners in 45 nm CMOS technology node. The circuit should also consume as much as possible less quiescent current and also consume less die area. 18 May 2014 6. Literature Review 6 Various approaches to design the voltage reference circuits have been presented in literature. These can be categorized mainly in four approaches: (a) Making use of a Zener diode that breaks down at a known voltage when reverse biased, (b) Making use of the difference in the threshold voltage between an enhancement transistor and a depletion transistor, (c) Cancelling the negative temperature dependence of a PN junction with positive temperature dependence from a PTAT circuit, (d) Utilization of Subthreshold Characteristics. 18 May 2014 7. Literature Review 7 R. P. Baker et al [1] did detail investigation of long term stability of zener voltage reference Ho-Jun Song et al [2] described the detail working of Enhancement and Depletion Reference Giustolisi et al [5] described the detail working of different types of BGR circuits Several sub-band gap voltage reference circuits have already been reported in the literature that ensure sub-1 V operation [3, 4, 6, 7] 18 May 2014 8. Performance parameters of voltage reference 8 Sensitivity of output voltage of voltage reference to temperature variation at fixed input voltage is called temperature sensitivity. It is measured in terms of Temperature Coefficient (TC). Unit of TC is C-1 . Sensitivity of output voltage of voltage reference to supply voltage variation is called line sensitivity. Unit of LS is V-1 Temperature Sensitivity & Line Sensitivity 18 May 2014 9. Performance parameters of voltage reference 9 The ability of the voltage reference circuit to reject the noise and other spurious signals at a particular frequency on the power rail, and to provide a stable reference voltage, is specified as the power supply rejection ratio (PSRR). The PSRR is a function of frequency expressed in dB with the following definition The quiescent current, also known as the supply current, is the current required to operate the voltage reference circuit at steady-state Power Supply Rejection Ratio (PSRR) & Quiescent Current 18 May 2014 10. Performance parameters of voltage reference 10 Circuit size Power dissipation Device mismatch Other design consideration 18 May 2014 11. Methodology 11 Design Methodology 18 May 2014 Supply Compensation Process Compensation LS Noise PSRR Theoretical Framework Temperature Compensation Simulation of Design Performance Parameters TC Selection of Compensation Technique Realize CT by Circuit Structure 12. Methodology 12 Temperature compensation achieved by CTAT-PTAT action 18 May 2014 Realized by MOSFETs Subthreshold Characteristic PTAT Current Source Weighing Factor Weighing Factor CTAT Current Source Temperature Compensated Reference Voltage Governed by Theoretical Equations 13. Methodology 13 Temperature compensation achieved by VTH action 18 May 2014 LVT Device Subthreshold Arrangement (HVT-LVT) Zero TC HVT Device Weighing Factor Realized by MOSFETs in Subthreshold Region Posing Different Vth Temperature Compensated Vref 14. Methodology 14 Line Sensitivity compensation 18 May 2014 Temperature Compensated Network Feedback Network VDD + VDD Zero TC + Supply Compensated Vref 15. Design of CTAT-PTAT action based sub-1V reference generator 15 Circuit analysis: Proposed circuit 18 May 2014 16. Design of CTAT-PTAT action based sub-1V reference generator 16 In subthreshold operation, the drain current of MOSFET is given by equation (1) From the proposed circuit In this circuit Putting the value of Vgs from equation (1) to equation (2), we get Let Circuit analysis: PTAT current source generation 18 May 2014 (1) (2) (3) (4) and using equation (3), we get (5) 17. Design of CTAT-PTAT action based sub-1V reference generator 17 Circuit analysis: PTAT current source generation 18 May 2014 ID5 is mirrored to M2, so we have Now putting the value of ID5 from equation (5), we get Equation (7) clearly shows that ID2 is PTAT current source (6) (7) 18. Design of CTAT-PTAT action based sub-1V reference generator 18 In subthreshold conduction mode the VGS shows a linear relationship with temperature as given by equation (8) From the proposed circuit ID15 is mirrored to M3 and using equation (9), we have Since Vgs16 decreases with temperature, so ID3 also decreases with temperature and exhibits the CTAT characteristics. Circuit analysis: CTAT current source generation 18 May 2014 (8) (9) (10) 19. Design of CTAT-PTAT action based sub-1V reference generator 19 To obtain the temperature compensated reference voltage, PTAT current source (ID2) and CTAT current source (ID3) are added together in proper ration at Vref node and is allowed to flow through resistor R1. The following condition must be satisfied to achieve a zero TC Vref. We have Putting the value of ID2 and ID3 from equation (7) and (10) respectively to equation (12) and then differentiating equation (12) with respect to temperature we get Circuit analysis: Temperature compensation 18 May 2014 (11) (12) (13) 20. Design of CTAT-PTAT action based sub-1V reference generator 20 At the minimum supply voltage, MOSFETs M5 and M11 are in saturation region, and drain current flows accordingly through M5. With any increase in VDD, Vsg of transistor M5 increases which in turn increases the current in this branch, sub-sequentially increasing the voltage drop across R2. With the increase in voltage at positive terminal of OP-AMP, its output voltage starts increasing. Also seen from figure of proposed circuit, OP-AMP output is connected to the gate terminal of transistor M5, thus decreasing the Vsg of this transistor. This feedback action compensates any change in the current due to variation in power supply. Also ID5 is mirrored to transistor M2, thereby making ID2 (PTAT current) independent of variation in supply voltage. Circuit analysis: Supply voltage variation compensation of PTAT current source 18 May 2014 21. Design of CTAT-PTAT action based sub-1V reference generator 21 At the minimum supply voltage, MOSFETs M17 is in saturation region, and drain current flows accordingly in this branch i.e. ID17 = ID16. Also the current through M16 governs the gate to source voltage of this transistor. Now if VDD increases from its minimum value, then PTAT current action increases the OP-AMP output, thereby increasing the gate voltage of transistor M17, maintaining the constant VGS . The current in transistor M15 i.e. ID15 therefore independent of variation in supply voltage. The ID15 is mirrored to ID3thereby generating the supply variation independent CTAT current at Vref node. Circuit analysis: Supply voltage variation compensation of PTAT current source 18 May 2014 22. Design of CTAT-PTAT action based sub-1V reference generator 22 The average TC is obtained as 19 ppm/C over temperature range of -25 to 85 C at the supply voltage of 0.6 V. Simulated results: TC 18 May 2014 23. Design of CTAT-PTAT action based sub-1V reference generator 23 The average value of LS is obtained as 0.93 %/V over supply range of 0.6 to 1 V at 27 C temperature. Simulated results: LS 18 May 2014 24. Design of CTAT-PTAT action based sub-1V reference generator 24 Circuit possesses an excellent supply rejection ratio of -55 dB up to 1 MHz frequency Simulated results: PSRR 18 May 2014 25. Design of CTAT-PTAT action based sub-1V reference generator 25 Comparison of proposed circuit with some recent voltage reference circuits 18 May 2014 Proposed Circuit Proposed Circuit Without Feedback Ref [8] Ref [9] Ref [10] Ref [11] Technology Node 45 nm 45 nm 90 nm 90 nm 130 nm 90 nm Temperature range (C) -25 to 85 -25 to 85 -40 to 125 -40 to 125 0 to 100 -40 to 125 supply voltage range (V) 0.6-1.0 0.6-1.0 1.6-3.6 0.9-1.5 1.2-2.3 1.1-3.3 Reference Voltage (mV) 173 159.64 811 512 781 423 TC (ppm/C) 19 811 39.5 23.66 48 72 Line Sensitivity (%/V) 0.93 66.65 2.03 1.12 0.34 2.0 26. Design of CTAT-PTAT action based sub-1V reference generator 26 Components Values 18 May 2014 Transistor Channel length Channel width M1 10um 50um M2 100nm 9.5um M3 100nm 2um M4 100nm 10um M5 100nm 5um M6 100nm 2.5um M7 100nm 5um M8 100nm 2.5um M9 100nm 5um M10 100nm 2.5um M11 100nm 5um M12 50nm 500nm M13 100nm 2.5um M14 1um 500nm M15 100nm 5um M16 100nm 10um M17 100nm 5um M18 100nm 2.5um M19 100nm 5um Passive Component Value R1 5.5K R2 5.5K R3 10K 27. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 27 Circuit analysis: Proposed circuit 18 May 2014 28. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 28 The proposed reference voltage in this work can be represented in simple manner as shown below. The load transistor is operating in subthreshold mode so by using equation (1), we can write the expression of Vref as Circuit analysis: Derivation of output voltage expression 18 May 2014 VDD Iref VREF (14) M1 29. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 29 From the proposed circuit VGS4 = VGS11 + VGS12 (15) Putting the value of VGS from equation (1) in (15), we have In equation (16) ID11 = ID12 (since in same branch), let Circuit analysis: Derivation of output voltage expression 18 May 2014 (16) 30. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 30 And let assume m is same for all the MOSFETs operating in subthreshold region. Now we get From equation (17) we obtained the value of ID4 given in equation (18) In this work Iref = ID3, Circuit analysis: Derivation of output voltage expression 18 May 2014 (17) (18) (19) 31. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 31 Putting the value of ID4 from equation (18) to equating (19) and then putting the value of Iref from equation (19) to (14) and then doing some rearrangement we get the final value of Vref i.e. Where Circuit analysis: Derivation of output voltage expression 18 May 2014 (20) 32. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 32 Circuit analysis: Temperature & op-amp offset compensation 18 May 2014 The relation of Vth with temperature is given by equation (21) Now putting the value of Vth from equation (21) to 20 and then differentiating with temperature we get If D = 1, the Vref will be independent of temperature but D is not made 1 intentionally. Due to op-amp offset voltage the output voltage of op-amp also increases with temperature which decreases the Vref so to compensate the error due to op-amp offset D is chosen 8. (21) (22) 33. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 33 Circuit analysis: Temperature & op-amp offset compensation 18 May 2014 The simulated reference voltage (Vref) versus temperature for different D at supply voltage 0.8 V 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 -65 -15 35 85 135 Voltage Temperature op-amp output Vref D=1 Vref D=8 34. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 34 At the minimum supply voltage, MOSFETs M13 and M6 are in saturation region, and drain current flows accordingly through M13 and M6. With any increase in VDD, Vsg of transistor M13 increases which in turn increases the current in this branch, sub-sequentially increasing the voltage drop across drain of M12. With the increase in voltage at positive terminal of OP-AMP, its output voltage starts increasing. Also seen from figure of proposed circuit, OP-AMP output is connected to the gate terminal of transistor M13, thus decreasing the Vsg of this transistor. This feedback action compensates any change in the current due to variation in power supply. Also ID13 is mirrored to transistor M3, thereby making ID3 independent of variation in supply voltage. Circuit analysis: Supply variation compensation 18 May 2014 35. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 35 From equation (20) Vref can also be written as Because Vth1 = Vth11 = Vth12 (all are LVT NMOS) According to Lin et al [12] the threshold voltage variations of both the HVT and LVT NMOS transistors go to the same trend for different corners due to same doping condition. Circuit analysis: Process corner compensation 18 May 2014 36. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 36 The average TC is obtained as 16 ppm/C over temperature range of -65 to 175 C at the supply voltage of 0.8 V Simulated results: TC 18 May 2014 37. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 37 The average value of LS is obtained as 0.53 %/V over supply range of 0.8 to 1.8 V at 27 C temperature. Simulated results: LS 18 May 2014 38. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 38 Circuit possesses an excellent supply rejection ratio of -42 dB up to 1 MHz frequency Simulated results: PSRR 18 May 2014 39. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 39 Monte Carlo Distribution of Vref Value at Supply Voltage 0.8 V and Temperature 27 C with Dispersion in Process Parameters for 1500 runs . The mean value of Vref was obtained as 265 mV Monte Carlo Simulation 18 May 2014 0 50 100 150 200 250 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.3 0.31 0.32 0.33 0.34 0.35 Frequency Reference Voltage (V) 40. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 40 Monte Carlo Distribution of Vref Value at Supply Voltage 0.8 V and Temperature 27 C with Dispersion in Devices Matching for 1500 runs. The mean value of Vref was obtained as 264.6 mV Monte Carlo Simulation 18 May 2014 0 20 40 60 80 100 120 140 160 180 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.3 0.31 0.32 0.33 0.34 0.35 Frequency Reference Voltage (V) 41. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 41 Monte Carlo Distribution of Vref Value at Supply Voltage 0.8 V and Temperature 27 C with Dispersion in Devices Matching and Process Parameters Simultaneously for 1500 runs. The mean value of Vref was obtained as 264 mV Monte Carlo Simulation 18 May 2014 0 20 40 60 80 100 120 140 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.3 0.31 0.32 0.33 0.34 0.35 Frequency Reference Voltage (V) 42. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 42 Simulated results: Summary of the Simulations Results 18 May 2014 Technology Feature Size 45 nm Reference Voltage 261 mV Supply Voltage Range 0.8 - 1.8 V Quiescent Current @ 27 C 6.88 uA Temperature Coefficient 15.96 ppm/C Temperature Range -65 175 C Line Sensitivity 0.538 %/V Process Sensitivity () 1.31 % PSRR @ 100 Hz @ 10 MHz -42.68 dB -42.19 dB 43. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 43 Comparison of proposed circuit with some recent voltage reference circuits 18 May 2014 Parameter Proposed Circuit Ref [8] Ref [9] Ref [10] Ref [11] Technology Node (nm) 45 90 90 130 90 Minimum Supply Voltage (volt) 0.8 1.6 0.9 1.2 1.1 Reference Voltage (mV) 261 811 512 781 423 Line Sensitivity (%/V) 0.538 2.03 1.12 0.34 2.0 Supply Voltage Range (volt) 0.8 - 1.8 1.6-3.6 0.9-1.5 1.2-2.3 1.1-3.3 Temperature Coefficient (ppm/C) 15.96 39.5 23.66 48 72 Temperature Range (C) -65 - 175 -40 to 125 -40 to 125 0 to 100 -40 to 125 44. DESIGN OF VTH BASED SUB-1V REFERENCE GENERATOR 44 Components Values 18 May 2014 Component Name Length Width M1 50 nm 300 nm M2 50 nm 300 nm M3 50 nm 600 nm M4 50 nm 300 nm M5 50 nm 600 nm M6 50 nm 300 nm M7 50 nm 400 nm M8 50 nm 1 um M9 50 nm 400 nm M10 50 nm 1 um M11 50 nm 600 nm M12 50 nm 600 nm M13 50 nm 300 nm 45. Conclusion 45 CTAT-PTAT and VTH-action based circuits shows the Vref of 173 and 260 mV respectively and were found to operate at supply voltages down to 0.6 and 0.8 V respectively. CTAT-PTAT and VTH-action based circuits shows the TC of 19 and 16 ppm/oC respectively. CTAT-PTAT and VTH-action based circuits shows the LS of 0.93 and 0.538 %/V respectively. Due to low supply voltage, TC and LS these circuits are very attractive for battery operated electronic applications. 18 May 2014 46. Future work 46 The current work presented the design and performance evaluation of sub-1V voltage reference circuits. Characterizations of the proposed circuits have carried out by simulation studies However the fabrication of the proposed designs is required to validate these results. Also any external parameters such as the effect of device mismatch on output voltage need to be investigated on the real environment. 18 May 2014 47. References 47 [1] R. P. Baker and J. Nagy Jr. "An investigation of long-term stability of Zener voltage references", IRE Trans. Instrum., vol. I, pp.226 -231 1960 [2] Ho-Jun Song, Choong-Ki Kim " A temperature-stabilized SOI voltage reference based on threshold voltage difference between enhancement and depletion NMOSFETs " IEEE J. Solid-State Circuits, vol. 28, no. 6, June 1993, pp.671-677 [3] G. De Vita and G. Iannaccone, A sub-1-V, 10 ppm/ C , nano power voltage reference generator, IEEE J. Solid-State Circuits, vol. 42, no.7, pp. 15361542, Jul. 2007. [4] Ueno, Ken, et al. "A 300 nW, 15 ppm/C, 20 ppm/V CMOS voltage reference circuit consisting of subthreshold MOSFETs." Solid-State Circuits, IEEE Journal of 44.7 (2009): 2047-2054. [5] Giustolisi, Gianluca, and Gaetano Palumbo. "A detailed analysis of power-supply noise attenuation in bandgap voltage references." Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on 50.2 (2003): 185-197. [6] H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi,and K. Sakui, ACMOS bandgap reference circuit with sub-1-V operation, IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 670674, May1999. 18 May 2014 48. References 48 [7] K. N. Leung and P. K. T. Mok, A sub-1-V 15 ppm/ C CMOS bandgap voltage reference without requiring low threshold voltage device, IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 526530, Apr.2002. [8] Samir, Anass, Edith Kussener, Wenceslas Rahajandraibe, Ludovic Girardeau, Yannick Bert, and Herv Barthlemy. "A sub-1-V, high precision, ultra low-power, process trimmable, resistorless voltage reference with low cost 90-nm standard CMOS technology." Analog Integrated Circuits and Signal Processing 73, no. 3 (2012): 693-706. [9] Tsitouras, A., F. Plessas, M. Birbas, J. Kikidis, and G. Kalivas. "A sub-1V supply CMOS voltage reference generator." International Journal of Circuit Theory and Applications 40, no. 8 (2012): 745-758 [10] Luo, Hao, Yan Han, Ray CC Cheung, Guo Liang, and Dazhong Zhu. "Subthreshold CMOS voltage reference circuit with body bias compensation for process variation."Circuits, Devices & Systems, IET-6, no.3, pp.198-203, IEEE, 2012. [11] Borejko, Tomasz, and Witold A. Pleskacz. "A resistorless voltage reference source for 90 nm cmos technology with low sensitivity to process and temperature variations." In Design and Diagnostics of Electronic Circuits and Systems, 2008.DDECS 2008. 11th IEEE Workshop on, pp. 1-6. IEEE, 2008. [12] Lin, Hongchin, and Dern-Koan Chang. "A low-voltage process corner insensitive subthreshold CMOS voltage reference circuit." In Integrated Circuit Design and Technology, 2006. ICICDT'06. 2006 IEEE International Conference on, pp. 1-4. IEEE, 2006. 18 May 2014 49. 18 May 2014