Multi-core

What is parallel programming ? Classification of parallel architectures

Dimension of instruction Dimension of data

Memory models for parallel programming Distributed memory model Share memory model

Multi-core architectures Steps in parallelization

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CONCURRENT

Two or more actions progress at the same time.

PARALLEL

Two or more actions execute simultaneously.

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How to write a program that can execute correctly on two proccesors or more.

Design considerations Correctness Efficiency Simplicity Scalability

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Single Instruction Single Data: SISD

Single Instruction Multiple Data: SIMD

Multiple Instruction Single Data: MISD

Multiple Instruction Multiple Data: MIMD

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No parallelism

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Vector machine Graphic processors

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No application (at this time)

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Multi-core architectures

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SHARED MEMORY MODEL

Multiple processors connect to one shared memory.

All processors can access same memory locations.

DISTRIBUTED MEMORY MODEL

Each processor connects to its private memory.

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SHARED MEMORY

Bottleneck for memory access

No data transfer

Easy for share data

DISTRIBUTED MEMORY

Better memory access

Data transfer from non-local memory

Easy for private data

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AMD Multicore Opteron Sun UltraSparc T1 IBM Cell Broadband Engine (CBE) Intel Core2 Duo

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Source: C. Hughes &T. Hughes, Professional Multicore Programming: Design and Implementation for C++ Developers, Wiley, 2008.

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Source: C. Hughes &T. Hughes, Professional Multicore Programming: Design and Implementation for C++ Developers, Wiley, 2008.

Jaruloj Chongstitvatana Parallel Programming: Introduction 15

Source: C. Hughes &T. Hughes, Professional Multicore Programming: Design and Implementation for C++ Developers, Wiley, 2008.

Jaruloj Chongstitvatana Parallel Programming: Introduction 16

Source: C. Hughes &T. Hughes, Professional Multicore Programming: Design and Implementation for C++ Developers, Wiley, 2008.

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Source: C. Hughes &T. Hughes, Professional Multicore Programming: Design and Implementation for C++ Developers, Wiley, 2008.

Starting from sequential code

Identify possible concurrency Design and implement Test for correctness Tuning for performance

May effect correctness If tuning is impossible, consider redesign

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Data race Deadlock

Notes: Results might be slightly different for each

run due to round-off error for different sequence of operations.

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