multi-layer channel routing complexity and algorithms rajat k. pal annajiat alim rasel 0409052002...

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Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 [email protected] CSE 6404 VLSI Layout Algorithms Page 67 -> 78 as a part of MS at BUET, 2009

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Page 1: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Multi-Layer Channel RoutingComplexity and Algorithms

Rajat K. Pal

Annajiat Alim Rasel0409052002

[email protected] 6404 VLSI Layout Algorithms

Page 67 -> 78as a part of MS at BUET, 2009

Page 2: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Cell

• Circuit element• Simple• Pre-designed

C

EA D

B

F

Page 3: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

ASIC (Standard Cell) Design Example

D C C B

A C C

D C D B

BCCC

CellMetal1Metal2

GNDVDD

C D

A BCell library

Placement [©Sherwani]

Page 4: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Channel

C

EA D

B

F

VLSI Layout

Channel

Page 5: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

A D

Channelnets: set of terminals to be connected

Channel routing

Page 6: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Transitively Oriented Graph/ Comparability Graph

u

v w wv

u x

Page 7: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Transitively Oriented Graph/ Comparability Graph ??

u

v w wv

u x

Page 8: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Transitively Oriented Graph/ Comparability Graph

- Vertex Types(intermediate)

u (source)u

V(source)

w(sink)

w(source)

v(sink)

(sink)x

Page 9: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Channel Specification

5 3 2 6 1 7 4

5 3 6 2 1 7 4

I 5

I 3

I 2

I 6

I 1

I 7

I 4

A

D

VH routin

g

Page 10: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Channel Specification

5 3 2 6 1 7 4

5 3 6 2 1 7 4

I 5

I 3I 2

I 6

I 1

I 7

I 4

A

D

S5 S3 S6 S2 S1 S7 S4

I 5

I 3

I 2

I 6

I 1

I 7

I 4

A

D

Channel Intervals

Page 11: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Channel Intervals

S5 S3 S6 S2 S1 S7 S4

I 5

I 3

I 2

I 6

I 1

I 7

I 4

A

D

HCG

2

3

1

45

6

7

Page 12: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Channel Intervals

HCG and

HNCG

2

3

1

45

6

7

S5 S3 S6 S2 S1 S7 S4

I 5

I 3

I 2

I 6

I 1

I 7

I 4

A

D

Page 13: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Channel Intervals

HNCG

2

3

1

45

6

7

S5 S3 S6 S2 S1 S7 S4

I 5

I 3

I 2

I 6

I 1

I 7

I 4

A

D

Page 14: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

clique cover

3

4

1

2

5

7

6

While G ≠ empty

choose a maximal clique

delete the vertices of the clique

algorithm

Page 15: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

clique cover

{1, 4, 5}

3

4

1

2

5

7

6

Page 16: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

clique cover

{1, 4, 5}

3

7

6{ 2, 7 }

2

Page 17: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

clique cover

{1, 4, 5}

36{ 2, 7 }

{ 3 }

Page 18: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

clique cover

{1, 4, 5}

6{ 2, 7 }

{ 3 }

{ 6 } But, the cliquecover may not beminimum one

Page 19: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

clique cover

{1, 4, 5}

{ 2, 7 }

{ 3 }

{ 6 } But, the cliquecover may not beminimum one

3

4

1

2

5

7

6

Page 20: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

clique cover

{1, 4, 5} { 2, 7 }

{ 3 } { 6 }

Independent set 3

4

1

2

5

7

6

{5, 3, 6} {2, 3, 6}

{2, 1, 6}{7, 1}{7, 4}

Page 21: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

clique cover

{1, 4, 5} { 2, 7 }

{ 3 } { 6 }

Independent set 3

4

1

2

5

7

6

{5, 3, 6} {2, 3, 6}

{2, 1, 6}{7, 1}{7, 4}

Page 22: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

clique cover

{1, 4, 5} { 2, 7 }

{ 3 } { 6 }

Independent set

{5, 3, 6} {2, 3, 6}

{2, 1, 6}{7, 1}

I2

I7

I5

I4

I1

I3

I6

{7, 4}

For perfect graph

(G)=κ(G)

(G)= size of the max independent setκ(G) = size of the min clique cover

Page 23: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Minimum clique cover

3

4

1

2

5

7

6

Sort the intervals w. r. t. Li

Orient the edges b. t. r. Ri < Lj While G ≠ empty

choose a maximal clique from sorted list

delete the vertices of the clique

algorithm

Page 24: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

3

4

1

2

5

7

6

I2

I7

I5

I4

I1

I3

I6

5

6

3

1 7

2

4

1 2

3 4

5 6 7

Page 25: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

3

4

1

2

5

7

6

I2

I7

I5

I4

I1

I3

I6

5

6

3

1 7

2

4

Page 26: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

3

4

1

2

5

7

6

5

6

3

1 7

2

4

5 2 7

Page 27: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

3

4

1

2

5

7

6

5

6

3

1 7

2

4

5 2 7

Page 28: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

3

4

1

6

5

3

7

2

5 2 7

3 1 4

Page 29: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

3

4

1

6

5

3

7

2

5 2 7

3 1 4

Page 30: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

63

5 2 7

3 1 4

6

Obviously, this is the minimum clique

Page 31: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page
Page 32: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Lemma

Lemma 3.1

For any vertices vi , vj and vk of the HNCG,if vi vj and vj vk , then vi vk

Proof From definition,

Ri < Lj and Rj < Lk

From the interval,

Lj < Rj

So, we have

Ri < Lk

So, the HNCG is acomparability graph

Page 33: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Lemma

Lemma 3.2

Each maximal clique computed by thealgorithm MCC1 in step 3 has exactly one

vertex from each maximal independent set of G

case 1:

There is no interval ending on the left side ofthe starting column of any interval in A

We consider any maximal independent set A

Page 34: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Independent set

{5, 3, 6} {2, 3, 6}

{2, 1, 6}{7, 1}

I2

I7

I5

I4

I1

I3

I6

{7, 4}

Lemma 3.2 (cont.) 5 2 7

3 1 4

6

In this case, vertices in A will be selected as the source vertex of successive maximal cliques

Page 35: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

case 2:

There is an interval ending on theleft side of the starting column of at least

one of the intervals in A

Lemma 3.2 (cont.)

Page 36: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Independent set

{5, 3, 6}{2, 3, 6}

{2, 1, 6}{7, 1}

I2

I7

I5

I4

I1

I3

I6

{7, 4}

Lemma 3.2 (cont.) 5 2 7

3 1 4

6

Let, I be the rightmost intervalselected by MCC1 in C1 such

that at least one interval of A starts after I ends &

J be the interval of A with leftmost end point among the intervals

of A , starting after I ends

Page 37: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Independent set

{5, 3, 6}{2, 3, 6}

{2, 1, 6}{7, 1}

I2

I7

I5

I4

I1

I3

I6

{7, 4}

Lemma 3.2 (cont.) 5 2 7

3 1 4

6

So, one interval of A is chosen bythe algorithm MCC1 in C1

So, exactly one interval of A is chosen in C1

Page 38: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Lemma

Lemma 3.3

MCC1 computes a minimum clique cover of theHNCG, G=(V, E’) consisting of dmax cliques

Proof

dmax = size of the maximum

independent set

From, lemma 3.2

A will become emptywhen Cl is computed

Let, the size of the maximalindependent set A be l,

where l < dmax

Page 39: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Lemma 3.3 (cont.)

{5, 3, 6}{2, 3, 6}

{2, 1, 6}{7, 1}{7, 4}

5 2 7

3 1 4

6The last clique computed by MCC1will include the last interval fromeach maximum independent set

Page 40: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Lemma 3.3 (cont.)

{5, 3, 6}{2, 3, 6}

{2, 1, 6}{7, 1}{7, 4}

5 2 7

3 1 4

6The last clique computed by MCC1will include the last interval fromeach maximum independent set

So, it follows that

the number of cliques computed

by MCC1 is exactly dmax

Page 41: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Theorem 3.1

The construction of the HNCG, G=(V, E’) andits transitively oriented graph G*=(V, F) fromthe intervals belonging to a channel can beimplemented in O(n+e) time, where n is the

number of nets and e is the size of the HNCG

Page 42: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Theorem 3.1 (cont.)

orienting of the edges can be done by

scanning all the intervalsexactly once from left to right

The following cases mayoccur at a column

position while scanning

an interval starts

an interval terminates

all the intervals continue

Page 43: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Theorem 3.1 (cont.)

case 1: while Ii starts, if Ij S1 terminatedbefore Ii ; orient an edge vj vi in G*

case 2:If Ii terminates at current column

position, we add Ii in the set S1

case 3: No action required

Page 44: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Theorem 3.1 (cont.)

In any instance of the CRP, at most two intervalsmay start or terminate at the same column.In this case, both the intervals are processedone after another.

The scanning of the columns requires O (n) time

The algorithm spends constant time in

introducing each edge of G and G*

The introducing time of all the edges is O (e)

Page 45: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Theorem 3.2

The algorithm MCC1 correctly computes arouting solution for the two layer CRPwithout vertical constraints using dmax

tracks. MCC1 can be executed in O(n+e) time.

Page 46: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

O (n)

O (n+e)

O (n+e)

In total,

O (n+e) time

Page 47: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Theorem 3.3

The algorithm MCC2 correctly computes arouting solution for the two layer CRPwithout vertical constraints using dmax

tracks. MCC2 can be executed in O(nlogn) time

Page 48: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Self-balancing binary search tree

Operation Big-O time

Lookup O(log n)

Insertion O(log n)

Removal O(log n)

In-order iteration over all elements O(n)

The overall worst-case Build Time is O(nlog n)

Times for various other operations in terms of number of nodes in the tree n:For some implementations these times are worst-case, while for others they are amortized.

Page 49: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Self-balancing binary search tree

Operation Big-O time

Lookup O(log n)

Insertion O(log n)

Removal O(log n)

In-order iteration over all elements O(n)

The overall worst-case Build Time is O(nlog n)

Times for various other operations in terms of number of nodes in the tree n:For some implementations these times are worst-case, while for others they are amortized.

In computer science, especially analysis of algorithms, amortized analysis finds the average running time per operation over a worst-case sequence of operations. Amortized analysis differs from average-case performance in that probability is not involved; amortized analysis guarantees the time per operation over worst-case performance.

Page 50: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

O (n)

O (n+e)

O (nlogn)

O (logn)

Building Self Balancing BST of

intervals sorted on their starting column numbers - O (nlogn)

Total=nlogn+(n + e) + n + n X (logn + logn)=2n + e + nlogn + 2nlogn=2n + e + 3nlogn=nlogn

O (logn)

Page 51: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Vertex Representation• Class Vertex {

– int key; //starting column and sequence number in transitive orientation

– int n; //vertex name: v1, v2 … etc. Prefix “v” will be used for now on for clarity

– double endingPosition; // ending column, double value such as 3.5 indicates that it ended before column 4. Thought it should be int, but due to lack of numbers between 3 and 4, double values are used.

– int outDegree;}

Page 52: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Input / Initialization

• Assuming for the given example following declarations and initializations have been done1) Vertex v1, v2, v3, v4, v5, v6, v7;2) v1.n=1; v2.n=2; …………. V7.n=7;3) All vertexes know their key (startingPosition) and

endingPosition

Page 53: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

• Insert v5

k=1end=3.5

outDeg=4n = v5

Page 54: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

• Insert v3

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

Page 55: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

• Insert v6

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

k=3end=5.5

outDeg=0n = v6

Page 56: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

The balance factor of a node is the height of its right subtree minus the height of its left subtree. A node with balance factor 1, 0, or -1 is considered balanced. A node with any other balance factor is considered unbalanced and requires rebalancing the tree. The balance factor is either stored directly at each node or computed from the heights of the subtrees.

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

k=3end=5.5

outDeg=0n = v6

Here v5 is unbalanced

Page 57: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

In right right case, tree is balanced using left rotation. So, left rotating v5, v3, v6 from v3

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

k=3end=5.5

outDeg=0n = v6

Here v5 is unbalanced

Page 58: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

k=3end=5.5

outDeg=0n = v6

Here v5 is now balanced

Page 59: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

k=3end=5.5

outDeg=0n = v6

Inserted v2

k=4end=5.7

outDeg=0n = v2

Page 60: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

k=3end=5.5

outDeg=0n = v6

Inserted v5

k=4end=5.7

outDeg=0n = v2

K=5End=6.5

outDeg=0n = v1

Page 61: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

k=3end=5.5

outDeg=0n = v6

Tree now has become unbalanced and v6, v2, v1 now forms a right right case

k=4end=5.7

outDeg=0n = v2

K=5End=6.5

outDeg=0n = v1

Page 62: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

k=3end=5.5

outDeg=0n = v6

Lets balance the tree using a left rotation

k=4end=5.7

outDeg=0n = v2

K=5End=6.5

outDeg=0n = v1

Page 63: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

k=3end=5.5

outDeg=0n = v6

Tree is now balanced

k=4end=5.7

outDeg=0n = v2

K=5End=6.5

outDeg=0n = v1

Page 64: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

k=3end=5.5

outDeg=0n = v6

Changed for a better view

k=4end=5.7

outDeg=0n = v2

K=5End=6.5

outDeg=0n = v1

Page 65: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

k=3end=5.5

outDeg=0n = v6

Inserted v7

k=4end=5.7

outDeg=0n = v2

K=5End=6.5

outDeg=0n = v1

K=6End=8

outDeg=0n = v7

Page 66: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

k=3end=5.5

outDeg=0n = v6

Tree is unbalenced. v3, v2, and v1 forms a right right case which is to be solved using a left rotation

k=4end=5.7

outDeg=0n = v2

K=5End=6.5

outDeg=0n = v1

K=6End=8

outDeg=0n = v7

Page 67: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

k=3end=5.5

outDeg=0n = v6

Tree is now balenced

k=4end=5.7

outDeg=0n = v2

K=5End=6.5

outDeg=0n = v1

K=6End=8

outDeg=0n = v7

Page 68: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

k=3end=5.5

outDeg=0n = v6

Insert v7

k=4end=5.7

outDeg=0n = v2

K=5End=6.5

outDeg=0n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

Page 69: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

k=3end=5.5

outDeg=0n = v6

V1, v7, v4 forms a right right case requiring to be balanced

k=4end=5.7

outDeg=0n = v2

K=5End=6.5

outDeg=0n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

Page 70: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

k=3end=5.5

outDeg=0n = v6

Tree is now balanced

k=4end=5.7

outDeg=0n = v2

K=5End=6.5

outDeg=0n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

Page 71: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 1 - Building BST, Done!

k=1end=3.5

outDeg=0n = v5

k=2end=4.5

outDeg=0n = v3

k=3end=5.5

outDeg=0n = v6

Better view

k=4end=5.7

outDeg=0n = v2

K=5End=6.5

outDeg=0n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

Page 72: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Channel Intervals

S5 S3 S6 S2 S1 S7 S4

I 5

I 3

I 2

I 6

I 1

I 7

I 4

A

D

HCG

2

3

1

45

6

7

Step 2 – Construct HNCG

Page 73: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Channel Intervals

HCG and

HNCG

2

3

1

45

6

7

Step 2 – Construct HNCG

S5 S3 S6 S2 S1 S7 S4

I 5

I 3

I 2

I 6

I 1

I 7

I 4

A

D

Page 74: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Channel Intervals

HNCG

2

3

1

45

6

7

Step 2 – Construct HNCG

S5 S3 S6 S2 S1 S7 S4

I 5

I 3

I 2

I 6

I 1

I 7

I 4

A

D

Page 75: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Channel Intervals

HNCG

2

3

1

45

6

7

Step 2 – Transitive Orientation

S5 S3 S6 S2 S1 S7 S4

I 5

I 3

I 2

I 6

I 1

I 7

I 4

A

D

Page 76: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

• Similarly, whole graph is made transitively oriented and “outDegree” field of all vertexes are now updated

v3

v4

v1

v2

v5

v7

v6

5

6

3

1 7

2

4

Step 2 – Transitive Orientation

Page 77: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

• While (! tree.empty()){– min = tree.findMinVertex();– C = C U min– Tree.delete(min)– If min.outDegree <> 0 then // not a sink

• Next = tree.findGreaterThan(min.endingPosition)

– Else • CliqueCover = CliqueCover U C• C = Empty

}

Step 3 – Overview

Page 78: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=3end=5.5

outDeg=2n = v6

k=4end=5.7

outDeg=2n = v2

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

Page 79: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=3end=5.5

outDeg=2n = v6

Find min

k=4end=5.7

outDeg=2n = v2

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

Page 80: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=3end=5.5

outDeg=2n = v6

Find min

k=4end=5.7

outDeg=2n = v2

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

Page 81: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=3end=5.5

outDeg=2n = v6

Min = v5Add v5 to Clique, C

k=4end=5.7

outDeg=2n = v2

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

Page 82: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=3end=5.5

outDeg=2n = v6

Tree.delete (v5)

k=4end=5.7

outDeg=2n = v2

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

{ v5 }

Page 83: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=3end=5.5

outDeg=2n = v6

Tree.delete (v5)

k=4end=5.7

outDeg=2n = v2

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

{ v5 }

Page 84: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=3end=5.5

outDeg=2n = v6

v5.outDeg > 0, so, its not sink, continuetree.findGreaterThan(v5.end)

k=4end=5.7

outDeg=2n = v2

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

{ v5 }

Page 85: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=3end=5.5

outDeg=2n = v6

min = tree.findGreaterThan(v5.end)// 4 (v2) is greater than v5.end = 3.5

k=4end=5.7

outDeg=2n = v2

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

{ v5 }

Page 86: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=3end=5.5

outDeg=2n = v6

Add min to Clique

k=4end=5.7

outDeg=2n = v2

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

{ v5 }

Page 87: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=3end=5.5

outDeg=2n = v6

Add min to Clique

k=4end=5.7

outDeg=2n = v2

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

{ v5, v2 }

Page 88: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=3end=5.5

outDeg=2n = v6

Now to delete v2, we need to swap v6 (3) and v2 (4)

k=4end=5.7

outDeg=2n = v2

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

{ v5, v2 }

Page 89: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=3end=5.5

outDeg=2n = v6

Now to delete v2, we need to swap v6 (3) and v2 (4)

k=4end=5.7

outDeg=2n = v2

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

{ v5, v2 }

Page 90: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=4end=5.7

outDeg=2n = v2

swapped v6 (3) and v2 (4)

k=3end=5.5

outDeg=2n = v6

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

{ v5, v2 }

Page 91: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=4end=5.7

outDeg=2n = v2

Now delete v2

k=3end=5.5

outDeg=2n = v6

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

{ v5, v2 }

Page 92: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=4end=5.7

outDeg=2n = v2

Deleted v2

k=3end=5.5

outDeg=2n = v6

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

{ v5, v2 }

Page 93: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=4end=5.7

outDeg=2n = v2

V2.outDeg > 0, so, not a sink, continueMin = tree.FindGreaterThan(v2.end)

k=3end=5.5

outDeg=2n = v6

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

{ v5, v2 }

Page 94: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=4end=5.7

outDeg=2n = v2

Min = tree.FindGreaterThan(v2.end)// 6 (v7) is greater than 5.7 (end of v2)

k=3end=5.5

outDeg=2n = v6

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

{ v5, v2 }

Page 95: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=4end=5.7

outDeg=2n = v2

Min = tree.FindGreaterThan(v2.end)// 6 (v7) is greater than 5.7 (end of v2)

k=3end=5.5

outDeg=2n = v6

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

{ v5, v2 }

Page 96: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=4end=5.7

outDeg=2n = v2

Add min to clique

k=3end=5.5

outDeg=2n = v6

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

{ v5, v2 }

Page 97: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=4end=5.7

outDeg=2n = v2

Add min to clique

k=3end=5.5

outDeg=2n = v6

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }

Page 98: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=4end=5.7

outDeg=2n = v2

To delete 6 (v7), we need to swap5 (v1) and 6 (v7)

k=3end=5.5

outDeg=2n = v6

K=5End=6.5

outDeg=1n = v1

K=6End=8

outDeg=0n = v7

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }

Page 99: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=4end=5.7

outDeg=2n = v2

Swapped 5 (v1) and 6 (v7)

k=3end=5.5

outDeg=2n = v6

K=6End=8

outDeg=0n = v7

K=5End=6.5

outDeg=1n = v1

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }

Page 100: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=4end=5.7

outDeg=2n = v2

delete 6 (v7)

k=3end=5.5

outDeg=2n = v6

K=6End=8

outDeg=0n = v7

K=5End=6.5

outDeg=1n = v1

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }

Page 101: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=1end=3.5

outDeg=4n = v5

k=2end=4.5

outDeg=3n = v3

k=4end=5.7

outDeg=2n = v2

V7.outDeg is 0, so, v7 is a sink. So, current clique is complete. Hiding deleted vertices andGoing to build next clique …

k=3end=5.5

outDeg=2n = v6

K=6End=8

outDeg=0n = v7

K=5End=6.5

outDeg=1n = v1

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }

Page 102: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=2end=4.5

outDeg=3n = v3

Min = tree.FindMin()We get 2 (v3)

k=3end=5.5

outDeg=2n = v6

K=5End=6.5

outDeg=1n = v1

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }

Page 103: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=2end=4.5

outDeg=3n = v3

Added 2 (v3) to cliqueNow delete 2 (v3)

k=3end=5.5

outDeg=2n = v6

K=5End=6.5

outDeg=1n = v1

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }{ v3 }

Page 104: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=2end=4.5

outDeg=3n = v3

deleted 2 (v3)Tree is now unbalanced in a right right case

k=3end=5.5

outDeg=2n = v6

K=5End=6.5

outDeg=1n = v1

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }{ v3 }

Page 105: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=2end=4.5

outDeg=3n = v3

Rebalancing using a left rotation

k=3end=5.5

outDeg=2n = v6

K=5End=6.5

outDeg=1n = v1

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }{ v3 }

Page 106: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=2end=4.5

outDeg=3n = v3

Rebalance using a left rotation

k=3end=5.5

outDeg=2n = v6

K=5End=6.5

outDeg=1n = v1

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }{ v3 }

Page 107: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=2end=4.5

outDeg=3n = v3

2 (v3) was not a sink, so continueTree.findGreaterThan(v3.end)// 5 (v1) is greater than 4.5 (end of v3)

k=3end=5.5

outDeg=2n = v6

K=5End=6.5

outDeg=1n = v1

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }{ v3 }

Page 108: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=2end=4.5

outDeg=3n = v3

Tree.findGreaterThan(v3.end)

// 5 (v1) is greater than 4.5 (end of v3)

Add v1 to clique

k=3end=5.5

outDeg=2n = v6

K=5End=6.5

outDeg=1n = v1

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }{ v3, v1 }

Page 109: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=2end=4.5

outDeg=3n = v3

Swap 3 (v6) and 5 (v1)

k=3end=5.5

outDeg=2n = v6

K=5End=6.5

outDeg=1n = v1

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }

{ v3, v1 }

Page 110: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=2end=4.5

outDeg=3n = v3

Swapped 3 (v6) and 5 (v1)

K=5End=6.5

outDeg=1n = v1

k=3end=5.5

outDeg=2n = v6

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }

{ v3, v1 }

Page 111: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=2end=4.5

outDeg=3n = v3

Now we can easily delete 5 (v1)

K=5End=6.5

outDeg=1n = v1

k=3end=5.5

outDeg=2n = v6

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }

{ v3, v1 }

Page 112: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=2end=4.5

outDeg=3n = v3

deleted 5 (v1)Min=tree.FindGreaterThan(v1.end)// 7 (v4) is greater than 6.5

K=5End=6.5

outDeg=1n = v1

k=3end=5.5

outDeg=2n = v6

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }

{ v3, v1 }

Page 113: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=2end=4.5

outDeg=3n = v3

v1 was not a sink, so we can continueAdd v4 to clique

K=5End=6.5

outDeg=1n = v1

k=3end=5.5

outDeg=2n = v6

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }

{ v3, v1, v4 }

Page 114: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=2end=4.5

outDeg=3n = v3

Delete v4

K=5End=6.5

outDeg=1n = v1

k=3end=5.5

outDeg=2n = v6

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }

{ v3, v1, v4 }

Page 115: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=2end=4.5

outDeg=3n = v3

Delete v4

K=5End=6.5

outDeg=1n = v1

k=3end=5.5

outDeg=2n = v6

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }

{ v3, v1, v4 }

Page 116: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=2end=4.5

outDeg=3n = v3

Deleted v4

K=5End=6.5

outDeg=1n = v1

k=3end=5.5

outDeg=2n = v6

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }

{ v3, v1, v4 }

Page 117: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

k=2end=4.5

outDeg=3n = v3

V4.outDeg was zero, hence currentclique is complete. Hiding deleted vertices for clarity

K=5End=6.5

outDeg=1n = v1

k=3end=5.5

outDeg=2n = v6

K=7End=9

outDeg=0n = v4

{ v5, v2, v7 }

{ v3, v1, v4 }

Page 118: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

Min=tree.findMin()// we get 3 (v6)Add to clique

k=3end=5.5

outDeg=2n = v6

{ v5, v2, v7 }

{ v3, v1, v4 }

{ v6 }

Page 119: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

delete 3 (v6)

k=3end=5.5

outDeg=2n = v6

{ v5, v2, v7 }

{ v3, v1, v4 }

{ v6 }

Page 120: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Step 3 - Details

• deleted 3 (v6)• Tree is now empty, so we stop and we are

done!• We have found 3 minimum cliques in our

clique cover!

{ v5, v2, v7 }

{ v3, v1, v4 }

{ v6 }

Page 121: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

Reference• Multi-Layer Channel Routine Complexity and Algorithms by

Rajat K. Pal• Graph theory and its applications to problems of society by

Fred S. Roberts• Introduction to Graph Theory by Douglas B. West• Slide 2 -> 3 is from teacher.buet.ac.bd/saidurrahman/cse6404• Slide 4 -> 5 from Mr. Jawaherul and 14 -> 47 from Mr. Emran• From en.wikipedia.org, Binary_search_tree, Tree_rotation,

Self-balancing_binary_search_tree• webpages.ull.es/users/jriera/Docencia/AVL/AVL%20tree

%20applet.htm

Page 122: Multi-Layer Channel Routing Complexity and Algorithms Rajat K. Pal Annajiat Alim Rasel 0409052002 annajiat@gmail.com CSE 6404 VLSI Layout Algorithms Page

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