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![Page 1: Multi-mode Average PWM Switch Models Missile Systems · Multi-mode Average PWM Switch Models Curtis Copeland Senior Architect Saber Users Group Forum April 7, 2016 Missile Systems](https://reader036.vdocuments.net/reader036/viewer/2022081406/5f1091bf7e708231d449c145/html5/thumbnails/1.jpg)
Copyright © 2016 Raytheon Company. All rights reserved.
Public Domain Information ITAR 120.11
Multi-mode Average PWM Switch Models
Curtis Copeland
Senior Architect
Saber Users Group Forum
April 7, 2016
Missile Systems
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Overview
Simulation Objectives
A simplistic approach to system modeling
Discussion of average models
An improved average model
Implementation example
Features and extensions
Future work
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Power System Simulation Objectives
Enable Successful System Integration– Non-recurring Engineering Cost
– Time to market
– Customer accountability
System Level Concerns– Inrush current
– Sequencing / Interdependence
– Power glitches / surges / brownouts / dropouts
– Bus stability
– Power budget
– Aggregate losses
Lower-level Concerns– Component stresses
– Converter stability
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A Simplistic Model:
The Arbitrary DC/DC Converter
Selectable behavior– Pass element ( Iin = Iout )
– DC transformer ( Vin * Iin = Vout * Iout )
Lumped loss models– Flat “efficiency”
– Overhead loss
– Conduction loss
“Infinite” bandwidth– No control loops
Limited large signal behavior emulation– Startup / Shutdown ramps
– Undervoltage lockout (UVLO)
– Enable input
Accelerates system analysis– Power budget
– Inrush current
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Average PWM Switch Modeling
Advantages of the method:– Computationally efficient
– Accurate small signal behavior
– Accurate large signal behavior
Challenges to Practical Simulations:– Large signal boundary conditions
Startup / shutdown / pre-bias
Overload / recovery
– Discontinuous derivatives
– Divide by zero errors
– Large, cascaded models
– Critical conduction boundary
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Average Switch Model
Branch QuantitiesQuantities may be inputs or outputs depending on topology being constructed i.e. Buck, Boost, Buck-Boost (inverting)
– VA: Voltage at Active Terminal
– VC: Voltage at Common Terminal
– VP: Voltage at Passive Terminal
– IA: Current into Active Terminal
– IC: Current out of Common Terminal (the average inductor current)
– IP: Current into Passive Terminal
– VSense: Voltage sensed at Inductor (inductor terminal opposite common terminal)
Duty– DA: Percentage of time that Active Terminal connects to Common Terminal
– DP: Percentage of time that Passive Terminal connects to Common Terminal
Ramp – Vramp: Voltage Ramp Amplitude (Input)
– HiSense: Current Mode Gain (sensing resistor multiplied by op-amp gain)
– Iramp: Current Ramp Amplitude (multiplied by HiSense to convert to a voltage)
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Canonical Topologies
L
COut
RLoadVOut
+
-
VIn
VSense
A
DA
DP
Cprivate
PC
Rdisconnect
ICIA
VC
VPVA
IP
average_pwm_sw
L
COut RLoad
VOut
+
-
VIn
VSense
A
DA
DP
Cprivate
PC
Rdisconnect
ICIA
VC
VPVA
IP
average_pwm_sw
L
COut
RLoad
VOut
+
-
VIn
VSense
A
DA
DP
Cprivate
PC
Rdisconnect
ICIA
VC
VPVA
IP
average_pwm_sw
BUCK
BOOST
BUCK-BOOST
BODY
DIODESCONDUCTION
ELEMENTS
Conduction losses can be modeled
Using diode models or resistors
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Pulse Width Modulation
A
IL
t
Iavg
Ipeak
Verror
ramp
rampv
ramp i
D T PD T
T
D TA P
IL
t
Iavg
rampv
Ipeak
Verror
ramp
D T
T
ramp i
CONTINUOUS DISCONTINUOUS
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Typical Application:
TPS40170 Eval Board
CONTROL LOOP
AVERAGE PWM SWITCH
SUPERVISOR
SWITCHING DEVICES
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Features
Topology-agnostic
Large Signal– Enable / Disable with proper behavior
– Isolated UVLO with hysteresis
– Ramped reference
– Tracking input
– Duty limits and blanking
– DC switching element loss models
Small Signal– Frequency response (ac)
– Slope compensation
– Current mode and/or voltage mode modulation
– Autonomous inductor conduction mode
– Frequency as a live input
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Behaviors Easily Implemented
Isolated topologies
“COMP” clamped soft start
Voltage tracking / margining
Feedforward
Current limit
Pre-bias mitigation
Pulse skipping / hiccup
Overcurrent
Internal references, regulators, delays, etc.
Frequency-dependent loss models
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Work to be done
Ridley peak current mode sampler
Average current modulator
Pulse skipping / hiccup / foldback
Non-trivial topologies: – Cuk, SEPIC
– Boundary conduction mode
– Variable frequency
– Resonant
– etc.
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References1. R. D. MIDDLEBROOK and S. CUK, “ A general Unified Approach to Modeling Switching Converter Power Stages ”, IEEE
PESC, 1976 Record, pp 18-34
2. Vatché VORPERIAN, “Simplified Analysis of PWM Converters Using The Model of The PWM Switch, Parts I (CCM) and II
(DCM) ”, Transactions on Aerospace and Electronics Systems, Vol. 26, N°3, May 1990
3. Basso, C, "A tutorial introduction to simulating current mode power stages," PCIM, October 1997.
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