multiplexers lecture l6.4 section 6.4. multiplexers a digital switch a 2-to-1 mux a 4-to-1 mux a...
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Multiplexers
Lecture L6.4
Section 6.4
Multiplexers
• A Digital Switch
• A 2-to-1 MUX
• A 4-to-1 MUX
• A Quad 2-to-1 MUX
• The ABEL when…then Statement
• TTL Multiplexer
Multiplexers
Y 4 x 1 MUX
s0s1
C0
C1
C2
C3
Y s1 s0
0 0 C00 1 C11 0 C21 1 C3
Multiplexers
Y
4 x 1 MUX
s0s1
C0
C1
C2
C3
Y s1 s0
0 0 C00 1 C11 0 C21 1 C3
0 0
A multiplexer is adigital switch
Multiplexers
Y
4 x 1 MUX
s0s1
C0
C1
C2
C3
Y s1 s0
0 0 C00 1 C11 0 C21 1 C3
0 1
Multiplexers
Y
4 x 1 MUX
s0s1
C0
C1
C2
C3
Y s1 s0
0 0 C00 1 C11 0 C21 1 C3
1 0
Multiplexers
Y
4 x 1 MUX
s0s1
C0
C1
C2
C3
Y s1 s0
0 0 C00 1 C11 0 C21 1 C3
1 1
A 2 x 1 MUX
2 x 1MUX
A
B
Z
s0
s0 Z
0 A
1 B
Z = A & !s0 # B & s0
A 4 x 1 MUX
2 x 1MUX
A
B
Z
s1
s0
2 x 1MUX
2 x 1MUX
s0
C0
C1
C2
C3
A = !s0 & C0 # s0 & C1 B = !s0 & C2 # s0 & C3 Z = !s1 & A # s1 & B
Z = !s1 & (!s0 & C0 # s0 & C1) # s1 & (!s0 & C2 # s0 & C3)
A 4 x 1 MUX
4 x 1MUX
C0
C3
Z
s1
s1 s0 Z
0 0 C0 0 1 C1 1 0 C2 1 1 C3
s0
C1
C2
Z = !s1 & (!s0 & C0 # s0 & C1)
# s1 & (!s0 & C2 # s0 & C3)
Z = !s1 & !s0 & C0 # !s1 & s0 & C1 # s1 & !s0 & C2 # s1 & s0 & C3
Y S
0 A 1 B
ProblemHow would you make a
Quad 2-to-1 MUX?
S
[A3..A0][B3..B0]
[Y3..Y0] Quad2-to-1MUX
mux.abl
MODULE Mux
TITLE 'Quad 2 to 1 Multiplexer, A. Student, 6/21/02'
DECLARATIONS
" INPUT PINS “
" OUTPUT PINS “
EQUATIONS
END Mux
S
[A3..0]
[B3..0][Y3..0]
Quad2-to-1MUX
mux.abl
MODULE Mux
TITLE 'Quad 2 to 1 Multiplexer'
DECLARATIONS
" INPUT PINS "
A3..A0 PIN 11,7,6,5;
A = [A3..A0];
B3..B0 PIN 4,3,2,1;
B = [B3..B0];
S PIN 10;
Switch S6(1..4)A input vector (4 bits)
Switch S7(1..4)B input vector (4 bits)
Push ButtonSelect Line
mux.abl (cont’d)
" OUTPUT PINS "
Y3..Y0 PIN 35,36,37,39 ISTYPE 'com';
Y = [Y3..Y0];
EQUATIONS
Y = A & !S # B & S;
END Mux
Output LEDs 9 – 12Output Vector Y (4 bits)
Logic Equation for the Multiplexer
Defines output
Mux Using Behavioral ABEL
0 0 0 C00 0 1 C10 1 0 C20 1 1 C31 0 0 C41 0 1 C51 1 0 C61 1 1 C7
s1 s1 s0 Z
8 x 1MUXC4
C7
Z
s2 s1
C5
C6
s0
C0
C3
C1
C2
Z = !s2 & !s1 & !s0 & C0 # !s2 & !s1 & s0 & C1 # !s2 & s1 & !s0 & C2 # !s2 & s1 & s0 & C3 # s2 & !s1 & !s0 & C0 # s2 & !s1 & s0 & C1 # s2 & s1 & !s0 & C2 # s2 & s1 & s0 & C3
MODULE mux81TITLE '8 to 1 Multiplexer' DECLARATIONS " INPUT PINS "C7..C0 PIN 11,7,6,5,4,3,2,1;C = [C7..C0];s2..s0 PIN 70,71,72;S = [s2..s0]; " OUTPUT PINS "Z PIN 35 ISTYPE 'com'; EQUATIONS when (S == 0) then Z = C0;when (S == 1) then Z = C1;when (S == 2) then Z = C2;when (S == 3) then Z = C3;when (S == 4) then Z = C4;when (S == 5) then Z = C5;when (S == 6) then Z = C6;when (S == 7) then Z = C7; @radix 16;test_vectors ([C,S] -> Z)[6,0] -> 0;[7,1] -> 1;[9,2] -> 0;[15,3] -> 0;[36,4] -> 1;[47,5] -> 0;[29,6] -> 0;[0A5,7] -> 1; END
mux81.abl
MODULE mux81TITLE '8 to 1 Multiplexer' DECLARATIONS " INPUT PINS "C7..C0 PIN 11,7,6,5,4,3,2,1;C = [C7..C0];s2..s0 PIN 70,71,72;S = [s2..s0]; " OUTPUT PINS "Z PIN 35 ISTYPE 'com';
EQUATIONS when (S == 0) then Z = C0;when (S == 1) then Z = C1;when (S == 2) then Z = C2;when (S == 3) then Z = C3;when (S == 4) then Z = C4;when (S == 5) then Z = C5;when (S == 6) then Z = C6;when (S == 7) then Z = C7;
@radix 16;test_vectors ([C,S] -> Z)[6,0] -> 0;[7,1] -> 1;[9,2] -> 0;[15,3] -> 0;[36,4] -> 1;[47,5] -> 0;[29,6] -> 0;[0A5,7] -> 1; END
Blif Simulation Report
8 to 1 Multiplexer C C C C C C C C s s s 7 6 5 4 3 2 1 0 2 1 0 Z V0001 0 0 0 0 0 1 1 0 0 0 0 LV0002 0 0 0 0 0 1 1 1 0 0 1 HV0003 0 0 0 0 1 0 0 1 0 1 0 LV0004 0 0 0 1 0 1 0 1 0 1 1 LV0005 0 0 1 1 0 1 1 0 1 0 0 HV0006 0 1 0 0 0 1 1 1 1 0 1 LV0007 0 0 1 0 1 0 0 1 1 1 0 LV0008 1 0 1 0 0 1 0 1 1 1 1 H 8 out of 8 vectors passed.
TTL Multiplexer1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
GND
Vcc 1G
B
1C3
1C2
1C1
1C0
1Y
2G
A
2C3
2C2
2C1
2C0
2Y
74LS153
X X X X X X 1 00 0 0 X X X 0 00 0 1 X X X 0 10 1 X 0 X X 0 00 1 X 1 X X 0 11 0 X X 0 X 0 01 0 X X 1 X 0 11 1 X X X 0 0 01 1 X X X 1 0 1
B A C0 C1 C2 C3 G Y
Dual 4-to-1-line multiplexer