nanochip vol9 iss1 final - applied materialsthe latest international technology roadmap for...

2 14 24

Beyond the smartphone:the next big thing

F a B s o L U t i o n s

Technology-Enabled Services for FastProblem Solving

Thick Epitaxial Silicon Enhances Performance of Power and MEMS Devices

APF FusionIntegrates Dispatch With Simulation

V9/ Issue 1 /2014

Solutions for Factory and Equipment Efficiency

30Bringing Existing Tools

to a New Level of Performance

20Beyond the Smartphone:

The Next Big Thing

CONTENTS

7 Increasing Endura PVD Capabilities for Thick Al and AlN

14CASE STUDY:APF Fusion Integrates Dispatch With Simulation

PLUS:33: At Your Service – An Interview With Seehack Foo36: Changing the Economics of Solar Cell Manufacturing41: The Last Word

F A B S O L U T I O N S

E X E C U T I V E P U B L I S H E RDana Tribula

[email protected]

P U B L I S H E RPeggy Marcucci

[email protected]

E D I T O R - I N - C H I E FLiz Baird

[email protected]

C O N T R I B U T I N G E D I T O R SGary DagastineDavid Lammers

Jill O’Nan

D E S I G NJane Olson Graphic Design

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NANOCHIPF A B S O L U T I O N S

24Thick Epitaxial Silicon Enhances Performance of Power and MEMS Devices

Building Customer

Satisfaction

7

2 Technology-Enabled Services for FastProblem Solving

18

NANOCHIP 1

These days the semiconductor industry is abuzz with speculation about the “next big thing” to follow smartphones and tablets. Will it be one new groundbreaking technology or waves of innovation across multiple markets? Will it be tied to the Internet of Things (IoT) or will a wild card product emerge from the deck?

This issue of Nanochip Fab Solutions o¥ ers an intriguing investigation into the technology path to the next big thing, with insights from market watchers and industry insiders.

While it’s exciting to ponder what changes the next big thing may bring, there are some aspects of our business that aren’t likely to change at all. For example, our customers will always need service o¥ erings that help make them more productive, e¦ cient and profi table, which means that Applied Materials will continue to deliver on its value proposition: higher device performance and yield at lower cost.

In this edition you’ll learn how Applied is continuously evolving services and spares o¥ erings designed to resolve your most challenging problems at every stage of the product life cycle. You’ll meet Seehack Foo, the new vice president of Applied Global Services’ Semiconductor Service and Components business unit, and read about the technology-specifi c service business units we have established to collaborate with their corresponding tool development teams.

You’ll read about new technology-enabled service o¥ erings that can help solve your highest value problems. The article details work by our Advanced Services team to predict epi lamp failure 5 days in advance with 90% accuracy, signifi cantly reducing unscheduled downtime.

Another article introduces our Global Continuous Improvement team, which is driving greater customer satisfaction and improved business results through sustained improvements in speed, quality and cost. In one case, by analyzing our service performance, we achieved >50% reduction in resolution of long-duration particle events, helping customers achieve their production goals faster.

New hardware solutions are also featured prominently. Applied has developed a hardware upgrade kit to enhance the thick silicon epi fi lm capabilities of the 200mm Centura Epi platform. This single-chamber, single-vendor capability is unique in the industry, and can help you reduce costs and complexity. To serve customers in the 200mm power devices and MEMS segments, Applied’s 200mm Endura PVD chamber has been enhanced to deliver a competitive, state-of-the-art, single-chamber and cluster solution for thick Al and AlN that meet volume-production throughput targets.

There are new Applied software solutions as well. You’ll read how Seagate used APF Fusion, the latest addition to Applied Materials’ Advanced Productivity Family (APF) software suite, to integrate a real-time dispatching (RTD) rule into simulation, validate its e¥ ects on key performance indicators, and save $100,000 in labor costs alone!

As the semiconductor manufacturing process grows increasingly complex, so do the needs of our customers. We understand that, and are constantly adding depth to our service o¥ erings so we can tackle your highest value problems quickly and cost-e¥ ectively—no matter what the next big thing is.

CHARLIE PAPPISGROUP VICE PRESIDENT

AND GENERAL MANAGER,APPLIED GLOBAL SERVICES

THE NEXT BIG THING:WE’RE READY FOR IT

A Letter from Charlie Pappis

nanOCHiP2

BYJames moYne,

PaRRis haWKins, JimmY isKanDaR

anD miChaeL aRmaCost

Manufacturing automation, specialized expertise and close collaboration combine to improve product, process and equipment performance.

TECHNOLOGY-ENABLED SERVICESfor fast ProBleM solVing

NANOCHIP 3

service agreement, they are designed specifi cally to help customers resolve their toughest production challenges—those with the greatest impact on device performance and yield—faster and more cost-e¥ ectively.

TOUGH CHALLENGE. ADVANCED SOLUTION.

The example below illustrates various aspects of Applied’s new technology-enabled services approach, in which technical experts using cutting-edge technologies—including predictive maintenance (PdM), virtual metrology (VM), run-to-run (R2R) control and equipment health monitoring (EHM)—work together to uncover problems and suggest solutions. The resulting benefi ts for contract customers include (1) integration of technologies, (2) incorporation of tool, process and automation technology domain knowledge, (3) delivery of collaborative support service, and (4) solution implementation as part of a continuous improvement process.

THE PROBLEM: REDUCE DOWNTIME FROM EPI LAMP FAILURE

In many fab lines epi process availability is critical. Overall availability, consistent availability and predictable availibility are all important factors. Therefore, it is important to minimize process mean-time-between-interrupts (MTBI) and mean-time-to-repair (MTTR), and also be able to predict with some lead time when a repair might be needed. Lamps are a common source of failure in epi and, as shown in fi gure 1, there are a number of mechanisms that cause them to fail. These failure modes are generally di¦ cult to anticipate until a sharp drop in resistance occurs right before failure. This results in a signifi cant amount of unexpected downtime and undesirable variability in downtime. After a failure and subsequent lamp kit replacement, “tuning” is required as part of the maintenance recovery process. Test wafers are processed and measured, and the process is adjusted based on the results.

The migration toward more advanced semiconductor device nodes (< 28nm), with stringent requirements for acceptable device performance, yield and productivity levels, is forcing the nanomanufacturing community to think di¥ erently. Manufacturing automation technology suppliers and their device-producer users are recognizing the technological and economic advantages of broader, deeper collaboration throughout the life cycle of production tools.

The latest International Technology Roadmap for Semiconductors (ITRS) Factory Integration (FI) chapter echoes this trend as follows:

The rapid increase in FI requirements (e.g., Big Data) and capabilities (e.g., predic-tion) in recent years has led to a change in the approach to implementing and maintaining FI capabilities. Development and maintenance of emerg-ing capabilities such as PdM (predictive maintenance), VM (virtual metrology), waste management, and utilities management incorporation into fab objectives, requires intimate knowledge of the fab objectives, process, equipment and the capabilities them-selves.[1]

Applied Materials has recognized this need, and is responding with a new class of integrated, advanced customer service solutions. These solutions combine Applied’s innovative manufacturing automation software with specialized expertise and extensive equipment and process domain knowledge. Delivered as service solution options for customers covered by an Applied

Short circuitbetween turns

Short circuitbetween filament helixand support pillar

Filament sagging below center line

Figure 1. Common epi lamp failure mechanisms.

TECHNOLOGY-ENABLED SERVICES

NANOCHIP4

The process is deemed production-ready when the test wafer measurements meet specifi ed quality criteria. This tuning process can often be costly, both in terms of high MTTR and highly variable MTTR, not to mention the cost of test wafers and metrology. The process of tuning can be rather ad hoc with adjustments determined manually and often in a univariate (one-by-one) fashion.

PdM technology uses process- and equipment-state information to predict when a tool or a particular component in a tool may need maintenance. This prediction data is then used as information to improve maintenance capabilities, such as avoiding unscheduled downtime. PdM technology-enabled services can be used to predict lamp failure, thereby

Applied Materials PdM Capability Overview

Historical tool data

Schedule maintenance via MMS system

Data acquisition

Tool performance reporting

Predictive models on target events

Configurable strategies apply prediction models to real-time tool data to

determine when maintenance will be needed and when/how to react

Equipment state, context, metrology, and maintenance

history data

PageEmail

TXT file

Technology-enabled services solution deploying

prediction models

O�ine prediction model construction

Real-time tool data

O�ine

Online model implementation for predictionOnline

Notifications

PdM

ACT

ION

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Figure 2. Applied Materials’ integrated PdM solution.

particular customer application. These specialists not only develop the optimized maintenance event prediction models, but also provide analysis utilizing the model prediction quality and customer objectives to inform the customer of the expected benefi t of model application before the model is deployed.

Once the model is developed o ́ ine, it is brought online through integration into the existing fab automation infrastructure, minimizing integration costs. As shown at the bottom of fi gure 2, confi gurable execution strategies allow the prediction model to be “eased” into fab operations, fi rst as an indication-only capability, and later as an actual control capability interfaced to the maintenance management system once the user has su¦ cient confi dence in the prediction capability.

The online component also includes a capability for model updating as necessary, and online PdM data analysis by the user or Advanced Services experts. The latter capability is illustrated in fi gure 3. Here a particular prediction

reducing unscheduled downtime and improving MTBI and MTTR.

Applied’s PdM solution, shown in fi gure 2, was developed over two years, with research into PdM techniques in nanomanufacturing and other industries. It includes an o ́ ine component for PdM model development and optimization, and an online component for model integration, execution and updating. The o ́ ine component uses historical data to develop maintenance event prediction models that are optimized to customer objectives. This is achieved with a comprehensive set of tools that provide capabilities for data merging (generally fault detection [FD], metrology and maintenance data), data quality strengthening, automatic and manual (graphical) data manipulation, key parameter identifi cation, model building, model assessment, and model optimization to customer objectives.

Advanced Services specialists use these technology tools to consult with both Applied and customer tool- and process experts so that the solutions are optimized to a

TECHNOLOGY-ENABLED SERVICESFOR FAST PROBLEM SOLVING

NANOCHIP 5

event can be further investigated by highlighting an area of interest, utilizing embedded software analysis to determine the primary sensors contributing to the event and viewing the wafer-by-wafer data traces of the individual sensors.

REDUCING MTTR WITH VM AND R2R CONTROL

As noted above, lamp replacement maintenance recovery can be time-consuming as there are usually multiple iterations of lamp parameter “tuning” that include running a number of test wafers with specifi c characterization recipes, analyzing metrology data, and making hardware and software adjustments. This process continues until the metrology data meets specifi ed quality criteria. Four to ten iterations of this type are not uncommon, leading to MTTR on the order of two days or more.

Advanced Services experts apply R2R control and VM1 capabilities in this situation as shown in fi gure 4a [5]. Specifi cally, they develop lamp-qualifi cation tuning models

using specialized software applied to historical test wafer process metrology and associated process FD output data. VM techniques are used to predict the test wafer metrology values, and multivariate R2R control techniques are used to determine what lamp tuning adjustments can be made simulatenously to bring the metrology values within acceptable limits, thereby completing the lamp-tuning process. When a lamp replacement event occurs, these models are re-centered using the data from the fi rst lamp-tuning iteration, and then applied during the second iteration to provide tuning recommendations in a multivariate fashion. The result is that fewer tuning iterations are required to bring the chamber to a satisfactory matched state for release back into production, as illustrated with the conceptual diagram of fi gure 4b.

REDUCING UNSCHEDULED DOWNTIME AND MTTR WITH EHM

EHM is a technology that monitors tool parameters to assess

Automatically detect tool state change

PdM model signal data with points selected

Pareto chart based on multivariate analysis

Single sensor trace depicting selected wafers

1

Select wafers ofinterest (pointsin red)

2

Drill down to a selected sensor’s values by wafer

4

Drill down to the weighting of contributing sensors

3

Use this information along with domain expertise to determine tool maintenance requirements and analyze tool health

5

Figure 3. Online PdM monitoring and analysis capability.

Figure 4. Example of R2R control and VM applied during maintenance recovery to reduce tuning iterations and MTTR. 4a: Mechanism utilized to provide PM recommendations. 4b: Conceptual diagram illustrating the impact of this R2R control approach in reducing tuning iterations and MTTR.

1 VM enables prediction of post-process metrology variables using process- and wafer-state information such as FD outputs [4].

Lamp PMadjustment

recommendationsPM processFD outputs

PM processmetrology

MVA R2R control and/or VM

MTTR Reduction

Tuning Iterations

Test

Waf

er Q

ualit

y (N

orm

aliz

ed)

Leve

l of M

etro

logy

Mat

ch to

Spe

cific

atio

n 1.0

0.8

0.6

0.4

0.2

Example: Lamp ReplacementDuring Thermal Processing (Improved)

1 2 3 4 5

Chamber BChamber A

Chamber A Before

Chamber A After

Chamber B Before

Chamber B After

(4a)

(4b)

NANOCHIP6

tool health as a function of deviation from normal behavior. Advanced Services specialists leverage multivariate EHM throughout the production and maintenance cycle in concert with PdM, VM and R2R control as shown in fi gure 5.

During production it is used to monitor overall tool health as well as the health of specifi c target components. During the maintenance process EHM is used to provide multivariate “fi ngerprints” that help assess whether a particular maintenance procedure has been successful. In the case of lamp failure, EHM monitors the health of the tool and lamp during production, and provides information on the quality of the lamp-replacement procedure during maintenance.

GETTING RESULTS: CUSTOMER PROBLEMS SOLVED

These technology-enabled service solutions from Applied Materials are adaptable to all our process tools and available as options to customers participating in Applied service agreements. They can help customers resolve di¦ cult problems

MTBI

PRODUCTION MAINTENANCE SEASONING RE-QUAL PRODUCTION

EHM used to monitor tool health during production

R2R control and VM process tuning

PDM used to predict (scheduled or unscheduled) maintenance, extend MTBI

R2R control and/or reverse VM used to determine maintenance settings/adjustments

EHM, VM, and metrology used to determine if maintenance is satisfactory

EHM used to determine if ready to move to re-qual

EHM helps determine when ready for production

Best Practices

MTTR MTBI

Figure 5. Utilizing Applied Materials technology-enabled services through the maintenance cycle.

faster and save money by utilizing a number of technologies collectively to provide maximum benefi t.

For example, fi gure 5 illustrates the use of these services throughout the maintenance cycle to reduce MTBI and MTTR. They also include continuous improvement mechanisms that provide feedback that can be factored into best practices, process- and equipment-operation design, and other automation capabilities such as maintenance and FD, delivering benefi ts that extend beyond the initial solution of a problem.

The type and level of benefi t depends, of course, on individual customer needs and the agreed roadmap for deployment of technology-enabled services. In the epi lamp-replacement example, application of PdM services resulted in the ability to predict lamp failure 5 days in advance with 90% accuracy. Further application of VM and R2R control to lamp MTTR would reduce the tuning time by an average of two iterations or more.

With a toolkit of advanced and proven analysis technologies customized to nanomanufacturing applications, including PdM, VM, EHM and chamber-matching options, Applied can address our contract customers’ most urgent issues quickly on multiple fronts, providing rapid and signifi cant benefi ts. Further,

we can incorporate these solutions into a continuous improvement process that will allow customers to utilize technology-enabled services to optimize equipment and process confi gurations and resolve di¦ cult problems e¦ ciently.

For additional information, contact [email protected] or [email protected].

[1] 2013 International Technology Roadmap for Semiconductors (ITRS): Factory Integration Chapter, available at www.itrs.net.

[2] J. Moyne, J. Iskandar, P. Hawkins, T. Walker, A. Furest and B. Pollard, D. Stark and G. Crispieri, “Deploying an Equipment Health Monitoring Dashboard and Assessing Predictive Maintenance,” Proceedings of the 24th Annual Advanced Semiconductor Manufacturing Conference (ASMC 2013), Saratoga Springs, New York (May 2013).

[3] J. Moyne, “Method and apparatus for opti-mizing profi t in predictive systems,” United States Patent Application (fi led February 2014).

[4] A. Khan, J. Moyne and D. Tilbury, “Fab-wide Control Utilizing Virtual Metrology,” (invited) IEEE Trans. on Semiconductor Manufacturing-Special Issue on Advanced Process Control, Nov. 2007, pp. 364-375.

[5] Proceedings of the 25th Annual Advanced Semiconductor Manufacturing Conference (ASMC 2014), Saratoga Springs, New York (May 2014). See also: “Improving Yield with Fleet Chamber Matching,” NanoChip Fab Solutions, Vol. 8, No. 2, 2013.

[6] J. Zou, “Minimizing Pilot Runs with Non-Threaded Control Technology,” Applied E3 User’s Conference, Phoenix, Arizona (February 2014).

tool health as a function of deviation from normal behavior. Advanced Services specialists leverage multivariate EHM throughout the production and maintenance cycle in concert with PdM, VM and R2R control as shown in fi gure 5.

to monitor overall tool health

TECHNOLOGY-ENABLED SERVICESFOR FAST PROBLEM SOLVING

NANOCHIP 7

FOR THICK Al AND AlN

INCREASING ENDURA PVD CAPABILITIES

Exponential growth in demand for wireless products, combined with their increasing functionality and power management requirements, is driving greater use and ongoing development of physical vapor deposition (PVD) processes in their fabrication.

BYMIKE ROSA, PHD

While CMOS is evolving toward ever smaller devices and thinner fi lm layers—now measured at the atomic scale in leading-edge devices—features and thicknesses typical of the growing class of emerging

technologies in the power, MEMS, and analog market seg-ments are comparatively large. Depending on the application, thick fi lms (≥5µm) or relatively thinner ones (50nm–2.5µm) can be required.

NANOCHIP8

dissipation. Power devices are used as switches or rectifi ers in power electronics and include di-odes, power MOSFETs, thyristors, and insulated gate bipolar transis-tors (IGBTs). Expected to be the largest contributor to the growing power device market in the next fi ve years,[1] the IGBT is present in many everyday products: variable speed motors, air conditioners, stereo systems with switching amplifi ers, trains, and electric cars. Their speed is beginning to rival that of MOSFETs, and they exhibit excellent ruggedness at higher power loads.[2]

By comparison, thinner layers of materials such as AlN are used as acoustic modulators in RF fi lter applications and used for their piezoelectric proper-ties in a variety of MEMS-based sensors and actuators. Over the years AlN has enabled smart-phones and tablets to remain compact and lightweight, while becoming more multifunctional and accommodating di¥ erent service frequencies around the world.

A key driver of this trend is the 4G and long-term evolution (LTE) cellular network technol-ogy that makes possible faster data download and improved user interaction with the mobile Internet. AlN is a vital performance enabler in the fabrication of the bulk acoustic resonator (BAW) mechanism on which these technologies rely. Consequently, AlN has attracted

Production of this class of devices is readily accommo-dated on 200mm equipment, spurring Applied Materials’ renewed focus and increased investment in 200mm technol-ogy development. The goal is to improve upon existing capabilities and address the unique fabrication challenges of MEMS, power devices, wafer-level packaging, through-silicon vias, analog devices, and CMOS image sensors. This includes a broadened concentration on

advanced fi lms for a range of applications that include PVD of metals, compound metals and semiconductor materials.

In this article, we address recent developments in thick aluminum (Al) deposition for power device applications and thinner aluminum nitride (AlN) deposition for RF fi lter applica-tions commonly used in today’s multifrequency cell phone technologies—both delivered on the Applied Materials Endura 200mm platform. Leveraging

the production-worthiness and proven reliability of Applied’s En-dura technology, these advances provide state-of-the-art, single-chamber and cluster tool-based solutions for thick Al and AlN that exceed current industry ca-pabilities for volume-production throughput and fi lm quality.

Increasingly, power device designs centered on reduced device footprint, high-power ap-plications, or both, employ thick Al layers to switch high-current loads or act as paths for thermal

pn field stop

nsub

psub

p

n

HV NMOS HV PMOS C G

E

Al Plug Al PlugAl Plug Al Plug

Source Drain Source Drain

GateGate

n-well n-well p-drain extension

Figure 1. Thick layers of Al are used in (a) high-voltage transistors and (b) IGBT power devices.

Table 1. Thick Al requirements vs. process performance.



(a) (b)

PROCESS PERFORMANCE PARAMETER TARGET REQUIREMENT CURRENT PERFORMANCE

Refl ectivity relative to Al for Al 0.5%Cu >85% @ 200°C AlCu 85%,

(AlCu avg. @ 436nm and 480nm) >75% @ 400°C AlCuSi 75%

Sheet Resistance (Rs) ≤ 6 mΩ/sq 6 mΩ/sq

Thickness Uniformity–Within Wafer (WiW) / WtW <1.7%,1σ / 1.7%,1σ 1% / 0.15%

Sheet Resistance Uniformity (Rs) - WiW / WtW <1.7%,1σ / 1.7%,1σ 1% / 0.15%

Density In-Film Particle (≥0.3mm) 0.08 particles/cm2 0.013 p/cm2

Extrusions None None

Stress <2000 MPa, tensile ~200 MPa

Deposition Rate >1.75 µ/min >2.3 µm/min

Throughput - 3 Chambers > 50 wph (3µm)/ 50 wph (3mm) >40 wph (6µm)

NANOCHIP 9

nonuniformity of dopant ions. At lower temperatures, grain sizes will be smaller, with signifi cantly shallower or nonexistent groov-ing creating more consistent dopant ion concentrations and hence a more uniform and consistent Rs. Because grain sizes are smaller, more boundaries exist where dopant ions can reside. This more even distribution results in a more uniform resistance, which in turn alleviates conditions favoring EM under higher current loads.

Consequently, the funda-mental hardware challenge is to keep the chamber and wafer cool enough to allow for productivity-enhancing single-step deposition of a layer at least 5µm thick—preferably thicker. Currently, OEM competitor sys-tems rely on multiple chambers to carry out fi lm depositions as a means of managing the heat buildup from the deposition process. In such systems, wafers are transferred through a series of multiple chambers, each depositing some portion of the required thickness.

IMPROVEMENTS

A number of carefully planned hardware modifi -cations to the standard Al deposition chamber compat-ible with the 200mm Applied Endura PVD platform have produced industry-leading improvements in fi lm quality and process productivity.

particular interest in recent years because it demonstrates the best balance of performance, manufacturability, and reliability for such use.[3]

BAW resonator devices enable precise fi ltering of the RF signals received from cell phone base stations by mobile phones. With a growing number of signals being received by smartphones (e.g., cell, Wi-Fi, GPS) and the crowding of available frequen-cies worldwide by multitudes of services, these fi lters must be exceptionally frequency-selective to avoid slowdowns or interrup-tions in operation. BAW devices also o¥ er the advantages of high power-load handling, compat-ibility with small form factors, and relatively easy fabrication using existing CMOS-compatible technologies.

THICK ALUMINUM PROCESS DEVELOPMENT

Figure 1 illustrates examples of the power device structures that incorporate thick layers of Al. Their use ranges from plug-fi ll applications, thick layers for high current-carrying capability

or high thermal-load tolerance, to back-side metallization of the wafer for thermal and electrical conductivity. At present, these layers are typically 3–7µm thick, although work continues on developing the means of depositing layers 11µm or more thick.

DEVELOPMENT CHALLENGES

Table 1 lists target require-ments for the thick Al applica-tion. Chamber temperature control is the crux of optimizing thick Al deposition to meet these requirements. Productiv-ity demands high throughput; high deposition rates (ide-ally >2µm/min) are therefore needed to grow the thick layers in as short a time as possible. However, the sputtering energy generated in achieving a high deposition rate builds up heat in the chamber. Elevated tem-peratures degrade fi lm quality by creating thermal grooving (elastic deformation at grain boundaries), “whisker” growth, and hillock formation (see fi gure 2). Grooving adversely a¥ ects the fi lm’s refl ectivity

and sheet resistance, which are important for subsequent lithography steps and overall fi lm conductivity, respectively (and also an indicative measure of overall grain size and surface roughness). Overheating causes other issues, such as fl aking and higher particle counts.

Grain size control—another challenge—is important in limit-ing hillock formation. Gener-ally, the higher the deposition temperature the larger the grain size (and the deeper the groove) formed during the deposition of the Al fi lm. While most planar Al fi lms are deposited at or slightly below 200°C, some plug-fi ll ap-plications require temperatures in the range of 380–450°C. The main consideration is the possible occurrence of electro-migration (EM) in the presence of larger grain sizes under condi-tions of higher current densities. This is predominately due to the concentration of a small percentage of Cu or Si in the Al fi lm along the grain boundaries, within the grooves between the grains. High current conditions may favor EM of ions between the Al grains due to the potential

Figure 2. Overheating and fi lm stress can produce defects such as (a) grooving, (b) “whisker” growth, and (c) hillock formation.

(b)(a) (c)

NANOCHIP10

kit while dissipating the heat load from the higher source power. Hot spots have been eliminated by equipping the electrostatic chuck with wafer lift pins instead of clamps and improving chuck temperature control.

The process kit has also been redesigned specifi cally for thick deposition processes. A higher deposition ring accommodates a greater depth of Al, while a wider cover ring o¥ ers better protection if metal fl akes o¥ chamber surfaces onto the wafer.

Key among these is resolu-tion of chamber heat loading and hot spots on the wafer. The former has been real-ized by upgrading the DC power supply to 40 kW and improving source-target- and process kit cooling. Edge-feed source cooling has been replaced by a more e¥ ective center-fed, forced-cooling approach. The process, which was previously not actively cooled, now benefi ts from a water-cooled adapter that helps stabilize the temperature of the process



Figure 4. Results from a 1000-wafer marathon using an AlCu (0.5%) target at 40 kW and 400°C show good results for 5.1µm thick fi lm.

Resistance and Rs Nonuniformity

Wafer Number0 100 200 300 400 500 600 700 800 900 1000

Rs (O

hm/s

q)

Rs N

on-U

(%)

8.00E-03

7.00E-03

6.00E-03

5.00E-03

4.00E-03

3.00E-03

5.00%

4.00%

3.00%

2.00%

1.00%

.000%

Resistance (Ohm/sq)Rs Non-Uniformity (%)

Stress and Thickness

Wafer Number0 100 200 300 400 500 600 700 800 900 1000

Thic

knes

s (Å

)

Stre

ss (M

pa)52000

50000

48000

46000

44000

100

80

60

40

Thickness (Å)Stress (Mpa)

Reflectivity and Ref Nonuniformity

Wafer Number0 100 200 300 400 500 600 700 800 900 1000

Ref (

%)

Ref N

on-U

(%)

90

85

80

75

70

65

60

35.00%

30.00%

25.00%

20.00%

15.00%

.1000%

5.00%

0.00%

Ref (%)Ref Std (%)

Target Life vs. Dep Rate

Wafer Number0 200 400 600 800 1000

Targ

et L

ife (k

Wh)

Dep

Rat

e (Å

/min

)

1200

1000

800

600

400

200

0

35000300002500020000150001000050000

Target Life (kWh)Dep Rate (Å/min)

Figure 3. (a) Top-down SEMs and (b) high-magnifi cation close-ups illustrate grain-size modifi cation made possible by tuning process temperature.

(a)(a) (b)

350°C

175°C Grain boundaries not visible

400°C

RESULTS

The above modifi cations have created a substantially new Al deposition chamber designed to address the needs

of the power device market: the high deposition rate (HDR) chamber. The HDR chamber is an Endura-based production-worthy process chamber for

NANOCHIP 11

material to orient in this manner. Recent studies have shown that this orientation can be further promoted by creating as smooth a substrate surface as possible on which to deposit the seed AlN between the substrate and the electrode underlying the AlN.[5]

Orientation within the seed layer infl uences that in the electrode, which in turn a¥ ects orientation in the AlN.

Second, AlN possesses a high quality factor (Q), i.e., it can store the maximum acoustic energy within the fi lter structure. In other words, the oscillations of the acoustic wave decay very slowly. This attribute enhances the signal clarity and strength of a given BAW device. The resonance frequency of a BAW device is inversely proportional to the thickness of the AlN layer and the electrodes above and below it, which makes them ideal for the most demanding 3G and 4G applications.[7] The thinner the electrode/AlN “sandwich,” the higher the frequency. This relationship means that AlN uniformity is extremely important

Stress Field of Acoustic Wave

~2µm

Top Electrode (Ti, Mo)Piezo Layer (AiN)Bottom Electrode

Acoustic Mirror

Substrate

Stress Field of Acoustic Wave

Top Electrode (Ti, Mo)Piezo Layer (AiN)Bottom Electrode

Substrate

Support Layer

Air Cavity / Vacuum Gap

Figure 5. (a) The SMR sits on top of refl ecting layers that limit loss of acoustic energy into the substrate. (b) In the FBAR, a cavity is etched beneath the active area, creating a suspended membrane.

thick Al deposition, as shown by the current performance results summarized in table 1 and illustrated in fi gures 3 and 4. The circled area in the top graph of fi gure 4 refl ects a “spacing matrix qualifi cation” performed at 600 wafers, approximately mid-target life for the process, which also a¥ ected the thick-ness for a given sputter time. In future, appropriate compensa-tion will apply throughout the target life to deliver a consistent thickness.

Already proven in the fi eld for layers up to 6µm, the high-productivity process ( >2.3µm/min) doubles the output of a standard Al deposition chamber, thus reducing the cost of opera-tion, and produces exceptionally uniform fi lms that exhibit no whiskers or hillocks. Enhancing production fl exibility, the cham-ber’s operating temperature range accommodates processes suitable to a variety of Al alloys.

AlN DEVELOPMENT

BAW fi lter structures are typically fabricated as either

a solidly mounted resonator (SMR) or thin fi lm bulk acoustic resonator (FBAR) devices, both of which are compatible with existing CMOS fabrication technologies (see fi gure 5). At present, most manufacturers construct them as SMRs, which are easier to implement. In an SMR, the BAW is fabricated on a Bragg refl ector stack consisting of alternating pairs of high and low acoustic-impedance materi-als that limit acoustic losses.[4] The air-gap approach, in which the cavity acts as the refl ector, is currently implemented only in leading-edge applications.

ADVANTAGES OF AlN

AlN exhibits several properties desirable in a BAW device. First, AlN has the requisite high degree of c-axis (002) crystal orientation ideal for achieving the highest piezoelectric constant and electroacoustic coupling.[5,6] Depositing the fi lm by reactive, pulsed DC sputtering of pure Al targets in a nitrogen atmosphere predisposes the

to device performance repeatability.

Lastly, AlN is stable, mechanically very strong, and possesses high thermal conductivity, which also enhances the power-handling capability of the device.[8]

DEVELOPMENT CHALLENGES

BAW structures are challenging to fabricate for several reasons. Crystal texture and fi lm deposition uniformity are the key requirements. Crystal texture is crucial for optimizing the piezoelectric behavior of the AlN. Here it is signifi cant that the quality of the silicon substrate directly infl uences the properties of the as-deposited AlN fi lm.[5] Recent studies have demonstrated the importance of both deposition rate and surface roughness of the substrate in achieving the desired AlN crystal texture. Films that grow more slowly (e.g., SiH4 oxide) generally produce better surface quality than thermal oxide.

(a) (b)

NANOCHIP12

However, experiments have shown that even slow-growing fi lms require subsequent planarization to achieve the desired crystallinity improvement. As noted above, the smoother the underlayer, the better the crystal orientation of the seeding layer between the substrate and the lower electrode, and of the piezoelectric layer itself.

Deposition uniformity must be virtually perfect given the relationship of resonance frequency to thickness of the electrode/AlN “sandwich.” The target for within-wafer uniformity on a 150mm or 200mm wafer is an exceptionally demanding 0.5% or less.[9]

In addition, volume production of such applica-tions requires high deposition rates while maintaining AlN fi lm stress at neutral or slightly compressive (-200-0 MPa),[10,11] particularly in FBAR structures, which can otherwise be fatally

distorted. Furthermore, it has been shown that in-fi lm stress produces a shift in the frequency response of the AlN fi lm; the natural frequency of the AlN FBAR devices exhibits a lesser shift when stress values trend toward neutral or tensile values. This e¥ ect, in addition to greater fi lm thickness, results in a less sensitive fi lm across the wafer.

Avoiding dopant redistribution and other damage to underlying CMOS layers is another critical consideration that requires post-CMOS processing be performed at temperatures lower than 450°C.[12] Given that AlN deposition quality improves at higher temperatures, this limitation imposes somewhat of a trade-o¥ on process optimization for integrated SMRs, although stand-alone devices could benefi t and then be hybrid-integrated into dual IC packages.

PROCESS IMPROVEMENTS

Because deposition uniformity is of paramount importance, Applied’s hardware improvement programs focused on redesigning the magnetron to achieve full-face target erosion with a rotating magnet. Four magnet designs were tested with various nitrogen-to-argon ratios in the gas fl ow. Investigations revealed that some designs delivered less actual power than requested power during sputtering, especially at lower nitrogen-to-argon ratios.[13]

Experiments also showed that higher nitrogen-to-argon ratios produced higher compressive stress levels in the fi lm. These resulted from bombardment by high-energy neutrals formed when lightweight nitrogen ions bounced o¥ the target, were neutralized, and made contact with the AlN with most of their initial energy retained.

These observations infl uenced magnet design optimization. Considerable process tuning was then required to refi ne performance and optimize the synergy of all parameters. For example, nitrogen-to-argon ratios had to be tuned so that the greater ionization potential and lighter weight of nitrogen

did not unduly reduce sputtering e¦ ciency. Also, high DC power levels—ideal for higher deposition rates—increased fi lm nonuniformity under certain conditions, necessitating compensatory adjustments to other parameters.

RESULTS

Table 2 summarizes the Applied Endura PVD chamber’s performance on 200mm wafers relative to key requirements for AlN deposition in SMRs. Figure 6 illustrates the excellent crystalline alignment of the AlN and molybdenum (Mo) electrode that optimizes the piezoelectric behavior of the AlN, while fi gure 7 highlights deposition rate and within-wafer (WiW) nonuniformity that both meet requirements.

It is noteworthy that, unlike available competitive systems, the Endura system’s exceptionally low nonuniformity is achieved without post-deposition trimming. The system further di¥ erentiates itself by producing high-quality AlN fi lm at temperatures as low as 200°C, which, as noted earlier, is essential in fabricating CMOS-integrated or FBAR devices suspended above sacrifi cial materials that can be damaged at higher temperatures.



Table 2. AIN process performance.

TARGET PARAMETERS REQUIREMENT ACTUAL

WIW Uniformity (6” / 8”) < 0.5% / <1.0% <<0.5%

Thickness 800nm – 2.5 µm Tunable

Deposition Rate > 75 nm/min > 75 nm/min

FWHM Rocking Curve ≤ 1.65 ≤ 1.3

Maximum Temperature 450 °C 200 °C – 400°C

Stress < “ 100 MPa Tunable “ 500MPa

Refractive Index 2.08 – 0.2 ~ 2.07

Surface Roughness < 2.5nm ~ 1.0nm

Deposition Rate > 75 nm/min > 75 nm/minDeposition Rate > 75 nm/min > 75 nm/minDeposition Rate > 75 nm/min > 75 nm/minDeposition Rate > 75 nm/min > 75 nm/min

NANOCHIP 13

Figure 6. SEM of AlN deposited on a Mo bottom electrode illustrates the well-matched crystallinity of the two fi lms.

Individual Measurementof Thickness-Polar_EE6mm

Wafer Number1 5 10 15 20 25 30 35 38

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s Po

lar_

EE6m

m

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Individual Measurement of %std-Polar_EE6mm

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%st

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olar

_EE6

mm

0.50

0.49

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Avg=0.4567

Individual Measurementof Dep Rate

Wafer Number1 5 10 15 20 25 30 35 38

Dep

Rat

e

75.475.375.275.1

75.074.974.874.774.674.574.4

UCL=75.251

LCL=9628.47

UCL=0.4866

LCL=74.447

UCL=9732.61

LCL=0.4268

Avg=74.849

Figure 7. Recent development results for (a) 1µm thick Al deposited at 250°C show (b) nonuniformity of 0.457% and (c) a deposition rate of 74.8 nm/minute.

(a) (b) (c)

SUMMARY

PVD for 200mm power devices, MEMS and RF applications is a key emerging technology segment for Applied Materials. To serve customers in these markets, the industry-standard Applied Endura 200mm PVD chamber has been enhanced to deliver a competitive, state-of-the-art, single-chamber and cluster solution for thick Al and AlN that meets volume-production throughput targets. Its temperature tunability (250°C–450°C) readily accommodates both applications. Deposition rates exceed 2µm/minute for Al up to 5µm thick; and consistently meet the 75nm/minute requirement for AlN thicknesses ranging from 50nm to 2.5µm. Thick Al layers exhibit superior surface roughness and grain boundary grooving with stable Rs, refl ectivity of 70–80 @ 633nm, and neutral stress (~50MPa). AlN layers are

exceptionally uniform (<0.5% on 6” and 8” wafers; <0.2 on 4” wafers) and AlN’s inherent high degree of c-axis (002) crystal orientation is enhanced when the oxide underlayer is planarized (FWHM rocking curve <1.3).

For additional information, contact [email protected].

[1] Yole Developpement, 2013.[2] A.Nakagawa et al., “Safe operat-

ing area for 1200-V non-latch-up bipolar-mode MOSFETs,” IEEE Trans. on Electron Devices, ED-34, pp. 351–355, 1987. (https://www.princ-eton.edu/~achaney/tmve/wiki100k/docs/Insulated-gate_bipolar_tran-sistor.html)

[3] Steven Mahon and Robert Aigner, Bulk Acoustic Wave Devices – Why, How, and Where They are Going,” Proceedings of the CS MANTECH Conference, May 14-17, 2007, pp. 15-18.

[4] W. E. Newell, “Face-mounted piezoelectric resonators,” Proceed-ings of the Institute of Electrical and Electronics Engineers, 53, pp. 575-81, 1965.

[5] Sha Zhao, et al., “Underlayer Infl u-ence on AlN Deposition by Reactive

Magnetron Sputtering,” China Semi-conductor Technology International Conference, 2014, ECS Trans., 2014, 60(1): 1171-1176.

[6] F. Engelmark, et al., J. Vac. Sci. Tech-nol. A, 18 (4), 1609, 2000. “Synthesis of highly oriented piezoelectric AlN fi lms by reactive sputter deposition,” vol. 18 (4), pp. 1609-12, 2000.

[7] Robert Aigner, “SAW, BAW and the future of wireless,” http://www.edn.com/design/wireless-network-ing/4413442/SAW--BAW-and-the-future-of-wireless, May 6, 2013.

[8] Ting-Ta Yen, “Experimental Study of Fine Frequency Selection Techniques for Piezoelectric Aluminum Nitride Lamb Wave Resonators,” http://www.eecs.berkeley.edu/Pubs/TechRpts/ 2013/EECS-2013-189.pdf.

[9] S. Mishin, B. Sylvia and D.R. Marx, ”Improving Manufacturability of AlN Deposition Used in Making Bulk Acoustic Wave Devices,” IEEE Ultrason. Symp. 215, 2005.

[10] K. Umeda, et al., “Improvement of thickness uniformity and crys-tallinity of AlN fi lms prepared by o° -axis sputtering,” Vacuum, 80, 658, 2006.

[11] G.F. Iriarte, et al., “Infl uence of deposition parameters on the stress of magnetron sputter-de-posited AlN thin fi lms on Si(100) substrates,” J. Mater. Res., 18 (2), 423, 2003.

[12] R. T. Howe and T. J. King, “Low-temperature LPCVD MEMS technologies,” BioMEMS and Bionanotechnology Symposium, Materials Research Society Proceedings, 729, 01, 2002.

[13] Sha Zhao, et al., “Early Observa-tions between Magnet and Film Properties for AlN Deposition by Reactive Magnetron Sputtering,” China Semiconductor Technol-ogy International Conference, 2013. ECS Trans. 2013 52(1): 391-396.

NANOCHIP14 NANOCHIP14

Factory-wide continuous improvement programs often include e¥ orts to improve dispatching rules for meeting cycle-time commitments and increase throughput for bottleneck tools.

Factory simulation software is used in today’s semiconductor environments to manage the risks of changing dispatching rules. Current simulation models require manual coding of dispatching rules into C++ extensions—an expensive, error-prone process because it’s di¦ cult to recreate a complex and dynamic production environment with complete fi delity. The alternative—analyzing and validating changes to dispatching rules and policies directly on the factory fl oor—is disruptive, risky and costly.

APF Fusion, the latest addition to Applied Materials’ Advanced Productivity Family (APF) software suite, is designed to solve this problem. A dispatching and capacity-analysis solution, APF Fusion provides a bridge between Applied’s AutoSched AP simulation and APF real-time dispatching (RTD) software. It enhances users’ ability to perform the “what if” simulations needed for more realistic dispatching/scheduling policy changes and short-term capacity planning.

INTEGRATES DISPATCH WITH SIMULATION

APF FUSION

Rapidly test dispatching rules without impacting production

BYNANOCHIP

STAFF

CASE STUDY

NANOCHIP 15

APF Fusion allows users to port existing dispatching rules from production APF RTD into simulation automatically, enabling the same dispatching rules to be used both on the factory fl oor and in simulations. This eliminates the need to create and maintain duplicate sets of rules for test and production environments, and dramatically reduces simulation times (see fi gure 1).

“APF Fusion makes it possible to quantify the e¥ ects of proposed rule changes before they are put into production,” said David Hanny, marketing manager for automation products at Applied. “When companies have one set of rules on their factory fl oor and a di¥ erent set of rules in their planning and simulation systems, it becomes di¦ cult to predict, for example, how many wafers to start or how much more equipment to buy.”

SEAGATE TECHNOLOGY REDUCES TIME, COSTS

Seagate Technology, a leader in data storage technology, is an early APF Fusion adopter, using it in their 200mm fabs in Bloomington, Minnesota, and Londonderry, Northern Ireland, which produce disk drive recording heads. Both sites have online factory

The switch back, together with having repository support within the APF Formatter, enables you to use the same dispatching rule for both the production and simulation model

Production Dispatching Rule Flow

Simulation Dispatching Rule Flow

SINGLE PRODUCTION AND SIMULATION DISPATCHING RULE

Dispatching Logic(Same for Simulation

and Production)

Product Due Date Priority

AutoSched Lot in Def Cycle Priority Due Date

Switch In

Lot

Min Priority/Min Due Date

APF

APF

xx

x

Figure 1. A single set of production and simulation dispatching rules enables faster testing and validation cycles.

simulation and RTD capabilities. The company’s dispatch team wanted to improve its ability to examine trade-o¥ s and then validate dispatching and scheduling policies.

Brian Gowling, senior manager of Industrial Engineering for Seagate’s RHO-Wafer Manufacturing operation, said the dispatch team sought to develop rules without adversely a¥ ecting production schedules and R&D cycle times. Working in an o ́ ine model, the team looked at how new rules might a¥ ect product cycle times, equipment capacity, utilization and throughput. They also sought to record factory events, so they could develop a more e¦ cient response to unforeseen events such as down tools, work-in-process (WIP) bubbles, and changes in demand.

Prior to installing APF Fusion, Seagate ran automated online factory simulations that updated actual factory conditions every 30 minutes and provided forecasts ranging from one shift ahead to one week ahead. The main applications for these simulations were to defi ne the goals for factory shifts, prioritize bottleneck equipment, schedule preventive maintenance (PM), prioritize process “No Path” and “Limited Path” e¥ orts, and set weekly factory velocity goals.

NANOCHIP16

However, the dispatch rules in the simulation model were simplistic compared to those in the factory dispatcher (see fi gure 2), resulting in signifi cant simulation inaccuracies (see fi gure 3).

“Because APF Fusion enables us to maintain the same dispatching rules for both production and simulation model environments, in one case we implemented and adjusted a

Figure 2. Di° erences between the detailed dispatch rules in the factory dispatcher at a Seagate Technology 200mm fab (left column) versus the more simplistic rules used in the fab’s simulation model before the installation of APF Fusion software.

Figure 3. Before APF Fusion software was installed at a Seagate Technology 200mm fab, more than 40% of the inaccuracies in lot-by-lot dispatching simulations were caused by major di° erences in wafer queue times. These inaccuracies occurred, in part, because specifi c dispatch rules could not be adequately modeled.

Sim Forecast Accuracy: Average Count of Lot-by-Lot Defects > Threshold

45%

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30%

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20%

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0%Lot

QueueTimes

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Rework Misc

INTEGRATES DISPATCH WITH SIMULATION

APF FUSION

CASE STUDY

FAB DISPATCHER

Lots are grouped by recipe

Batches ranked by priority, local rules, and then global dispatch

Batches managed by many parameters:Tool specs, product, process step, process path, RD team, experiment, recipe, lot ID, and priority

Over 40 distinct dispatch rules with 5–10,000 active parameters; each of the dispatcher rules is e¥ ectively a custom extension

Dynamically-modifi ed rules by WIP and tool conditions

ONLINE SIMULATION MODEL

Lots are grouped by recipe

Batches ranked by priority, then global dispatch

Batches have minimum and maximum constraints based on equipment and process step

Minimal customized dispatch logic in simulation extensions

Does not exist currently in simulation

batching parameter from the dispatch rules from within the online simulation,” Gowling said. “Previously, we didn’t have a method of modeling this rule to view the impact.” (See fi gure 4.)

With APF Fusion, Seagate was able to integrate an RTD rule into simulation, validating the e¥ ects of fi ve di¥ erent dispatching parameters on key performance indicators (KPIs) at both its manufacturing sites in just one week instead of the more than six months it would have taken otherwise. That modeling ability directly translated into about $100,000 in labor savings.

BETTER ALLOCATION OF METROLOGY RESOURCES

APF Fusion has also helped Seagate better allocate its metrology resources. Out of eight metrology tools at a fab, only two can perform specifi c functions Seagate calls “CUT” and “MEAS; the remaining six tools only perform “MEAS.”

Under normal operating conditions, the CUT function is primarily used for engineering and R&D WIP. Specifi c engineering and R&D teams are given a daily allocation of CUT metrology capacity. Some teams are allowed to run one or two wafers per day; others can run as many as 10 per day (see fi gure 5).

When WIP is balanced, the six dedicated MEAS tools can keep up with all the MEAS-related WIP. In such instances, the R&D teams are allowed to exceed their allocation. However, if a WIP bubble begins to grow, either because of too few available tools or because of a WIP infl ux, CUT-related WIP is deprioritized and the two “dual-capability” tools process MEAS-related WIP instead.

The factories’ dispatching rules control the balance of the R&D and production lots run on these metrology tools. Seagate engineers can adjust that balance dynamically to smooth out the WIP bubbles.

FACTORY-WIDE VIEW

While some manufacturers rely on spreadsheets for capacity planning, Madhav Kidambi, Applied APF Fusion product manager, said discrete event simulation is far more accurate, and factory-wide simulations enabled by Applied’s APF suite, which includes Fusion, will enable more accurate “what-if“ analyses.

“Engineers will be able to see the impact of dispatching rules not only in their specifi c area of interest, but in other areas of the factory as well. APF Fusion makes it possible to see the impact of changes everywhere else in the factory and to view overall factory performance.”

For example, many companies pay particular attention to the dispatching/scheduling algorithms in the photolithography area because those tools consume a large part of the budget.

NANOCHIP 17

Figure 4. The graph shows the impacts of implementing and adjusting a batching parameter from within the online simulation provided by APF Fusion. The data comes from three simulation model runs where a WIP bubble event was recorded at a constrained tool. Seagate previously had no way to model this dispatch rule to view its impact.

Figure 5. At Seagate, factory dispatching rules control the balance of the R&D production lots run on eight metrology tools. If a WIP bubble occurs, CUT-related WIP is deprioritized, and the two metrology tools performing this function will process MEAS-related WIP instead.

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Example of Metrology Tool WIP Allocation

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However, Kidambi said companies may fi nd that over time lithography is not the true constraint in the fab.

“It could be etch, it could be some other area. If you just do a local optimization in the litho area, it could very well lead to big WIP bubbles in other areas. Then, at the end of the day, you’ll fi nd the overall improvement is not there, and all you have done is created another bottleneck.”

APF Fusion best fi ts into a simulation environment used for tactical-level planning; that is, relatively short-term capacity planning of one week to three months.

“For longer-term simulation, you are better o¥ running a steady-state simulation analysis,” Kidambi said. “But Fusion can support simu-lations which indicate where there are bottleneck tools that are keeping the fab from meeting customer commitments in short-term scenarios.”

To get the most benefi t from APF Fusion, the latest versions of AutoSched AP and APF RTD and Reporter software are required.

THE HUMAN FACTOR

According to Hanny, one challenge facing the industry is the di¦ culty of coordinating the e¥ orts of engineers working separately in dispatching, on the shop fl oor, and in planning.

“In many cases their work is siloed. APF Fusion will both enable and require engineers to work more collaboratively, so that faster, better operational decision-making is achieved.”

Kidambi said several semiconductor companies have expressed a desire to integrate their homegrown scheduling/planning tools using APF Fusion.

“We have heard from some companies that they want this kind of capability so they can use our SmartSched [short interval real-time scheduling] software, and also integrate with homegrown or commercial scheduling products. That would give them a great capability to integrate external scheduling algorithms. At this point, however, these are just internal development projects.”

For additional information, contact [email protected]

Team A

Team B

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Team D

DAILY CUT ALLOCATION

1

2

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9

NANOCHIP18

Applied Materials’ success depends on serving customers well—not just once, but over and over, as new generations of devices and production tools evolve.

To evolve our operations so that Applied Materials can consistently deliver competitive products and services, superior customer experiences and healthy business results, we engage in ongoing e¥ orts to sustain and strengthen a culture of systematic, companywide continuous improvement.

In March 2012, we centralized all our continuous improvement initiatives under one Global Continuous Improvement

■ Customers: Improvement begins with an accurate and comprehensive understanding of what the customer is telling us, then translating that customer “voice” into specifi c measureable items called critical to quality metrics (CTQs).

■ Processes: In CI, all work is viewed as process and has a clear start, fi nish, inputs and outputs. The “improvement” part of CI focuses on how we make these processes more successful at delivering services that meet our CTQs.

■ Variation and waste: When processes don’t meet our CTQs, it’s typically because the process steps demonstrate excessive variation and/or waste.

Voice of the customer drives Applied’s continuous improvement initiatives

BY ROB

RULE

(GCI) team in a formalized e¥ ort to drive both greater customer satisfaction and improved business results through sustained improvements in speed, quality, and cost. The GCI team’s mission is to accomplish this by improving and accelerating business processes, empowering employees, and embedding a culture of continuous improvement across the corporation.

Continuous improvement (CI) is generally defi ned as a collection of activities used to improve the ability of core processes to meet customer requirements. For us it means listen-ing to customers, improving our processes, and reducing variation, defects and waste.

BUILDING CUSTOMER SATISFACTION

NANOCHIP 19

IMPROVING SERVICE DELIVERY

A key initiative in Applied’s CI e¥ ort targets improvements in the delivery of customer services—fi eld service, parts and product support. The focus is on continually improving the capability of our core service processes to enhance the speed, quality and value we provide.

For example, in an Applied Materials Voice of the Customer (VoC) survey, respondents stressed that the predictability of tool uptime was important to them. Additionally, they indicated that Applied could improve the speed with which service issues were resolved.

In response, Applied Global Services (AGS) developed new platform-focused service options that can help pinpoint toolset-specifi c performance parameters. This approach enables faster detection, prediction and resolution of performance issues specifi c to those tools. In addition, AGS defi ned specifi c CTQ measurements related to speed and availability, and launched multiple service delivery improvement projects for customers on service contracts.

One of these projects examined the speed with which Applied resolved particle issues. While AGS was meeting contract commitments for tool performance, a deeper and more thorough look at our performance revealed a signifi cant opportunity to improve

resolution times. Particle events are a great candidate for process improvement because they can be complicated to diagnose and require actions that involve a lot of inherent wait time. At any step in the particle recovery process, for example, Applied customer engineers (CEs) can fi nd themselves waiting for test wafers, for parts, or for a chamber to reach operating conditions.

The project team realized that while CEs couldn’t eliminate all the wait time associated with recovery, they could standardize response actions to minimize the number of cases where unnecessary wait time was incurred. The team then consolidated existing technical and process knowledge from our product support teams and process labs to develop standard response guides. Key elements of the new response guides included:

■ Specifi c, standard, immediate-response actions to validate failures and avoid lost production time due to false alarms.

■ Situational procedures to mitigate particle levels and avoid invasive corrective actions.

■ A catalog of common “known sources” to aid troubleshooting and avoid the need for excessive partitioning tests.

By rolling out these new standards, the project team drove a >50% reduction in the number of long-duration particle events (see fi gure 1). That in turn reduced the average

AGS response time for such events, better enabling us to help customers achieve their production goals.

BETTER COMMUNICATION OF SPARE PART CHANGES

Applied Materials is also focusing on improving customer experiences related to spare part services. We learned from our VoC survey that customers wanted more e¥ ective and more timely notifi cation of engineering or supply changes to spare parts. Customers could then use this information to plan for change and ensure they had adequate time to complete any necessary testing and qualifi cation.

Accordingly, Applied launched two CI projects. The fi rst redesigned the communication process so that customers on service contracts receive clear and relevant information on the specifi c parts they use. The second increased the lead time of these notifi cations to give customers more time to assess and prepare for change and help them minimize disruptions to their operations.

As a result, more than 80% of contract part change notifi cations are now delivered to contract customers at least 180 days prior to taking e¥ ect, compared to just 30% before.

AN ONGOING EFFORT

Applied Materials invests aggressively in CI e¥ orts. These include advanced training and information systems for CEs, improved demand planning, and Lean Six Sigma initiatives led by “black belt” experts, using tested, world-class methodologies to systematically track, analyze and upgrade our own performance.

In CI there is no “fi nish line.” There will always be room for us to improve our delivery of products and services that delight our customers. Applied’s new GCI initiatives are a tangible expression of our commitment to the future and to our customers’ success.


Long

-Dur

atio

n Ev

ents

DEFINE CONTROLMEASURE ANALYZE IMPROVE

Baseline Period Post-Improvement PeriodParticle Service Call Performance (P-Chart)

Figure 1. The trend chart above shows the proportion of customer tool particle events for which there was a lengthy resolution time. Standardizing Applied Materials’ responses to resolution of particle events resulted in performance improvement of over 50%.

NANOCHIP20

BEYOND THE SMARTPHONE:

THE NEXT BIG THINGBY

DAVID LAMMERS

NANOCHIP 21

Lacking a clear consensus on specifi cs, most market watchers nonetheless agree that it will have something to do with the Internet of Things (IoT). A June 2014 report by International Data Corporation (IDC) estimates that sales of billions of smart, connected gadgets like Google Glass will generate a stunning $7.1 trillion in annual sales by 2020, with most of the total in services and supporting software.

According to Rob Lineback, an analyst at IC Insights, some people in the industry are looking for one or two huge growth drivers; others believe the next big thing will be made up of many products to serve many markets.

Automotive electronics is a large segment that is showing healthy growth, he said. Wireless medical systems and fi tness trackers are generating a lot of interest, and the category is projected to grow by a CAGR of about 37%, reaching $4.7 billion in 2017. The semiconductor content, however, “is just not big enough to move the needle much for a $300 billion industry,” said Lineback, who co-authored the IC Insights IC Market Drivers Report.

He noted that medical systems are set to grow to about $65 billion by 2017, while medical semiconductors are roughly a $5 billion market this year and forecast to grow to $6.8 billion by 2017—a relatively small market compared with PCs or smartphones.

“When we look ahead, there are plenty of things to watch. Some will be a fad, a fl ash in the pan, while others may take hold. It’s the old saying: ‘You don’t know what the next big thing is until you get there,’” Lineback said.

A MEDICAL BREAKTHROUGH?

Eileen Tanghal, director of Applied Ventures LLC, a venture capital fund, sees medical as a prime IoT opportunity. A variety of medical testing, personal diagnostic, gene sequencing, and drug discovery procedures are still being done on glass

slides in labs, using labor-intensive methods.

“Replacing those with silicon-based testing would signifi cantly reduce the cost-per-test and speed up the ability to develop new drugs,” she said, estimating that if the medical testing and remote diagnostics industries in the developed nations move to silicon-based solutions, it could add about $1.2 billion to the worldwide semiconductor equipment market. If these tools are adopted worldwide, the impact on the silicon equipment industry could reach the $5 billion level.

Food production and clean energy are two other areas ripe for silicon-based solutions, according to Tanghal.

CHARTING A COURSE FOR IoT DATA

Mike Rosa, a MEMS expert and senior strategic and technical marketing manager for 200mm Emerging Technology Products at Applied Materials, believes that the semiconductor industry’s next wave lies in the thousands of IoT device applications for sensors, microcontrollers and communications that will combine to help people make decisions. “But generating value out of the data, gathering the right data to make an informed decision: therein lies the value of the Internet of Things,” he said.

The semiconductor industry has been on a roll, pushing well past $300 billion in annual revenues. But with smartphones and tablets showing signs of slowing down, the industry’s perennial question returns: What is the next big thing?

IDC defi nes the Internet of Things as “a network

of networks of uniquely identifi able endpoints (or

“things”) that communicate without human interaction

using IP connectivity—be it locally or globally.” using IP connectivity—be it locally or globally.”

THE INTERNET OF THINGS IS...

Courtesy of Intel CorporationCourtesy of Intel Corporation

Devices Gateways Network Data Center

MOBILE

HOME

INDUSTRIAL

NETWORKINFRASTRUCTURE

Devices that are connecting to the Internet, integrating greater compute capabilities, and using data analytics to extract meaningful information.

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from APC technologies and by sensors attached to thousands of machines can be used to detect, classify, diagnose, control, predict and prevent various failure modes. “It is the new data that makes predictive maintenance a reality,” Read said.

STANDARDS AND SECURITY

Bill Curtis, director of new business development at ARM, Ltd., argued that much work remains to be done to develop the standards required for high-volume IoT markets. “The things around us are increasingly smart and connected, creating an opportunity for shipping billions of devices. However, today we live in a siloed world. There are many di¥ erent standards, and almost none of the stu¥ out there can communicate.”

from the need for gateway products and cloud-based computing services. As data comes streaming in from sensors, gateway systems will fi lter data so as not to overwhelm the network infrastructure. “A gateway device would decide: ‘Is this important? Should I send it or not?’”

Speaking at SEMI’s recent IoT conference, held in Austin, Texas, Formisano said the fi rst IoT waves are being seen in industrial applications, such as sensor-driven systems for manufacturing semiconductors, chemicals, and other high-value products. “Intel is using the IoT to make our chips. Gone are the run cards a¦ xed to the run box. Today’s leading-node factories rely on high levels of advanced process control and large amounts of data coming through the sensor networks,” he said.

“Also interesting is this notion of ‘brown fi eld’ things, which refers to the 85% of the things out there which are not connected. Street lights are still not intelligent, semi-trailer trucks are still not part of a fl eet management system. To get them connected you don’t have to build a brand new bus, or truck, or train. So there is a lot of excitement today in getting today’s things on the IoT,” Formisano said.

As demand for IoT devices skyrockets, Jeremy Read, head of service marketing at Applied Global Services, said semiconductor manufacturers increasingly will upgrade their existing 200mm tools to run the modern automation software and advanced process control (APC) applications that are key parts of what he calls an industrial IoT (IIoT) approach to chipmaking. Data gathered

Indeed, thinking primarily about the connected gadgets at the “edge” of a network is selling the IoT short. Alongside the low-cost edge devices are gateways, cloud-based computing and all of the services and software required to analyze the data streaming in from edge devices.

While much attention is focused on the low-cost “intelligent edge” devices, David Formisano, Intel’s director of strategy of integrated Internet of Things, said Intel will profi t

POWERING THE INTERNET OF THINGS

Advanced SafetyAdvanced Safety

InfotainmentInfotainmentRadar + Vision

Cloud Computing

Smart Energy Grid

Energy Management | Wind + Solar

Digital Power Conversion Connected Farms

Industrial NetworkingIndustrial Networking

Human – Machine Interface

Machine – MachineMachine – Machine

Data CenterBase Stations

Tra�c Monitoring

Telehealth

Home Hubs

Security

Energy Meters

Connected Appliances

Home Health Monitors + FitnessHome Health Monitors + Fitness

MOBILE

CONSUMER

INDUSTRIAL

Microcontrollers | Digital Networking | Auto MCU | Analog and Sensors | RF

NETWORKINGMetro Cells | Small Cells

Networked PrintersNetworked Printers

Enterprise Gateways, Switchers, Routers

Security

Courtesy of Freescale Semiconductor, Inc.

BEYOND THE SMARTPHONE:

THE NEXT BIG THING

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Formisano said the corporate world needs interoperability standards so that IT and operations organizations can share data. And ever since the public became aware of how much data is being secretly gathered, security and privacy concerns are increasing. “Security and privacy is a big challenge. The government is interested in the IoT, but almost every week is asking, ‘How do we deal with the privacy and security issues?’”

Costs are another major concern. To put a sensor, control circuitry, Internet communications capabilities, and some form of energy harvesting on an edge device selling for less than a dollar or two is a formidable challenge. Curtis points to ARM cores aimed at IoT applications: 32-bit processors consisting of just 12,000 gates. “The processors are pretty doggone small. Going forward we will want a world of very small, very cheap devices,” he said. And a whole new world of communications protocols is evolving to ensure that data

can be sent over the Internet at very low levels of power consumption.

Rajiv Kumar, marketing manager at Freescale Semiconductor’s microcontroller unit, said tiny 32-bitters are powerful enough to recognize hand-motion interfaces, such as those used on NEST home controllers. Kumar sees the IoT putting new vigor into the electronics industry, as startups work on “very tangible problems” across all walks of life. “Now, almost everyone has a mobile phone, and tablets compete with PCs for market share. I see the next wave as a lot of connected waves, becoming more and more relevant.”

Freescale o¥ ers a multitude of IoT-class microcontrollers, using a Lego-like building-block approach to quickly confi gure ARM-based solutions. And design teams can download tools and use credit-card sized development boards to quickly come up with IoT-type solutions for hundreds of markets, Kumar said.

PRINTED ELECTRONICS NEEDED?

Rosa said he believes silicon-based solutions will not be inexpensive enough to meet the cost targets mandated by many IoT applications. Printed electronics on cheap plastic substrates will fi nally come to the fore, undercutting the cost to process silicon wafers. While some market research fi rms predict that a trillion sensors will be in use by 2020 or 2022, Rosa said that is unlikely unless production costs are driven down. “There are about 12–14 billion MEMS in use today, so a trillion sensors by 2020 is not going to happen unless we can cut the manufacturing costs by one to two orders of magnitude.”

Dean Freeman, semiconductor manufacturing analyst at Gartner, said printed electronics are appealing, but thus far they haven’t found a commercial high-volume application. “Many of the IoT-class MCUs and communications devices will be made in 300mm fabs, using legacy process technology.”

Freeman calculates that 10 billion IoT things, each with an

average of three MEMs devices, may be made in 2020. That would create demand for about 22 new or converted 200mm fabs, each running 50k wafers per month. “That is assuming an 80% yield and a 4mm2 device. That is about 1.1 to 1.2 million wafer starts per month,” he said. Viewed another way, a moderately successful IoT market would add about 10% to the annual wafer fab equipment (WFE) expenditures, about equal to today’s market for refurbished equipment, he added.

THE NEXT BIG THING: IoT OR I DON’T KNOW?

So all of this debate leaves us with a few questions: Will the next big thing rely more on chip technology, new materials technology, or software? Or all of the above? And at the end of the day, what is it that will have us lining up at some big-box store at midnight to buy one?

Applied Ventures’ Tanghal, who considers herself an optimist, fi rmly believes that something will emerge as a high-volume, high-value product akin to what the smartphone has been since 2007. The next big thing is out there, she said, probably being developed by young people in ambitious startups with dreams of a buy-out by companies like Google, Amazon, or others. Maybe personal robots, drones or other forms of human-assistance systems will be winners. Or something else?

“Innovation doesn’t stop,” said Tanghal.

What do you think will be the next big thing? Send your ideas to [email protected]

$14.4 TRILLION

Courtesy of Cisco Systems, Inc.

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Figure 1. The Internet of Things will create a dramatic transformation in industrial economies, as connected devices, cloud-based computing, and Big Data analytics converge. The biggest impact, already underway, is in manufacturing, with an estimated $3.9 trillion in added value over the next ten years.


“Thick” is a relative term, of course. Today, epi fi lms of more than 20µm are regarded as thick, although developmental targets for epi fi lms can be as much as ~150µm in thickness.

For power semiconductors it’s the electrical isolating qualities of the undoped thick epi fi lms that provide the benefi t. They enable higher voltages with larger R(o¥ )values, and contribute to higher switching speeds and reduced device footprints (see fi gure 1).

For MEMS devices—gyroscopes, pressure sensors, digital compasses, accelerometers, and now micromirrors for a new breed of pico projectors—thick epi opens a route to lower cost manufacturing, combined with greater device sensitivity and performance thanks to the taller mechanical structures (i.e., the smaller footprint) it enables (see fi gure 2).

Additionally, manufacturers who have been purchasing device-layer silicon-on-insulator (SOI) wafers now have the option to produce high-quality thick epi fi lms themselves, thereby reducing wafer costs.

ENHANCES PERFORMANCE OF POWER AND MEMS DEVICES

BYMIKE

ROSA, PHD

THICK EPITAXIAL SILICON

Power semiconductors and MEMS-based sensors and actuators are fundamental to the advanced capabilities and e¥ ective power management of mobile products and advanced systems. One way to enhance the performance of these power and MEMS devices is by using thicker epitaxial (epi) layers, an approach that is gaining traction for a range of applications.

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NEW THICK EPI TECHNOLOGY FOR 200MM CENTURA TOOLS

Applied Materials is committed to ongoing investments and R&D activities to support emerging applications for 200mm technology. This includes continued development of its widely used 200mm Centura Epi platform.

Given the potential benefi ts of uniform, high-quality thick epi layers, Applied Materials has developed a unique hardware upgrade kit to enhance the thick silicon epi fi lm capabilities of the 200mm Centura Epi platform. The upgrade kit enables users to deposit silicon epi up to 100µm thick with outstanding fi lm properties, uniformity, lower defect levels and throughput, in the same chamber where they currently grow thin epi layers. Development is ongoing to further enhance the growth rate for higher production throughput and for fi nal thickness, currently targeted at 150µm.

This single-chamber, single-vendor capability is unique in the industry, and helps users reduce costs and complexity. It is available now on new and refurbished 200mm Centura Epi tools, and as an upgrade for the installed base. It is one more way in which Applied—a pioneer in epitaxial technologies and the leading supplier of epitaxial deposition equipment—helps customers extend the life cycle and maximize the value of this familiar, reliable and cost-e¥ ective toolset.

The new kit is based on hardware upgrades, including an advanced motorized lift, a new tapered susceptor design, a new susceptor alignment tool (SAT) and other hardware and software enhancements transposed from advanced Applied 300mm toolsets. It provides the capability to grow thin (<1µm) or thick (≤ 100µm) silicon

Figure 2. New MEMS devices such as micromirrors for pico projectors, along with established MEMS products such as gyroscopes and accelerometers, can leverage thicker silicon device layers for improved performance and benefi t further from still thicker layers. The images shown are scanning electron microscope (SEM) photographs of a MEMS gyroscope (top) and stand-alone micromirror.

n+ substrate

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Figure 1. Power devices such as superjunction MOSFETs, illustrated above, can benefi t from thick epi layers. In (a) we see the predominant manufacturing method, where a thick epi deposition is doped in one area, repeated several times to build thickness, and then is annealed. In contrast to this multistep method, (b) shows a simpler approach where a thick epi layer is grown, etched using deep reactive ion etch (DRIE), and then fi lled using a doped thick epi capability to build a superjunction power MOSFET. R&D implementations of this are shown in (c) and (d), as companies continue to experiment with thick epi, DRIE, oxide fi ll and other processes.

(a) (b) (c) (d)


epi layers in the same process chamber, enabling higher growth rates (up to 6µm/min), greater process fl exibility, and the ability to produce a higher number of better performing devices.

ENABLING THICK EPITAXY FOR POWER DEVICES

Thick epi is currently being used to enhance insulated gate bipolar transistors (IGBTs) and superjunction (SJ) MOSFETs. Higher density devices can be built using these thicker epitaxial silicon layers. This enables IGBTs to operate at higher power levels and SJ MOSFETs to switch faster and at ever higher voltages while maintaining small form factors.

SJ MOSFETs are a newer device-type gaining preference over conventional power MOSFETs in applications where small size and fast switching at high voltages are key requirements. These include power adapters, game consoles, solar inverters, and battery chargers for products such as tablets and laptops.

Conventional planar MOSFETs have cells built from well-like structures, whereas the body of an SJ MOSFET features cells with a columnar structure in which p-type columns extend vertically through a relatively thicker n-doped epitaxial region to the substrate (see fi gure 4). Conventional power MOSFETs su¥ er from a so-called “silicon limitation” where an increase in the voltage-blocking capability causes an increase in on-resistance, making it more di¦ cult to achieve energy savings in the end product.

With SJ MOSFETs, however, the relatively thicker and highly doped epi region enables higher breakdown voltages, while the close spacing of tall, thin columns increases cell density and allows voltage- and current-handling capabilities to be maintained as die sizes shrink. Reduced on-resistance is achieved by reducing the overall thickness of the die.

To build these devices, fi gure 1 (b)–(d) shows how the thick silicon epitaxial layer is subsequently etched using a dedicated DRIE tool to form trench structures. The trenches are then backfi lled with highly doped void-free material using a reduced-pressure (RP) epi process, also enabled by the 200mm Centura Epi platform. Using its own 200mm DRIE tools, Applied Materials has demonstrated aspect ratios for these trenches as high as 40:1, with critical dimensions of about one micron in trenches 44µm deep.

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APPLICATIONS: AC drive–Grid T&D / medium to high voltage

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Power Electronics MarketPower Electronics Device Characteristics

SJ MOSFETs have the same range of characteristics as high voltage MOSFETs: Up to 900V and 75A, switching at higher than 50 kHz

IGBT

APPLICATIONS: All type of inverters kW to MW range

MO

SFET

Figure 3. SJ MOSFETS are still a small part of the overall power semiconductor market (~10%) but their growing voltage- and current-handling capabilities, combined with their existing high switching-speed capabilities, will eventually threaten the market share of iGBTs. (Figure courtesy of Yole Développement.)

GS

D

Planar GS

D

Superjunction

p p

Figure 4. Conventional planar MOSFET structure at left, and SJ MOSFET structure at right. SJ MOSFETs have cells with p-type columns extending vertically through an n-doped epitaxial region to the substrate. The thicker p-doped region enables a lower R(on), as well as a higher R(o° ) in the blocking state.




Key requirements for the overall process include an atmospheric (ATM) epi process to grow the thick n-type layer silicon, followed by a DRIE step that demonstrates precise control over sidewall profi le and trench top and bottom critical dimensions. That in turn is followed by an RP epi process for fast, void-free fi lling. The Applied 200mm 3-chamber Epi Centura platform can accommodate both ATM and RP confi gured chamber-types.

THICK EPITAXY FOR MEMS DEVICES

The push for more functionality in portable electronics has resulted in more MEMS content in each new generation of consumer devices to support features such as gesture recognition and GPS.

As with integrated circuits, MEMS components are facing constant downward price pressure. There is also simultaneous demand for greater performance and smaller sizes because of the importance of form factor in handheld systems.

Force ~ V21 tl2 g

g

t

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Figure 5. Thicker epi layers combined with an advanced DRIE etch process can enable higher structural density and thus higher sensitivity in MEMS devices (and in just about any type of electrostatic device that utilizes arrays of interdigitated comb-fi nger structures for either sensing or actuation). As shown in the above illustration and accompanying equation, device thickness (t) is directly proportional to force and voltage applied. Increasing (t) in the device design provides the opportunity to either reduce V, or to keep everything constant and achieve a greater F (e.g., capacitive sensitivity), depending on the device’s function.

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FR (Operating Frequency)

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Figure 6. For resonant MEMS devices, the TTV of the device layer must be minimized across the entire wafer, given the large e° ect it has on the fundamental resonant, or natural, frequency of the MEMS devices produced on that wafer. The fi gure above mathematically illustrates how changing the physical dimensions of a structure—for example, by excessive variations in thickness—would lead to changes in resonant frequency.

Thick epi opens up the possibility for lower-cost manufacturing, and because taller, thinner mechanical structures can be fabricated from thicker epi layers, the sensitivity and performance of these tiny machines can be increased while their overall sizes are kept to a minimum (see fi gure 5).

A key requirement is that the total thickness variation (TTV) of the device layer be exactly the same across the entire wafer. This need arises because many types of MEMS devices are operated at their mechanical resonance, or natural, frequency. This is the frequency at which their sensitivity, or displacement for a given input energy, is maximized.

The resonance frequency is normally the device’s operating frequency, and any variation in the thickness of the device layer will trigger a change in it. That could inadvertently lead to MEMS devices with di¥ ering performance characteristics produced on the same wafer (see fi gure 6).


THICK EPITAXY FOR DEVICE-LAYER WAFERS

At present, device-layer SOI wafers are fabricated using a complex, multistep process. First, a silicon wafer is wafer-bonded directly to a handle wafer with an oxide layer (either thermally grown or fabricated via CVD). The silicon is ground down to a specifi ed thickness, planarized via CMP, and then transferred to an insulating substrate, after which devices can be built with it.

Applied’s enhanced 200mm Centura Epi platform o¥ ers a simpler approach. An insulating substrate is grown or deposited directly on a handle wafer. Then, a uniformly thick epitaxial polysilicon layer is grown directly on top of it (see fi gure 7).

KEY FABRICATION CHALLENGES

As with any new technology, the fabrication of thick epi fi lms brings challenges as well as opportunities. The major challenges are:

■ Uniformity: it’s more di¦ cult to achieve overall fi lm thickness and doping uniformity with thicker epi fi lms because the thicker the fi lm, the more di¦ cult it is to control doping concentration across the wafer and through the thickness of the fi lm. A constant and uniform wafer temperature is also critical.

■ Film growth rate: keeping a tool’s productivity high is always a key goal; Applied’s current growth rate target is to achieve deposition rates of ≥6µm/minute per chamber for single-step fi lm deposition.

Epitaxial SiGrowth

(20µm – 150µm)

Direct Wafer Bonding

1) Wafer Grind2) Fine Polish

Handle Wafer

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Device Layer

Handle Wafer

Handle Wafer

Device Layer

Thick Epi Poly Layer

Handle Wafer

Bonded Si Wafer

Thick Epitaxial Si Growth Direct Bonding and Grind Back and CMP Polish

Figure 7. Two methods of fabricating device-layer SOI wafers. The left diagram shows a thick epitaxial growth approach, while at right a more complicated wafer-bonding/grinding/polishing approach is illustrated.

Such variations in operating frequencies may result in devices that operate outside the range of their control circuitry. Or conversely, more expensive control solutions would be required to accommodate the range in mechanical device frequencies. An ideal scenario would be where a high level of repeatability is achieved for the manufacture of the MEMS device such that a moderate-to-low cost application-specifi c IC can be employed to control it.

In contrast to other approaches, the enhanced 200mm Centura Epi platform enables greater within-wafer uniformity and repeatability for both thin and thick epitaxial silicon layers. Using Applied’s Epi Uniformity and Repeatability Kit, manufacturers can improve TTV for epitaxial silicon fi lms by as much as 30%.

The process kit, developed specifi cally for thick epitaxial silicon, includes a motorized wafer lifter to ensure accurate wafer placement; a newly designed tapered susceptor plate that benefi ts thin and thick fi lms by eliminating wafer movement and avoids “wafer bridging” issues commonly seen when growing very thick epi fi lms; and fi nally a new susceptor leveling tool that ensures repeated and accurate wafer positioning during post-chamber cleans.

These and other technologies help users achieve superior on-wafer performance and higher productivity versus other commercially available epi tools.




Figure 8. The two charts show thickness (left) and resistivity (right) results for a 100µm-thick epitaxial silicon fi lm grown across a 200mm wafer at a rate in excess of 5.9µm/min with Applied Materials’ enhanced 200mm Centura platform. The thickness nonuniformity and resistivity nonuniformity are both < 1%.

■ Wafer bridging: bridging, or sticking, has always been a concern when growing fi lms thicker than 20µm in any epi reactor.

■ Film quality and potential chamber coating: higher growth rates and longer process times may promote fi lm defects and chamber dome coating.

■ Repeatable wafer placement: after a chamber clean, susceptor leveling can a¥ ect wafer placement, which could decrease device performance and yield.

200MM CENTURA RESULTS AND PERFORMANCE

With more than 800 chambers installed worldwide, Applied Materials’ 200mm Centura Epi platform is well suited to help customers address these challenges. Summaries of the enhanced Centura performance in fabricating a 100µm-thick epi layer are shown in fi gures 8 and 9.

Developments such as thick epi fi lms on cost-e¥ ective 200mm tools will help bring about enhancements in the power semiconductors and MEM devices that are the prerequisites for today’s fastest-growing electronics applications. Applied Materials is working with device-level partners in the automotive and consumer markets

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Figure 9. The chart shows excellent on-wafer particle performance for the same 100µm-thick epitaxial silicon fi lm described in the previous fi gure. There were less than 20 particles (adders) >0.12µm across the 200mm wafer.

Repeatability1σ = 0.4%

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on next-generation devices that employ thick epi, and is continuously optimizing process and tool development to extend thick epi capabilities further.


NANOCHIP30

An emerging trend is for manufacturers to upgrade 200mm and 300mm tools to a new, more contemporary level of performance. Many economical, reliable and fully depreciated tools, fi rst commissioned in the early 2000s or before, are still used in a variety of applications where scaling isn’t the main goal. These tools are often candidates for upgrades and performance

Enhancing the capabilities and extending the useful life of existing semiconductor production equipment allows manufacturers to extend process capability, increase fl exibility and lower wafer cost.

BY TONY

MARTINEZ AND

WEI-JEN TSAI

BRINGING EXISTING TOOLSTO A NEW LEVEL OF PERFORMANCE

improvement adjustments that increase uptime and e¦ ciency, and extend their lifetimes.

For example, Applied Materials has done this with our 200mm Centura DPS etch tools. At multiple customer sites we have achieved more than twice—sometimes nearly three times—the mean wafers between cleans (MWBC) RF exposure time, signifi cantly increasing tool productivity.

NANOCHIP 31

GREATLY INCREASED TOOL PRODUCTIVITY

A case in point is one customer whose fab output was constrained during a transition to a new process mix. Following the introduction of the customer’s new process, their 200mm Applied Centura DPS Al metal etch system was experiencing particle excursion issues, leading to a low and unpredictable MTBC of 60–90 RF hours. In addition, the customer wanted to switch gases in one process step from a fl uorine-based gas (CHF3 with Cl2 and BCl3) to a nitrogen-based chemistry (N2 with Cl2 and BCl3), which required additional process modifi cations.

Applied Materials suggested an analysis by its FabVantage consulting group to examine the situation and recommend remedial actions. The FabVantage team included individuals with deep process and equipment knowledge who worked with the customer to evaluate the tool’s existing performance baseline and evaluate it against all relevant benchmarks, best known methods (BKMs) and best practices. Quantitative recommendations were then established for a series of process, hardware, and recipe performance improvements and fi rst implemented on a golden tool to validate them.

One recommendation was to use an enhanced dome temperature control unit (E-DTCU) to keep particle formation in the dome to a minimum. Other recommendations included:

■ Hardware: To further reduce the need for frequent chamber cleans, the existing polyimide electrostatic chucks (ESC) in the tool’s chambers were replaced by new ceramic ESCs, along with change-outs of the existing process kits to yttria-coated kits. Polyimide ESCs are susceptible to accelerated wear and buildup of organic residues, whereas ceramic ESCs are resistant to buildup and don’t attract as many deleterious chemicals.

■ Process: As part of this change, the in-situ cleaning was tuned and optimized for the ceramic ESC.

After implementing these changes on the golden tool, it was necessary to demonstrate process transparency. This was done by checking the etch rate and the etch rate within-wafer (WIW) uniformity on an Al etch process and by measuring the oxide loss on patterned wafers.

Figure 1. Etch contour maps showing the results of process transparency testing. Colors on the map indicte etch rate, angstroms/minute.

MTBC PERFORMANCE CURRENT RECIPE

Current HW Confi guration 60–90 RF hrs

Golden Chamber Enhancements > 100 RF hrs

Al Etch Rate Before Converting (PRE)

Al Etch Rate After Converting (POST)

Before and after E-DTCU converting. Al Etch Rate and WIW NU% matched.

PRE POST AVERAGE UNIF AVERAGE UNIF

3124.96 11.80% 3052.45 11.84%

Figure 1 shows the etch rate and uniformity for an Al etch process. In addition to the etch rate and uniformity being matched to within 1%, the etch rate profi le was preserved, as indicated in the wafer maps.

NANOCHIP32

BRINGING EXISTING TOOLSTO A NEW LEVEL OF PERFORMANCE

Figure 2. Cross-section SEMs of etch profi le before and after the changes. The left SEM in each pair shows a dense region on the wafer, and the right SEM shows an isolated region. Numbers in the table denote the amount of oxide removed in angstroms.

Etch Profi le Matching (3200Å Al)

PRE

POST

OX LOSS PRE

CENTER EDGE DENSE ISO DENSE ISO

PRE 370 634 385 664POST 355 637 368 673

Before and after E-DTCU converting. Pattern wafer profi le matched.

Figure 2 shows the etch profi le results, indicating amount of oxide removed. Oxide loss, as measured by scanning electron microscopy (SEM), was calculated in both dense and isolated regions of the wafer. Oxide loss matches were identifi ed to within 4% in the dense regions and within 1% in the isolated regions.

Together, these performance improvements have resulted in a more than 60% improvement in MTBC with no degradation in tool performance. They have also increased processing fl exibility in the fab, eliminating Al metal etch as a major source of the fab’s bottleneck.

WORKING TOGETHER FOR BEST OUTCOME

This project, the fi rst of multiple, ongoing engagements with this customer, is an example of how the FabVantage team can serve as trusted advisors and problem-solving partners for customers, helping extend tool performance to a new level, reduce fab constraints and lengthen the useful life of an existing manufacturing asset. In addition, it demonstrates how Applied Materials can apply the correct services and hardware solutions at all customer technology nodes and on a wide array of processes to help them fi nd ways to get more good wafers out the door at lower cost.

Ceramic electrostatic chuck.



Seehack Foo, vice president of the Applied Global Services (AGS) Semiconductor Service and Components group, defi nes ”service” as doing what it takes to enable customers’ success with their Applied Materials equipment. A 27-year veteran of the semiconductor industry, Foo was formerly vice president of Service Operations at KLA-Tencor. He spoke recently with Nanochip Fab Solutions (NFS) about our customers’ service needs and what he has in mind for AGS’s service and spare parts o¥ erings.

AN INTERVIEW WITH SEEHACK FOO

AT YOUR SERVICE

NFS: You joined Applied in this role at the beginning of the year. How’s it going? What have been your key priorities?

Foo: Coming into Applied has been an extraordinary experience—at times a bit daunting, but mostly exhilarating, energizing. There is so much here at Applied: incredibly smart people, spread out across the globe, and an unbelievably rich and diverse product and technology portfolio. In semiconductors alone, Applied has multiple o¥ erings in nearly a dozen di¥ erent technology areas, and our service organization—comprising more than 3,000 customer engineers [CEs] and 100 spares depots—supports all of them.

Applied is an industry leader with strong, established relationships with customers, and this is an exciting time to be in the service business. The complexities of chip manufacturing and the staggering costs of production facilities challenge our customers more than ever to accelerate and maximize yield, reduce cost and improve productivity. In particular, with the introduction of FinFET technologies and V-NAND, there are many new challenges that we can address with our service o¥ erings. Our service model is evolving signifi cantly to one that extends well beyond traditional equipment support practices.

Device complexity—new materials, and tight, tight process windows—means customers now look to us for advanced capabilities to monitor and fi ne-tune processes for optimum performance and more predictive operations. In particular, the introduction of new technologies or node upgrades represent challenges for our customers and this is where we can shorten the cycles of learning. Software-based monitoring and control systems, sensors, data mining and data analytics—especially predictive analytics—are becoming part of our services tool kit, helping us distill data and turn it into actionable information that increases predictability and good wafers out. All of this speaks to the need for a new class of service that helps resolve key customer challenges faster and more e¥ ectively.

My focus has been on determining what is needed to take service to this next level; to take a great service organization and make it even better, to deepen our current service o¥ erings, and to o¥ er world-class solutions that customers consistently trust and choose to help them create real value with their Applied Materials equipment.


Customers’ business strategies also come into play. In a way, no two customers have the same issues. For example, an IDM making high-performance, cutting edge devices will want to talk about ramping to high yields fast and with minimum output risk. A cutting-edge foundry might have those same concerns about fast ramp, but they want us to help improve yield predictability and output. A memory manufacturer, on the other hand, cares about cost reduction, optimized output and fast cycle time. So does a customer running a 200mm foundry, but they’re also concerned about managing obsolescence and will want to know how we can help them get scarce parts or update their system and process technology. And when we meet with customers making MEMS, power devices, TSVs and so forth, the list of challenges is long and varied—from node and technology transitions to tool and process optimization, equipment OEE and COO, and continuous improvement engineering support.

NFS: You’ve been around this industry for a number of years. How are customer support requirements changing?

Foo: When I fi rst started in this industry, device architectures were much simpler and the service problems were largely related to hardware reliability. We operated for years in a very reactive mode. Today the service model is very di¥ erent. With so much process complexity and the high costs associated with not resolving problems quickly, customers expect more from their service providers. They rely on advanced software and sensors, extensive libraries of BKMs and engineers specialized in both equipment and process to help detect, classify, diagnose, control, predict and prevent various failure modes that can impact on-wafer results—and also impact cost and productivity.

NFS: How are you preparing your organization to respond to these changing customer support requirements?

Foo: If we want customers to make AGS their fi rst choice when it comes to service, it follows that we must be a trusted, cutting-edge service organization with unique and growing capabilities that bring signifi cant benefi ts customers can’t readily get elsewhere.

We have made much progress in this direction but more needs to be done. We’re taking a hard look at everything we do—from the kind of service products we o¥ er, to where and how we source parts, to how our organization is structured and deployed around the world. We aim to operate more e¥ ectively, o¥ er greater capabilities, or run in ways that are faster, less expensive, and better aligned with the needs of our customers.

Within the past few months we have reorganized the Semiconductor Service and Components group to more directly align service and spares functions with Applied’s semiconductor systems divisions. This will create greater synergy and collaboration among product design, development and support teams and enable us to evolve technically deep service o¥ erings that more holistically address customer needs. As the business units release new products—for example, for ALD—we are developing our service o¥ erings before these products are released to our customers. These are not just basic maintenance procedures. O¥ erings to deliver fast time to yield and high-volume manufacturing are now being developed in parallel to the product.

Once the customer buys a tool, our service organization will probably help take care of it in one way or another for the next 15, 20 or more years. So we’ve got to constantly improve our performance to sustain and strengthen relationships with our customers. And we must be prepared to deliver comprehensive, continuously evolving services and spares o¥ erings that help resolve even their most challenging problems—those that impact device performance, yield and cost—at every stage of a product’s life cycle.

NFS: When you speak with customers, what are the main service issues on their minds?

Foo: All customers are working towards faster time to yield, improved and more predictable process performance and lower total cost-per-wafer-out. They are also introducing new manufacturing capabilities like hard mask etch or high-K metal gate that represent di¥ erent manufacturing challenges as they are rolled out into high-volume manufacturing. At the macro level all customers want the same things from us: fast, responsive expert help and quality parts that make their equipment and operations more productive, boost system performance, and lower their overall production costs. However, it’s di¦ cult to generalize because virtually every customer circumstance in this business is unique in its own way. Customers’ specifi c concerns lie on a broad spectrum of needs and there’s little room for “one size fi ts all” solutions.

At one end of the spectrum are customers who have viewed service as an adjunct to in-house resources when problems and maintenance requirements crop up. At the other end are manufacturers who view service more broadly, as a strategic tool that can help them better manage skyrocketing process complexity, time-to-market pressures and fab costs. Increasingly, those customers rely on technology-enabled services in their fabs and from their equipment suppliers for faster resolution of problems that threaten their productivity and costs.

“Software-based monitoring and control systems, sensors, data mining and data analytics—especially predictive analytics—are becoming part of our services tool kit, helping us distill data and turn it into actionable information that increases predictability and good wafers out."

AT YOURSERVICE AN INTERVIEW WITH SEEHACK FOO

NANOCHIP 35

Each production technology Applied o¥ ers has specifi c technical nuances, so it is clear that we cannot have a “one size fi ts all” strategy when it comes to servicing them. Therefore, we’ve formed new, technology-specifi c service business units (SBUs) that are tied to corresponding product development teams. For example, our CMP SBU works with the CMP systems design group, with shared goals related to new product design, equipment serviceability, CE training, parts specs and sourcing, and performance improvements.

Finally, we have an all-out e¥ ort under way to improve our operational e¦ ciency without sacrifi cing quality so that we can better meet our customers’ needs for services and parts.

NFS: Many customers traditionally have handled their service needs internally. Do you foresee a change in that trend?

Foo: Some customers have very capable in-house resources and handle most of their own support; some customers have relied more heavily on Applied for service. However, as tools and processes grow more complex we see more customers seeking help.

As the OEM, our service personnel are trained by the experts who designed the tools. With more than 30,000 tools installed, we have access to deep, comprehensive data from an exhaustive knowledge base, so we are learning about our tools all the time. We’ve also developed advanced diagnostic tools so we can pinpoint problems faster.

In addition, our product knowledge is always up to date, which among other benefi ts makes equipment upgrades and modifi cations that much easier. We provide our service engineers with state-of-the art diagnostics, in-depth training, expert resources and other tools that give them the ability to solve problems more quickly than others can do. And in our industry, there is absolutely no doubt that time is money.

NFS: By necessity, customers are always focused on costs—especially costs for spares. What are you doing to address their concerns?

Foo: First, we have to look at reducing total cost of ownership. Our prices may not always be the lowest, but our ability to reduce costs substantially on an overall basis by increasing device performance, yield and throughput can bring customers tremendous economic benefi ts by lowering their cost per good wafer out.

“Our data shows customers are more satisfi ed with longer term service relationships than with primarily transactional interactions, because their equipment tends to run better and their parts tend to last longer."

“We provide our service engineers with state-of-the art diagnostics, in-depth training, expert resources and other tools that give them the ability to solve problems more quickly than others can do. And in our industry, there is absolutely no doubt that time is money.”

That said, we understand the importance of price and availability of parts, consumable components and other necessary items. In order to truly be a trusted supplier for our customers, we must be competitive in this area. A new companywide e¥ ort is underway to strengthen Applied’s parts sourcing and qualifi cation capability with a particular emphasis on being located close to the customer. Our goal is to increase our o¥ erings of locally sourced parts, and repair and cleaning services.

NFS: Any parting thoughts, Seehack?

Foo: With every advance in semiconductors—a new node, new materials, new process methods—comes a greater degree of chip manufacturing complexity, whether the challenge is technology, time-to-market or cost. So I would like to see us forge deeper, longer term relationships with customers. The closer collaboration will enable us to better understand and anticipate their needs and deliver support solutions that resolve high-value problems faster.

Our data shows customers are more satisfi ed with longer term service relationships than with primarily transactional interactions, because their equipment tends to run better and their parts tend to last longer.

Customers also benefi t in a number of ways from the advance planning that comes with stable, longer term relationships. Costs are incurred more predictably, service quality and response times can be better, and from the service organization’s point of view it’s a more e¥ ective way to plan for customer needs. For example, ensuring parts availability is much easier when customer needs can be anticipated well in advance.

It’s really true that we will succeed only to the extent that we help our customers succeed. Therefore, our success lies in being a trusted partner who helps customers make their operations better and less costly on an ongoing basis, so that they can thrive in their markets. Working together in that way, we will move the industry forward.



CHANGING THE ECONOMICS OF SOLAR CELL MANUFACTURING

Applied Vericell Solar Wafer Inspection System accurately predicts solar cell e¦ ciency to deliver higher yields and lower costs.

BY BRENT AMES

Production yield and cell e¦ ciency are critical in today’s c-Si solar cell manufacturing market. Average selling prices are declining, so both wafer and cell manufacturers need to keep costs low while maintaining signifi cant R&D investments. Wafer manufacturers must deliver high-quality wafers at a competitive price; cell manufacturers must mass-produce high-e¦ ciency cells and maintain high production yields.

Solar cell manufacturing is consumable-intensive and operates on razor-thin margins. About 70% of the cost of manufacturing solar cells comes from raw materials such as polysilicon and silver. This makes it very important for manufacturers to avoid, or minimize the e¥ ect of, sub-par materials.

Average cell e¦ ciency, or power conversion rate, for a multicrystalline solar cell is about 17.5%. As manufacturers know, there is only so much space on a roof or so many acres of land that can be dedicated to solar power installations. This means that tiny percentage di¥ erences in e¦ ciency across arrays of hundreds of solar cells can add up to major competitive di¥ erentiation.

The need for better cell e¦ ciency drives the need for better quality wafers. Factories face a host of challenges in the quest for the best wafers. Only about half of all wafers are inspected automatically. Manual inspection is a

Applied Materials Cell Manufacturing Center of Excellence in Treviso, Italy.

NANOCHIP 37

game of chance, with only spot inspections instead of batch inspections. The cost of manual inspections is rising along with the cost of labor. Some automated mechanical inspection units have been known to generate false positive rates of up to 4%, negating return on investment for the end user. New processes and cell architectures present new types of defects—which typically cannot be detected during manual inspections.

INTRODUCING APPLIED VERICELL SOLAR WAFER INSPECTION SYSTEM

The Applied Vericell Solar Wafer Inspection System uses unique, proprietary

Micro-crack inspection

Thickness variation and resistivity

Coin stack cassette integrated

Automated loading

Lifetime Photolumi-nescence

Surface and geometry inspection

Saw mark detection

Yield analysis server

Sorting 6, 12, 18 bin

Figure 1. The Applied Vericell Solar Wafer Inspection System helps improve cell- and factory-production yields by using metrology modules to analyze eight variables on each wafer, including photoluminescence, before the wafer is processed.

image analysis and prediction algorithms to perform bare wafer inspection before cell processing begins. This fully automated system is the fi rst in the industry to integrate full wafer inspection, multiple inspection modules and a sorter—plus photoluminescence that can predict cell e¦ ciency—into a single tool. The ability to classify wafers by grade before production begins improves fi nal production yield and lowers manufacturing costs by eliminating bad or low-e¦ ciency wafers at the outset, before money is wasted manufacturing a cell that can’t be sold.

The Applied Vericell Solar Wafer Inspection System (see fi gure 1) uses multiple metrology

modules to collect information about wafer thickness, thickness variation (TTV), resistivity, shape, edge chips, stains, saw marks, microcracks, and crystal fraction. The system uses photoluminescence technology combined with advanced algorithms and proprietary image analysis to determine fi nal cell e¦ ciency before the wafer is processed. Photoluminescence is also used to identify wafers with impurities and dislocation defects.

This data allows c-Si solar wafer and cell manufacturers to optimize their manufacturing lines so they can produce the highest grade cells possible. Applied’s breakthrough technology has been proven to increase average factory cell yield by 0.2% and factory

production yield by 1%, resulting in potential annual savings of $750,000 to $2 million (USD).

The ability to predict cell e¦ ciency has long been a goal for the solar cell market. The Applied Vericell Solar Wafer Inspection System uses its algorithms and analysis to achieve high prediction accuracy. The algorithms use a broad set of inspection data, along with customized reporting, that allows manufacturers to identify a wide range of potential improvements. Combined with photoluminescence technology and the industry’s lowest false alarm rates for microcracks and saw marks, this tool is a unique o¥ ering in the solar manufacturing marketplace.

NANOCHIP38

The Applied Vericell Solar Wafer Inspection System loads bare wafers from coin-stack magazines or cassettes, then sends each wafer through an inspection line at the rate of one wafer per second. The tool first sorts the wafers based on customer-defined mechanical characteristics either after the wafering process is complete (wafer manufacturer) or before the cell manufacturing process starts (cell manufacturer). The system’s ability to predict e¦ciency lets manufacturers

sort starting material, bin materials with similar e¦ciency ratings together, and potentially scrap wafers that have a predicted cell e¦ciency that is below their minimum specification.

All data collected by the system is easily transmitted into databases and connected to manufacturing execution systems through standard interfaces. Automated notification helps factory managers and engineers identify yield issues quickly.

Figure 2. Study results showed strong correlation between cell e¹ciency that was predicted using the Applied Vericell Solar Wafer Inspection System, and cell e¹ciency measured after cell production was complete.

An important benefit of the Applied Vericell Solar Wafer Inspection System is that it has extremely low false alarm rates—less than .25%, compared to up to 4% for other tools—for saw mark and microcrack inspection modules. False alarms directly a¥ect factory yield, causing good material to be scrapped. If a tool runs 80,000 wafers in a day, scrapping just 4% of the wafers can potentially erase the return on investment from operating the inspection tool in the first place.

VALUE FOR CELL MANUFACTURERS

Cell manufacturers can use the Applied Vericell Solar Wafer Inspection System to spot-check the quality of incoming wafers from manufacturers, and to perform inspections themselves so they can grade incoming material by potential cell e¦ciency. They can reject low-quality wafers that can’t be sold early in the production cycle, thus eliminating wasted consumable and labor expense on unsellable material. Knowing the capabilities of each wafer lets manufacturers improve planning and control of cell product yield, and helps them optimize equipment and production lines to improve cell e¦ciency yields.

VALUE FOR WAFER MANUFACTURERS

The Applied Vericell Solar Wafer Inspection System o¥ers significant benefits for wafer manufacturers as well. By tracking batches or individual wafers, they can further use cell e¦ciency measurements to pinpoint

underperforming tools and ingots. Tool performance can then be modified to optimize ingot and wafer yield. Successful processes on the highest performing tools can be replicated across other tools, improving yield. Wafer manufacturers can use cell e¦ciency metrics to charge a premium price for high-quality wafers that have a known high potential. The ability to di¥erentiate with verified wafer quality before cells are manufactured improves planning and control of wafer product yield.

JOINT STUDY DEMONSTRATES PREDICTION ACCURACY

A study by Applied Materials and solar manufacturers Sun Edison (formerly MEMC Electronic Materials) and Gintech Energy Corporation showed that bare wafer prediction accuracy using multiple sensors is exceptional. Wafers from 12 bricks, 2,000 wafers in all, were tested. The wafers were indexed with laser marking. The Applied Vericell Solar Wafer Inspection System and predictive algorithms were used to forecast the final cell e¦ciency of each wafer after the manufacturing process. Once the wafers were manufactured into cells, end-of-line testing measured their cell e¦ciency. The result was a strong correlation between predicted wafer value and final measured e¦ciency. This correlation is expressed as mean average e¦ciency (MAE). Ideally, MAE will be .15% or less. MAE in these

Wafer Number

Act

ual C

ell E

�ci

ency

(nor

mal

ized

)

1.04

1.02

1

0.98

0.96

0.94

0.92

Measured and Predicted Eciency (stacked)

1 7 13 19 25 31 37 43 49 55 61 67 73 79 85 91 97 103

109

115

121

127

133

139

145

151

Measured E�ciency (normalized)Predicted E�ciency (normalized)

Predicted Cell E�ciency

Act

ual C

ell E

�ci

ency

(nor

mal

ized

)

1.04

1.03

1.02

1.01

1

0.99

0.98

0.97

0.96

0.95

Predicted E�ciency vs. Measured E�ciency

.095 .096 .097 .098 .099 1 1.01 1.02 1.03 1.04

MAE=0.08%


NANOCHIP 39

tests ranged between 0.08 and .1% (see fi gure 2).

Generally, a batch of wafers will have a small number of very high e¦ ciency wafers, with the majority falling somewhere in the middle, and then a “tail” of very low e¦ ciency wafers. Identifying this wafer tail allows manufacturers to reject very low e¦ ciency cells. As shown in fi gure 3, this tail consisted of wafers with e¦ ciency below 16.5%, totaling 1.75% of the wafer batch. In this example, a replacement or refund for these

low-e¦ ciency cells would be $.85 per wafer. Savings on cell processing would be $.55 per wafer. If a manufacturer scans about 25 million wafers per year, 1.75% of 25 million is 437,500 wafers, providing a total cost savings of $612,000—just by rejecting the extreme tail of the wafers (see fi gure 3).

In this study, the cell e¦ ciency average was 18.45% without sorting materials by quality. Predicting cell e¦ ciency improved cell e¦ ciency by 0.2%, from 18.45 to 18.64%. Figure 4

shows that this was achieved by sorting starting materials and binning low-quality materials together so they could be identifi ed and rejected.

CASE STUDY: GLOBAL WAFER MANUFACTURER ACHIEVES PRODUCTIVITY GAINS AND COST SAVINGS

In 2013, Applied Materials teamed with a leading global solar wafer manufacturer to evaluate the Applied Vericell

Figure 3. The Applied Vericell Solar Wafer Inspection System can identify the lowest performing “tail” of a given batch of wafers. Rejecting these wafers before they are processed into cells can provide signifi cant cost savings.

Solar Wafer Inspection System. During the 4-month program, more than 6 million wafers were processed using the new tool.

The Applied Vericell Solar Wafer Inspection System was installed in a fab that was experiencing production problems leading to yield loss. Using the system to measure the total percentage of yield loss by type of mechanical defect, the manufacturer determined that wafer thickness variations were a¥ ecting 8% of yield. Saw marks were a¥ ecting another 10%.

Figure 4. Wafers that do not meet cell e¹ ciency standards can be binned together and rejected as a batch. In this study, eliminating three bins of the lowest performing wafers reduced costs and improved average factory cell e¹ ciency from 18.45 to 18.64%.

18

17

16

15

14

13

12

Cell E�ciency Prediction

137 73 10

914

518

121

725

328

932

536

139

743

346

950

554

157

761

364

968

572

175

779

382

986

590

1

1.75% ExtremelyLow E�ciency

300

200

100

0

Normalized to 1,000 Wafer Lot

Bin

Freq

uenc

y

Frequency

161 6 5 16 13

27 31 4570

105

152

205179

53

4 0

700

600

500

400

300

200

100

0

Advanced Wafer Binning Distribution

Bin

Freq

uenc

y

Frequency

16

139

297 272

583

171

434

0 0

1 2 3 4 5 6 7 8 MoreBins 1-3 are rejected;the factory will only

process bins 4-7

19.5

19

18.5

18

17.5

17

16.5

16

Elimination of bins 1-3 improves average factory cell

eciency from 18.45% to18.64% and lowers costs

178 15

523

230

938

646

354

061

769

477

184

892

510

0210

7911

5612

3313

1013

8714

64 1541

1618

1695

1772

1849

Before SortingAfter Sorting

NANOCHIP40

The Applied Vericell Solar Wafer Inspection System uses advanced analysis software to identify root causes of yield loss. By comparing yields of identical equipment within a single process, managers were able to identify a single wire saw that was causing 10–20% more defects than other saws (see figure 5). They also identified two saws that were causing yield loss due to thickness variations. Photoluminescence inspection, unique to the system, identified two poorly performing ovens that were causing 0.24% cell e¦ciency loss. The system also analyzed and compared wafer performance by the wafer’s original location in a cast ingot, determining that certain locations in the ingot had higher levels of impurities.

The end results of this evaluation identified key areas for factory-wide yield improvement, using cell e¦ciency prediction and an upgrade from manual inspection to automated inspection. The Applied Vericell Solar Wafer

Figure 5. The Applied Vericell Solar Wafer Inspection System identifies underperforming tools by comparing yields of identical equipment within a single process. In an evaluation with a global wafer manufacturer, the system discovered that a single wire saw caused 10–20% more defects than other saws.

Inspection System used proprietary yield management software to identify equipment that was performing poorly. The ability to accurately predict cell e¦ciency allows the manufacturer to sort and re-melt low-e¦ciency wafers, reducing waste and costs and improving overall shipped wafer quality. Minimized manual handling

lowered labor costs and helped reduce breakage, improving yield. The manufacturer estimates a gain of 12.5% in productivity versus other automated inspection systems and has improved profits by about $156,000 per machine. For geometry measurements, the manufacturer estimates a savings of $31,000 per year by using automated instead of manual inspections.

NEW TECHNOLOGY DELIVERS A COMPETITIVE EDGE

The solar cell market is at an inflection point for costs and technology. When the market was young, manufacturers focused on expansion and quantity. Eventually, as has happened in many other technology markets, producers found themselves

facing dropping demand and overcapacity. Some companies found that it was cheaper to shutter factories rather than run them at a loss. As the solar industry matures, factories now are focusing on yield and process improvements. Instead of mixing good and bad materials to achieve a working average e¦ciency, solar wafer and cell manufacturers are at a point where they must drive yield improvements within the factory and place greater emphasis on quality. Tools such as the Applied Vericell Solar Wafer Inspection System are playing a critical role in delivering the e¦ciency, cost and quality improvements solar manufacturers need to compete and thrive.


100

90

80

70

60

50

40

30

20

10

0

Percentage of Saw Mark Yield Loss by Wire Saw

Wire Saw Tool ID

Perc

ent Y

ield

A B C D E F G H I J K L M N O P Q R S T U V W

Class Saw Mark

0 No result

1 <5 µm

2 5-15 µm

3 15-25 µm

4 25-35 µm

5 >35 µm

Applied’s wafering applications and cell manufacturing lab in Xian, China.



The Advanced Semiconductor Manufacturing Conference (ASMC) celebrated its 25th anniversary in Saratoga Springs, New York, in late May, with a record 308 participants enjoying the spectacular spring weather while refl ecting on the considerable challenges facing the semiconductor industry.

Mukesh Khare, director of research at IBM’s semiconductor division, kicked o¥ ASMC with a keynote that provided plenty of optimism on the technology front. After silicon FinFETs come silicon germanium FinFETs, nanowires in a gate-all-around architecture, and then carbon nanotubes (CNTs) with their spectacular mobilities. IBM has long been bullish on CNTs. (Gartner analyst Dean Freeman is more skeptical, saying “using CNTs is like trying to line up worms on a wafer.”)

“The technology roadmap is very rich, and can continue for a good period of time,” Khare said. IBM believes its 10nm technology will involve fi fth-generation ArF lithography with sidewall image transfer technology. “It took the industry 15 years to develop high-k,” he added. “EUV lithography is another technology that will take a lot of resources, but it is coming together.”

Charlie Pappis, vice-president and general manager of Applied Materials’ Global Services business, said while traditional patterning shrinks have become more di¦ cult, “the industry has changed the innovation equation to new materials and the third dimension [vertical, 3D structures] out of necessity, as we get to sub-ten nanometers.”

we can improve the e¦ ciency of design by using leading-edge transistors more creatively. Older fabs can also be upgraded and improved, partly by networking tools and analyzing the big data streaming from 200mm and 300mm production tools.

It used to be harder for semiconductor-related companies to raise money due to the cyclicality of the industry. Pappis said that DRAM cycles often exacerbated the industry’s ups and downs, noting that even the traditional seasonality swings have modulated. Instead of manufacturing volumes rising solely to meet consumer demand during the Christmas season, the Chinese New Year is exerting its own pull. “Our focus on Western ways is going away, as demand rises in other parts of the world, especially in Asia,” Pappis said.

The attention paid to consumer trends carried over into a closing presentation by Gartner’s Dean Freeman. “The consumer is king, so if they get scared things could change. But we see a pretty nice year shaping up,” he said. Capital expenditures should increase by 5.6% on average in 2013–2018, with an increasing share going to packaging.

And as low-cost devices aimed at Internet of Things (IoT) applications begin to reach higher volumes, it will put new life into 200mm fabs. By 2020, about seventeen 200mm fabs, each capable of 50,000 wafer starts per month, will be required to produce the devices needed for the estimated 10 billion “things” going into IoT applications. “The IoT should help the underutilized fabs around the world. Right now, we count 20 shuttered 200mm fabs, and some of them could be put back into service if our scenario of a reasonable—but not spectacular—growth rate for the IoT occurs,” Freeman said.

I could barely count all the new fab lines being built now by TSMC. In his ASMC keynote, John Lin, general manager of operations at the G450C center in Albany and a general manager of operations at TSMC, described a fl urry of investments. These fabs will be “nearly people-less,” Lin said, with 80–90% of the operators working in glassed-in control rooms, monitoring the production lines.

A TSMC fab can have about 1,000 di¥ erent products underway at any one time. The company builds about 4,000 new masks a month. To keep improving, the foundry is building what Lin called a “big data neural system.”

“We want to feed [data] forward and feed backward in an integrated manufacturing system, including design and packaging,” he said.

GLOBALFOUNDRIES has similar goals. Dave Gross, in charge of automation technology, said networks between the fabs and suppliers are expanding, even as security concerns continue. “It used to be that not one bit of data could go outside the fab. Not one bit. Now, we stream data constantly.”

David Lammers is an Austin-based technology journalist.

THE

LAST

WOR

D

DAVID LAMMERS

MATERIALS, LITHO, MANUFACTURING AND MONEY TOP ASMC THEMES

Mukesh Khare, director of research, IBM semiconductor division

Robert Maire, president of Semiconductor Advisors, LLC.

Dean Freeman, Industry Analyst at Gartner

ECONOMIC CHALLENGES LOOMUntil the 28nm node, the chip industry has consistently been

able to “double the number of transistors for the same number of dollars,” said Robert Maire, president of Semiconductor Advisors, LLC. Maire summed up the core cost problem nicely, noting that as double patterning became necessary at the 28nm node, “the industry fell o¥ the [cost-reduction] wagon. We need to fi x or replace EUV. Wouldn’t it be nice to have direct-write lithography, so we wouldn’t need a $5 million mask set?”

Since 1965, Moore’s Law has been translated into economic terms, as companies were able to reduce the cost-per-function by about 25–30% per year. Getting back on that cost-reduction curve is the key problem as scaling continues to move ahead. To be sure,

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