nanoFabricChang Seok Bae

nanoFabric nanoFabric : an array of connect

nanoBlocks nanoBlock : logic block that can be

progammed to implement Boolean function and switches to route signals

Using CAEN (chemically assembled electronic nanotechnology) requires new computer architecture

Next: fabrication/architectural implication and overview on the architecture

Fabrication and Architectureal Implications Plausible fabrication process

Wires of different types are constructed through chemical self-assembly

Aligns groups of wires Silicon-based die

Self-assembly (alignment) restriction A post-fabrication configuration Bypassing defect density

Fabrication and Architectureal Implications (cont) Two-terminal device (diode-resistor

logic) Three-terminal device is unsuitable with

inexpensive chemical assembly No inverter: output and its complement

Signal restoration and registers Lack of transistor CMOS: density problem and speed down Molecular latch: composed of a wire with

two inline NDR (negative difference registers) at either end

NanoFabric architecture

nanoBlock nanoBlock connectivity Scalability Defect Tolerance Configuration

nanoBlock

Fundamental unit MLA (molecular

logic array) : functionality of block

Latches I/O area:

connect the nanoBlock to its neighbors

nanoBlock (cont)

MLA Two orthogonal sets

of wires: when configured to be “on”, act as diodes

Benefit: construted by direct assembly

Drawback: signal degrading, so molecular latch is used

nanoBlock Connectivity

Fabrication constrain bring each side of block to have inputs or output but not both: one diagonal

Switch block: input/output overlap

Scalability

Arrangement of clusters and long-wires Routability of netlists

as the number of components increasing

Configuration time to be remained due to parallel configuration

Defect Tolerance Defect-tolerant nature

Regularity: choose where particular function is implemented

Configurability: pick one component (nanowire, parts of nanoBlock) which implements particular circuit

Fine-grained nature: reduce the impact of a defect to a small portion of the fabric, which enriches interconnection overhead

Key difficulty: impossible to test the individual components in

isolation Teramac: inconjuction with an outside host to test

itself

Defect Tolerance (cont)

Defect mapping process Phase I: no known fault-free regions

Basic tester implemented in CMOS Host computer configures testers

Phase II: After a sufficient number of functioning resources discovered

Already tested area of the fabric acts as a host for testing the remainder

For very large devices, many parallel independent device used

Configuration

Molecular switch : high voltage outside the normal operating

range Configuration

Fabric scale: Fabric is design so that clusters can be programmed in parallel

Cluster scale: configuring one nanoBlock per cluster due to CMOS overhead

nanoBlock scale: Accessing each nanowire separately not in space but in time dimension

SAM simulation

To exploit the advantage of nanoFabric, SAM (a split-phase abstract machines) is proposed and simulated.

Comment: this simulation is approached at highest level away from the circuit constraints.

Conclusion

Even though this approach exploit the parallel nature of chemical assembly, fine-grained style brings high complexity of configuration to implement functionality or fault tolerance

There are still many challenges left in creating functional computing device