nanoscale system design challenges: business as usual? · novel industry-university system r& e...

Nanoscale System Design Challenges: Business as Usual?

www

Hugo De ManK.U.Leuven / IMEC

[email protected]

© H.De Man/IMEC ESSCIRCDERC02 2

Outline

• Post.com and Post-PC?

• Design challenges?

• Research and education: business as usual?


Post-PC: 3rd generation of computing...

Mainframe

Data processing

1000

+Networking

+DSP (MM)

PC1

10

Smart Things>100 #

AmbientIntelligence

1

/ human

chips / thingDisruptiveDisruptiveTechnologyTechnology

0.01

60 70 80 90 00 10


Ambient Intelligence [Weiser,Aarts]

1. Wireless WAN-LAN network delivers infotainment, communication, navigation... anyplace, anytime, for every citizen…

2. Hidden, pervasive computing. IT to background, people in the foreground, improves quality of life in non-invasive way...

3. Things see, listen, feel, become sensitive and adaptive to people…


AmI is a 4 in 1 system

Embedded, ubiquitous, distributed wearable computing

Ubiquitous wireless communication

Proactive, intuitive non-keyboard user interface

Distributed Transducer systems (MEMS & BIO sensing)


Ambient Intelligence Global System

WLANBasestations

<1W,10Gops > 100 Mbps

C RF

www

AD

AD

SoC-SiP(Wearable) Assistant

seehearfeel

• biometric input• global connectivity• multimedia, games • QoS• gps• augmented reality• health, security

1000 m 10m

TCRF

TCRF

WBANBody Transducers

100µW - (k)bps

1m 0.1-2W10..100Gops

RF

1/person

>100/person aura

T C RF

WPAN Ad-Hoc Network of Picocell Ambient Transducers

100µW, 1Gops peak(k)bps

T C RF

Ambient

10m

T:transducerC:basebandRF: radio link

WANspeakshow

stimulate


Computational Complexity > MooreResult of :Communication:

Shannon limit (>>bps/Hz.W) -> coding (Turbo, SDMA…) 1G = 10 Mops -> 3G = 6000 Mops

MPEG 4 OO coding-decoding (>5 Gops)Intelligence and Human Interface:

Context awareness, self learningSpeech recognition, Biometrics=AI search (100Gtrs)3D Graphics, games, video indexing (100 Gops[1][2])

All described in software IP (C, C++, Java, MATLAB)(not really clean Models of Computation!!)

[1] Nakatsuka (Toshiba): isscc 1999, pp16-19[2] Boekhorst (Philips) : isscc 2002. pp28-31


Driven by Technology Convergence

1960 1970 1980 1990 2000 2010 2020 2030

1 mm

1 nm

DSM-Technology

Nano-Technology30 nm

Micro Micro NanoNano ConvergenceConvergence

SocietalSocietalNeedsNeeds

Mems & BioSensors/Actuators

Packaging

EmbeddedEmbeddedSoftware TechnologySoftware Technology

Intelligent, adaptive 1 chip systems

1000 processors50MB memory

“Ambient“AmbientIntelligence”Intelligence”Giga-Complexity

Nano-Electronics


Outline

• Post.com and Post-PC?


“ Not process technology but our inability to masterthe Giga-complexity of Nano-systems may prove

to be the showstopper to Moore’s law”


Nano-systems with Giga-complexity

Transducer nodes

Ultra low energy (100Mops/mW)Ultra low cost (1€)1..10 Mtr (small size)Low flexibilityDSP&RF dominatedChip-package co-designUltra fast hw design

Assistant nodes/basestations

Low energy (10-50Mops/mW)Low cost (100 €)10..100 Gops, >100 MtrHigh FlexibilityData-Intensive, dynamic tasksTask and data concurrencyIncremental sw design

@100..500 times Power efficiency of today’s µP...“ASIC in a week” “PLATFORM”

Need global system optimisationGHz RF and mixed signal everywhere


The Energy-Flexibility ConflictPower efficiency (MOPS/mWatt) Source: T.Claasen et al. (ISSCC99)

Intrinsicpowerefficiencyof 32 b silicon

microprocessors

2 1 0.5 0.25 0.13 0.07feature size(µm)

1000

100

10

1

0.1

0.01

0.001

ISProcessorsreconfigurable computinghardwired muxed

DSP-ASIP’s

AmI


Challenge#1: Disruptive Architectures

• Novel 4G radio architectures (BWRC,WWRF)

• Reach intrinsic power efficiency for domain specific programmable, memory dominated platforms!

Need a “software washing machine”Spatial/temporal localisation of data production/consumption

On top of a multiprocessor platformBetter 100 processors@200MHz than 1 @20GHz RTOS controls Fcl and VDD and leakage(!) power (circuits!)Communication driven design


Software Washing Machine [Catthoor, IMEC]

Platform independent global source to source transformations for data-intensive applications save power!

IN: Dirty C++ software IP’s + scenario

OUT: Cleaned Concurrent C++ tasks OUT (SYSTEMC)

Platform specific compiler

Data optimisation (type, parallelism)

Task Concurrency management (static)

Transformations tominimize data-transfer & storage (DTSE)


DTSE impact on uniprocessor power...MPEG-4 decoder performance on x86 for CIF 25fps 384Kbps

0

25

50

75

100

125

150

175

150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900

MHz

Fram

es p

er s

econ

d

DTSE floatDTSE intDTSE mmxFDIS floatFDIS intFDIS mmxx86 intx86 mmx

Importance of software washing for low power!

Bormans-Catthoor IMEC

unwashed

float

mmx

DTSE

data //x86opt


+ RTOS to control (VDD Fcl VT)

2V

0.6V

0.18 µmVDDmax=2VVT=0.35V

maxmaxmax2max

2

max

max

maxmax

.DD

DD

TDD

TDD

cl

cl

DD

DD

DD

DD

TDD

TDD

cl

cl

VV

VVVV

ff

VV

PP

VV

VVVV

ff

α

α

−−

==

−−

=

Run MPEG4 @ 1/50of power on x86


A jump for IS processors…Source: T.Claasen et al. (ISSCC99)

microprocessors

2 1 0.5 0.25 0.13 0.07feature size(µm)

1000

100

10

1

0.1

0.01

0.001

Computing efficiency (MOPS/mWatt)

ISProcessorsreconfigurable computinghardwired muxed

AmI

for 1 task


Challenge#2: Use parallel architectures

Also leads to energy efficient computation

energycycle

λ/2

+ +

+ +

+ ++ ++ ++ ++ ++ ++ ++ +

store5

work1 4

λ/2

++ + +

++ + +++ + +

++ + +

1/4

4

store

λ

1

Task/Data parallelism -> multi-”processor”


Also dictated by DSM wiring delay...50nm Cu lines with tw = 20% clock period

Clock Frequency (MHz)

Wid

th Is

osyn

ch z

one

(mm

)Layer 3,4

Layer 1,2

Based on Table 2, p11 Khatri,Brayton,Sangiovanni

Below 100nm isochronous zones < 2*2 mm2


Architectures today?

From ASIC’s -> Platform based design. “Today’s platform is yesterday’s board”

Fixed Hardware Kernel

Variable Region

sw hw

rc

pe io

Bus-Based

Hard IP

Softapplication IP

CompilerRTOS

Hard to scale, hard to compile into: what in sub 100nm?Need New “Mead-Conway” idea: regular, scalable, simple...


Sub 100nm programmable platform

• Regular network of programmable / reconfigurabletiles 2*2mm2 clocked at low freq (O(500 MHz))

Tile: 4 M transistors (ASIP processors, memory)Locally synchronous, globally asynchronousLow data-rate communication over packet switched network using predictable wiring fabricOS driven power management / tile (VDD, Fcl, IDDQ)

• Life cycle extendable by incremental software development and remote reconfigurability

Networked adaptive computing machines


Networked Adaptive Computing Machines

Subnetworks for compute intense concurrent tasks (brain zones)

Packet switching, low swing MD network [5A]

I/O

peripherals

4M

MemoryHierarchy

PE

ME

DynRCPASIP

ConfigurationProgram

Data

Com

m. Pow

erC

onf.Test


Regular Wiring Fabric[Khatri,Brayton,Sangiovanni: Kluwer 2001 0-7923-7407-X ]

S SV V SG

SG

SSV

V

SS SSVV VV SSGG

Example: repeating Example: repeating dense wiring fabricdense wiring fabricpattern at minimum pitchpattern at minimum pitch

-- Eliminates signal integrity, delay uncertainty concernsEliminates signal integrity, delay uncertainty concerns-- Reduces power bounceReduces power bounce-- Manufacturing friendlyManufacturing friendly


Challenge#3: The devil is in the software

Scenario {Sw IP legacy}Sw Washing machine

Hw-Sw // Task MappingRun-time reconfig / progr

Run-time Power management

Middleware (Hw/Sw Virtual machine)

Conf. & Program Memory Map

Hw IPProtocols

RTOS

network

terminal


Outline

• Post.com and Post-PC ?


• Research and education: business as usual?


The gain is at the top!(After Kienhuis)

Software Washing M

Architectural Exploration

Platform dep. Trafo’s

Cycle Accurate Hw/SwModels

VHDLModels

Opp

ortu

nitie

s

Cos

t of M

odel

ing

High Low

HighLowHw/SwPlatform

Soft IP + scenario’s MoA

Explorere

sear

chno

w


Bottleneck: filling the architectural gap! UML

cC++, JAVAMATLABSystem specs -> 7th Heaven of software

x[i]=fft(4πy[k])...

SA

HDL

10-100GOPS/Watt

DS Hell of Physics

200M+ transistors200M+ transistorSoC Architecture

PhysicalGapEDA,VSIA,IP

ArchitecturalGap

People & Methods

MultidisciplinarityNew methodologies

New abstraction layers


But pyramid tops are domain specific!

Wireless Multimedia Networking Automotive

TmediumRFADDSP

StreamsStorageArithmDDF

ADTStorageSearchDynamic

SensorsScalarsReactiveCF

Discover the common ground -> EDAThe tops -> design your design system!


So...Who will create the innovation?

Universities

4y

0y

7y+ Team+ Global - Ad-Hoc- Secretive

+ Formalization+ Long term+ Open- Structure

Systems Industry

-Diversity of SoC market-Incremental = $ -Methodology = Edu

EDA Industry


Escaping the deadlock...

• Novel industry-university system R& E structure• Multidisciplinary team based and open system research • Its mission:

“Building the top of pyramids on the foundation of the EDA industry and on knowledge acquired from challenging

system design experiments”

People and methods first…tools later


Networked System Design R&E Centers:

System Theme

ChampionUNIVERSITIES

IT

CS

EE

> 5 acad.staff> 20 Ph.D.> 30 M.Sc.> 10 Residents

DemonstratorPublications

SoCE’swww.methodsTools, "IP”,

patents start-up's

Gvt.

INDUSTRIALaffiliates

Residents$

Tools, IP, infrastr.


Examples

• 4G + Human++ @ IMEC + Univ• Embedded Systems Institute Eindhoven• Alba Project, Scotland• Berkeley Wireless Research Center• Gigascale Silicon Research Center• STARC...


Conclusions

• Post-PC differentiator: energy efficient mixed signal PLATFORM + PROGRAMMING environment

• The devil is in the software and linking it to DSM scaling effects (leakage, signal integrity, substrate noise…)

• Availability of skilled SoC engineers may be the showstopper toMoore’s law…multidisciplinary R&E needed

• Concurrent open research in SoC - SiP design by network of system design centers, industry and universities…Moore insists...


Business as usual?

“Progress will be in the merger of previously unconnected techno-cultures

driven by society needs“


Thank YouSystemDesign

SiliconIP

SiliconProcess

LifeSciences

SOCIETY

AmISystem

nanoscale system design challenges: business as usual? · novel industry-university system r& e...

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