nanotechnology fueling moore's law - stmik jakarta sti&k
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Nanotechnology Fueling Moore's Law
Koji Shiro
Director & General ManagerTechnology & Manufacturing Group-Japan
INTEL KK
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Outline
Key MessagesWhat is Nanotechnology? Nanotech State of the ArtThe FutureThe Ultimate Vision SummaryQ+A
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Key MessagesNanotechnology is here today in “state of the art” high speed Si CMOS process technologies
Si nanotechnology process scaling/convergence will continue for the next 10-15 years
Alternative new technologies have emerged and will begin to be integrated into Si CMOS by 2015
Nanoscience research is needed to facilitate these radical new scalable technologies beyond 2020
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What is Nanotechnology?
a. New structures like carbon nanotubes
b. Silicon devices made smallerc. Arranging atoms and moleculesd. Letting atoms assemble themselves e. Something far in the futuref. In production todayg. All of the above
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NSET* Nanotechnology Definition (Feb 2000)Research and technology
development at the atomic, molecular, or macromolecular levels, in the length scale of approximately 1 – 100 nanometer range
**National Science and Engineering Technology CouncilNational Science and Engineering Technology Council
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Silicon Nanotechnology is Here!
1000010000
10001000
100100
1010
1010
11
0.10.1
0.010.01
MicronMicron NanoNano--metermeter
1970 1980 1990 2000 2010 2020
Nominal feature sizeNominal feature size
NanotechnologyNanotechnology
130130nmnm9090nmnm
7070nmnm5050nmnm
Gate WidthGate Width
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Silicon Devices Shrink to Virus Size
50nm 100nm
Influenza virusInfluenza virusSource: CDC
Transistor for Transistor for 90nm Process90nm Process
Source: Intel
Source: CDC
Source: Intel
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Moore’s Law In Action
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1970 1975 1980 1985 1990 1995 2000 2005 2010
4004
80808086
8008
Pentium® Processor486™ DX Processor
386™ Processor286
Pentium® II ProcessorPentium® III Processor
Pentium® 4 Processor
Heading toward 1 billion transistors in 2007
Itanium® Processor
>220>220M Transistors Integrated Into M Transistors Integrated Into Devices Produced TodayDevices Produced Today
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>6 Orders Of Magnitude Reduction in Cost/Transistor
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
'68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02
$$
Source: WSTS/Dataquest/Intel, 8/02Source: WSTS/Dataquest/Intel, 8/02
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New Materials, Devices Extend Si Scaling
GateGateSilicideSilicideaddedadded
ChannelChannelStrainedStrainedsiliconsilicon
ChangesChangesMadeMade
FutureFutureOptionsOptions
HighHigh--kkgategate
dielectricdielectric
NewNewtransistortransistorstructurestructure
TransistorTransistor
Source: IntelSource: Intel
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New Materials, Devices Extend Si Scaling
Source: IntelSource: Intel
Metal linesMetal linesAl CuAl Cu
InsulatingInsulatingdielectricdielectric
SiOSiO22 SiOFSiOF
CDOCDO(low(low--k)k)
ChangesChangesMadeMade
FutureFutureOptionsOptions
Ultra Ultra LowLow--kk
DielectricDielectric
InterconnectsInterconnects
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The Future
Continue CMOS Nanoscaling Non-classical CMOSConvergenceNovel devices
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Nanotechnology features
Structures measured in nanometers–Less than 0.1-micron (100nm)
New materials and device structures–Incrementally changing silicon
technology baseMaterials manipulated on atomic scale–In one or more dimensions
Increasing use of self-assembly–Using chemical properties to form
structures
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Intel Nano Transistors90nm Node
2003
30nm Prototype (IEDM2000)
20nm Prototype(VLSI2001)
25 nm
15nm
1515nm Prototypenm Prototype(IEDM2001)(IEDM2001)
65nm Node2005
32nm Node2009
Increasing leakageIncreasing leakage
22nm Node2011
1010nm Prototypenm Prototype(ITJ 2002)(ITJ 2002)
45nm Node200750nm Length
(IEDM2002)
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Nanotechnology for Gate Dielectrics
Integration is the key challengeIntegration is the key challengeIntegration is the key challenge
9090nm processnm process1X1X1X1X
Experimental highExperimental high--kk1.6X1.6X
< 0.01X< 0.01XCapacitanceCapacitance
LeakageLeakage
Silicon substrateSilicon substrate
GateGate
3.03.0nm Highnm High--kk
Source: IntelSource: Intel
Silicon substrateSilicon substrate
1.21.2nm SiOnm SiO22
GateGate
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Lithography Gap to Close with EUVL10001000
100100
1010’’8989 ’’9191 ’’9393 ’’9595 ’’9797 ’’9999 ’’0101 ’’0303 ’’0505 ’’0707 ’’0909 ’’1111
Initial ProductionInitial Production
Feature sizeFeature size
157157nmnm
1313nm (EUVL)nm (EUVL)
Lithography Lithography WavelengthWavelength
193193nmnm248248nmnm
GapGap
nm
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EUV LLC Consortium Demonstrates EUVL
5050nm Lines Printednm Lines Printedwith EUV Lithographywith EUV Lithography
EUV EUV LithographyLithographyPrototype Exposure ToolPrototype Exposure Tool
EUV lithography is now in commercialization phase
EUV lithography is now EUV lithography is now in commercialization phasein commercialization phase
Source: Source: SandiaSandia
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EUV Reflective Mask Structure
Conventional optical photomask13nm EUV
light
Low Thermal Expansion Substrate
Absorber
SiSi (~4.1nm)(~4.1nm)
Reflectivemulti-layer coating
40 pairs Mo-Si
Mo (~2.8nm)Mo (~2.8nm)
Bufferλ
6” Fused silica substrate
λ
Light source
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The Future
Continue CMOS Nanoscaling Non-classical CMOSConvergenceNovel devices
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Intel’s TeraHertz Transistor:Lower Ioff Leakage
Raised Raised Source/Source/DrainDrain
< 30< 30nm Siliconnm Silicon OxideOxide
GateGate HighHigh--k k GateGate
DielectricDielectric
Fully Depleted Substrate: Subthreshold Leakage is Approaching Theoretical Minimum
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Experimental Tri-Gate Transistor
SourceSourceDrainDrain
GateGate
Source: IntelSource: Intel
GateGate
SiliconSilicon
DrainDrain
SourceSource
Improved version of TeraHertztransistor– Better performance– Scalable to smaller sizes (low leakage)– Possible intercept towards end of decade?
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Nanotubes/Nanowires( >> 2010?)
Collaborations with universities in progressGood individual device data, many integration and materials issues to be resolved
Source: Morales & Source: Morales & LieberLieber, Science , Science 279279, , 208 (1998)208 (1998)
Silicon Silicon NanowireNanowire
Carbon Carbon NanotubeNanotube
S
DG
2 2 to 20 nmto 20 nm
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The Limits of Logic Scaling
For an arbitrary switching device made of of a single electron in a dual quantum well–Operating at room temperature
It can be shown a power dissipation limit of 200 W/cm**2Will limit the operational frequency to ~100 GHz at length scales ~ 4 nm
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The Future
Continue CMOS Nanoscaling Non-classical CMOSConvergenceNovel devices
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Marriage of High Speed Logic with Other Technologies
{{ TodayTodayFlash/DRAMRF
MEMS/NEMSOptoelectronicsBioelectronicsAlternate memory –MRAM, FeRAM, Ovonics
{{ FutureFuture
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Intelligent Silicon
EXPANDING
EXPANDING
EXTENDING MOOREEXTENDING MOORE’’S LAWS LAW
WirelessWireless
OpticalOptical
BiologicalBiological
SensorsSensors
FluidicsFluidics
MechanicaMechanicall
NanoNano
Silicon Innovation Enabling ConvergenceSilicon Innovation Enabling ConvergenceSilicon Innovation Enabling Convergence
ExpandingExpanding the Silicon the Silicon CanvasCanvas
NanoNano is is HereHereNew New DevicesDevices, ,
MaterialsMaterials, and , and ProcessesProcesses
SSISSI LSILSI VLSIVLSIDiscreteDiscrete
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The Future
Continue CMOS nanoscaling Non-classical CMOSConvergenceNovel devices
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Novel Devices:R+D Time Requirements
Product development spectrum– Software– System– Assembly– mArch– Power delivery and cooling– Circuit Design– Layout– Processing– Materials
Change that affects one level or two adjacent levels is relatively easy to manage 2-5 years R+D effort
Change that affects many levels is very difficult 6 – 20 years R+D effort
– Must coordinate all changes– Long lead times
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Emerging Research Architectures
ATURITY
~2009?~2009? 2015++2015++
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Technical criteria
CMOS compatibility Energy efficiencyScalability Performance Architectural compatibilitySensitivity to parametric variationRoom temperature operationStability and reliability
Option Must Be Superior to Option Must Be Superior to Si Si CMOS Based CMOS Based On Cost, Power, PerformanceOn Cost, Power, Performance
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The Ultimate Vision
The brain is the ultimate model for its ability to deal with complexity
Little understanding on its architecture & organizationCompared to tomorrow’s computers – Orders of magnitude more powerful – Self assembled– Parallel operation– Self repairing to a significant degree– Fault tolerant– Runs on ~ 10W– 3D
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Summary
Nanotechnology is here today in “state of the art” high speed Si CMOS process technologies
Si nanotechnology process scaling/convergence will continue for the next 10-15 years
Alternative new technologies have emerged and will begin to be integrated into Si CMOS by 2015
Nanoscience research is needed to facilitate these radical new scalable technologies beyond 2020