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<ul><li><p>NATIONAL RADIO ASTRONOMY OBSERVATORY</p><p>CHARLOTTESVILLE, VIRGINIA</p><p>ELECTRONICS DIVISION INTERNAL REPORT No. 187</p><p>THE NRAO VLBI MARK II PROCESSOR</p><p>B. MEREDITH AND B. RAYHRER</p><p>JUNE 1978</p><p>NUMBER OF COPIES: 150</p></li><li><p>INDEX</p><p>PAGE </p><p>CHAPTER 1: Introduction Photograph of the Processor ............... 1-2</p><p>Block Diagram of Control CPU andFFT Processor ....................................... 1-3</p><p>Specification of Buffer ...................... 1-4</p><p>Specification of Correlator ............... 1-13</p><p>Specification of FFT ............................ 1-15</p><p>CHAPTER 2: Software ................................................................................ 2-1</p><p>CHAPTER 3: System Interconnection and Computer I/o's ................... 3-1</p><p>CHAPTER 4: Circuit Description ........................................................... 4-1</p><p>Decoder ................................................................... 4-1</p><p>Buffer A ................................................................. 4-3</p><p>Buffer B(C) ........................................................... 4-6</p><p>Load Control B(C) ................................................ 4-7</p><p>Unload Control B(C) ............................................. 4-8</p><p>Recorder Control 1 .............................................. 4-13</p><p>Recorder Control 2 .............................................. 4-14</p><p>Correlator and Correlator Card ........................ 4-14</p><p>TC Counters ........................................................... 4-18</p><p>Fringe Rotators .................................................... 4-18</p><p>Buffer Interface .................................................. 4-19</p><p>Delay of Fringe Rate Display ............................ 4-19</p><p>TCD Display, Memoscope, Alert .......................... 4-19</p><p>Masterclock ........................................................... 4-20</p><p>Diagnostics and Failures ................................... 4-22</p><p>FFT Interface ........................................................ 4-24</p><p>CHAPTER 5: Mnemonics Index ................................................................... 5-1</p></li><li><p>THE NRAO VLBI MARK II PROCESSOR</p><p>CHAPTER 1: Introduction</p><p>This report describes the hardware developments of the Mark II VLBIprocessor during the past four years. The reader is referred to NRAO</p><p>Electronics Division Internal Report #118, in which the principle of theMark II system is described. The processor control program is described in</p><p>NRAO User's Manual #26. We will limit this report to the processor anddescribe in detail all needed features.</p><p>Summary of changed and added hardware features (see Figures 1.2, 1.3, 1.10):The old 190 channel correlator was replaced by a larger 576 channel</p><p>correlator.</p><p>The new correlator works with eith 1, 2 or 3 stations and processes</p><p>autocorrelation, cross-correlation or a combination thereof in any one of8 modes.</p><p>A self-checking feature was added to the correlator which insures</p><p>that the correlator circuitry is working properly.</p><p>Nine extra channels for total counts were added in addition to the</p><p>correlator dhannels.The fringe rotator was redesigned.</p><p>The two-station (Leach) buffer was replaced by a three-station buffer.</p><p>Buffers B and C were enlarged to 81,920 bits. One may add a delay from</p><p>0 to 19,456 Ps under program control for source switching experiments.The previously open head drum servo loop was closed.</p><p>The audio decoder was redesigned.</p><p>The video decoder was redesigned and accepts MK-II or MK-II-C format.</p><p>The buffer was designed so that VR-660 or IVC-825 video recordersmay be connected on any of the inputs.</p><p>The buffer was designed so that when an error is detected for the512 ps sync word the correlator is blanked during the previous 512 ps of data.</p><p>A blanking circuit was added that insures that invalid data is shiftedout of the correlator before the correlator is unblanked.</p><p>A special FFT processor was added to the system to calculate spectraand correct for fractional bit shift.</p><p>Block diagram Figure 1.2 shows the overall system.</p></li><li><p>1111 N</p><p>IS</p><p> S</p><p>IN</p><p> lea</p><p>rit#</p><p>Sap</p><p>Iiitle.W</p><p>atit*</p><p>t..</p><p>:t)</p><p>Ep a;</p><p>..........</p><p>&gt;5"</p><p>rto</p><p>to</p><p>witid</p><p>fn</p><p>eM</p><p>atrrg</p><p>irr,7</p><p>7. 1</p><p>1"'</p><p>ON</p><p>MIR</p><p>SIN</p><p>V</p><p>,</p><p>MO</p><p>O:,</p><p>P/1</p><p>(:) to</p><p> g</p><p>rap</p><p>h</p><p>*</p><p> ,</p><p>;.</p></li><li><p>ON</p><p> Uw</p><p>e o</p><p>tipte</p><p>r&amp;R</p><p>VA</p><p>kti</p><p>ktv</p><p> 62</p><p>0</p><p>4kW</p><p>, lb</p><p> CoP</p><p>Eri</p><p>x m P</p><p>OIA</p><p>/T h</p><p>l4L</p><p>T /</p><p>NV</p><p>tt4rF</p><p>, T</p><p>NT</p><p> it zt</p><p>rike </p><p>E, C</p><p>oN</p><p>rieO</p><p>LIE</p><p>Dpe</p><p>Sst</p><p>41)D</p><p>kEst</p><p>AD</p><p>DR</p><p>E-s</p><p>t</p><p>ID /i</p><p>s</p><p>cAtiB</p><p>RID</p><p>EhE</p><p>rfo</p><p>rzlE</p><p>s</p><p>WcP</p><p>AN</p><p>DIv</p><p>oR</p><p>E 6</p><p>208</p><p> kW</p><p>ilb</p><p>Ct 0</p><p>P6-</p><p>-</p><p>TE</p><p>LE</p><p>TY</p><p>PE20 tt</p><p>4It</p><p>o 1</p><p>14141) </p><p>A-D</p><p>DR</p><p>Ess</p><p>: 6o</p><p> 61</p><p>TO</p><p> coR</p><p>MLA</p><p>-</p><p>ttA</p><p>FF</p><p>E0</p><p>CO</p><p> *M</p><p>OM</p><p>*.</p><p>Fre</p><p>pti </p><p>D/T</p><p>Eif</p><p>kit</p><p> k 4 P</p><p>T </p><p>DhAr</p><p>AD</p><p>DR</p><p>ESS:</p><p> 10Tk</p><p>PE</p><p> bR</p><p>iVE</p><p> \AA</p><p>NG</p><p>to 1</p><p>27.7</p><p>TR</p><p>Ack 1</p><p>600 t</p><p>tP1</p><p>TE</p><p>N r</p><p>OtIP</p><p>AT</p><p>I aLE</p><p>Ir I</p><p>PS</p><p>taro</p><p> MA</p><p>TI L</p><p>okb</p><p>67</p><p>-t(D</p><p>uro.</p><p>, 1.1</p><p>! C</p><p>OA</p><p>rreoL</p><p> (oh P</p><p>wre</p><p>a A</p><p>PI)</p><p> rF</p><p>r prz</p><p>ocE</p><p>sto</p><p>te.</p></li><li><p>Specification of Buffer:</p><p>Inputs from each of three video recorders:</p><p>ASTRODATA: clipped diphase video signal at 4 Mb/s, 0.3-15 VPP</p><p>into 752</p><p>HEADSWITCH: 30 Hz square wave, 7 V , none for MK II-CPP</p><p>AUDIO 1: diphase time code at 3.84 Kb/s, 0.5-20 VPP</p><p>AUDIO 2: diphase ID code at 3.84 Kb/s, 0.5-20 VPP</p><p>Outputs to each of three video recorders:</p><p>RUN: Relay contact to start-stop recorders</p><p>60 Hz REFERENCE: 60 Hz TTL square wave to which the recorder</p><p>motors lock.</p><p>HEAD DRUM: Analog signal +7V with TC = 5 seconds to</p><p>control phase of head drum servo. Not used</p><p>for MK-II-C.</p><p>Inputs from Correlator Control:</p><p>REFCLK: 4 MHz square wave, master reference</p><p>UCLK B, C: 4 MHz square wave, unload clockMODE 2: correlator mode 2</p><p>ALERT OFF: Disables audible error buzzer</p><p>Outputs to correlator control:</p><p>DAT A, B, C: 4 Mb NRZ data</p><p>FRAME A, B, C</p><p>TCD DAT A, B, C: audio NRZ data</p><p>TCD CLK A, B, C: audio clock</p><p>FLERR A, B, C: error count</p><p>DATOK A, B, C: True when data is decoded properly</p><p>XFER: True when processor is ready to correlate</p><p>Computer I/O to 1 general purpose Varian interface as assigned in</p><p>Chapter 3.</p><p>Block diagram Figure 1.3 shows the buffer.</p><p>The buffer is designed to decode MK II (VR 660) as well as MK II C (IVC 825A)</p><p>formats shown in Figures 1.4, 1.5, 1.6, 1.7, and 1.8. Buffer A has a small</p><p>4,096 bit memory half of which is used to correct for time displacements (jitter)</p><p>of the tape recorders and the other half is used to keep track of bad 512 Ps sync</p><p>patterns. At the end of every 2,048 bits a 8 bit sync pattern is decoded. If</p></li><li><p>this pattern does not appear or if it is decoded at the wrong time, an error inthe pattern or a bit slip has occurred during the last 512 microseconds. Whenthis data is shifted thru the correlator the correlator is blanked by DATOK goingfalse.</p><p>Buffer B and C each have a 81,920 bit memory, of which 4,096 bits performthe same function as Buffer A, and 77,824 bits are used for delay of 0 to</p><p>19,456 ps. This delay is under program control and may be changed rapidly.</p><p>Timing and address relations for Buffer A, B and C are shown in Figure 1.9.</p></li><li><p>13, S</p><p>Ywc </p><p>tiEtt</p><p>DA</p><p>TA</p><p> A 8</p><p> C.,</p><p>To</p><p>ST</p><p>AR</p><p>T/</p><p>101</p><p>A/c</p><p>F L</p><p>AI</p><p>licL</p><p>ICA</p><p>L</p><p>rRA</p><p> ttE</p><p> CT</p><p>To</p><p>6'2</p><p>0 I</p><p>T </p><p>I to tt</p><p>, SY</p><p>NC</p><p> tt&amp;</p><p>tle</p><p>LO</p><p> po tot R</p><p> 14 :</p><p>D er, R</p><p>.oi</p><p>tt </p><p>a</p><p>DD</p><p>R </p><p>UN</p><p>LO</p><p>A</p><p>SyN</p><p>t bt7</p><p>r:cr</p><p>%1 </p><p>POIN</p><p>TER</p><p>Fio</p><p>Not</p><p>.TD</p><p>r6 1</p><p>E 1</p><p>4 </p><p>1)4</p><p>77rA</p><p>MIA</p><p>0-</p><p>AV</p><p>D10</p><p>T A-(</p><p>00</p><p> V</p><p>Ec O</p><p>DE </p><p>v? ?U.</p><p>6f3</p><p>o </p><p>60H</p><p>z B</p><p>vcr</p><p>Dlo</p><p>AU</p><p>DID</p><p>Z</p><p>AS</p><p>TR</p><p>O C</p><p>beA</p><p>,</p><p>tDF</p><p>SYK t</p><p>)flC</p><p>T</p><p>ottt</p><p>. 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I</p><p> I 0</p><p> 0 I</p><p> 7 b</p><p> PC I </p><p>6 g</p><p>.5- 0</p><p> 2</p><p> b </p><p>bA</p><p>7 A</p><p>498 </p><p>/ 4. 9</p><p>9 b</p><p> t-a</p><p>t74 M</p><p>b E</p><p>OF</p><p> 620-</p><p> b 4</p><p>P---j</p><p>OF</p><p>65</p><p>51</p><p>2. b</p><p> ST</p><p>OR</p><p>SD</p><p> IN</p><p> it</p><p>P*P </p><p>&amp;G</p><p>T/ v</p><p> G</p><p>A P</p><p>- 2</p><p>1 /- b</p><p>11</p><p>31 /</p><p> 122</p><p>_ ,b</p><p>2.8</p><p>2.s</p><p>/ 1</p><p>92</p><p>77</p><p>.ts</p><p>1:WI=</p><p>FE</p><p>R- </p><p>A </p><p>4-0</p><p>/6 6</p><p>ifs 6 = /0</p><p>24 t</p><p>As </p><p>, i t-</p><p>pcd</p><p>(L</p><p>2 t </p><p>/02.</p><p>q. a</p><p>citc</p><p>lyes</p><p>eL</p><p>rtkA</p><p>rreR</p><p> e1 C</p><p>:ID</p><p>ets/0</p><p> 4-8</p><p>0 tA</p><p> SR</p><p> p</p><p>q,c</p><p>.ttt</p><p>i.1</p><p>02</p><p>4-0</p><p>.</p><p>-13</p><p>(AF</p><p>F =</p><p> e2</p><p>k6</p><p>)130</p><p>/ii3i</p><p>-</p><p>FRA</p><p>YIE</p><p>"</p><p>6 t4</p><p>.aL</p><p>iVF</p><p>oacIA</p><p> IV</p><p> I 6</p><p>z_ </p><p>T ID</p><p>A/</p></li><li><p>Specification of Correlator:</p><p>A block diagram of the correlator is shown in Figure 1.10. There is one</p><p>cable to the buffer and a description of the signals is given above. There</p><p>are four cables interfacing to the computers thru four general purpose interfaces.</p><p>Their description is given in Chapter 3. One additional cable connects to the</p><p>computer I/O bus to handle the 60 Hz interrupt. The correlator has a total</p><p>of 576 channels which are arranged in one of 8 modes as shown in Figure 1.11.</p><p>In addition to those channels there are 9 total count channels plus 16 channels</p><p>which may be placed in parallel with any of the others under program control.</p><p>MODE CORRELATOR</p><p>0 - 96 CH AUTO A, 96 CH AUTO B, 192 CH CROSS A-B</p><p>1 - 288 CH AUTO A, 288 CH AUTO B</p><p>2 576 CH AUTO A</p><p>3 192 CH AUTO A, 192 CH AUTO B, 192 CH AUTO C</p><p>4 288 CH CROSS A-B</p><p>5 128 CH AUTO A, 128 CH AUTO B, 128 CH CROSS A-B</p><p>6 - 96 CH CROSS A-B, 96 CH CROSS A-C, 96 CH CROSS B-C</p><p>7 &lt; 64 CH AUTO A, 64 CH AUTO B, 64 CH AUTO C64 CH CROSS A-B, 64 CH CROSS A-C, 64 CH CROSS B-C</p><p>Figure 1.11 Correlator Modes</p><p>There are three 3-level fringe rotators similar to the one described in EDIR #118.</p><p>Fringe rotator A-B and A-C are independently controlled by the program whereas</p><p>fringe rotator B-C takes the phase difference of A-C minus A-B.</p><p>Sample rates are controlled by the program and correspond to the bandwidths:</p><p>2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 62.5 kHz, 31.25 kHz and 15.625 kHz.</p></li><li><p>hut </p><p>Li- r</p><p>---- A</p><p>.......</p><p>c </p><p>MCC c</p><p>hoc</p><p>1 , cos c</p><p>os' c</p><p>ps</p><p>Pio </p><p>DE</p><p>T*01</p><p>162</p><p>0</p><p>riPLE</p><p>Rh </p><p>A .V</p><p>M-P</p><p>LO c 201</p><p>1Ht.</p><p>X- T</p><p>A I</p><p>OH</p><p>L</p><p>L.r-</p><p>Tie</p><p>.IN</p><p>RoM</p><p>/01Z</p><p>IPP</p><p>e -F</p><p>P S</p><p>FY? </p><p>Oti</p><p>IPC</p><p>H</p><p>t wc.</p><p>t.W</p><p>Ctv</p><p>oikt</p><p> LI</p><p>COP</p><p>TO 62.0</p><p>1</p><p>riP</p><p>LE</p><p>k.5'</p><p>441 </p><p>PaC</p><p>AN</p><p>PLE</p><p>P</p><p>rppk</p><p>u. P</p><p>ATE</p><p>:D</p><p>GL</p><p>AY</p><p>Dq</p><p>rt.i</p><p>.r/</p><p>C.</p><p>r E.</p><p> R.</p><p>AM</p><p>Dto</p><p> A E</p><p>t C</p><p>Ftz</p><p>oti v</p><p>t t.</p><p>t E</p><p>t R</p><p>.,T</p><p>O 6</p><p>10</p><p> I</p><p>71-1</p><p>, t </p><p>C. D</p><p>IA PO</p><p>CW</p><p>rri</p><p>. .1.; </p><p>rO</p><p>W. E</p><p>WE</p><p>:</p><p>..roo</p><p>re,</p><p>1</p><p>e C</p><p> 19 4</p><p> /M</p><p>EL </p><p>Co</p><p> kA</p><p>-TO</p><p>P</p><p>co</p><p>siN</p><p>G C</p><p>HA</p><p>NA</p><p>/6</p><p>Tyzo</p><p>ti6 </p><p>ZO TR</p><p>oti</p><p>()to'</p><p>API</p><p>A x</p><p>icE</p><p>-</p><p>R&amp;-</p><p> TA</p><p>C K</p><p>T</p><p>IRP</p><p>T</p><p>TO</p><p> 6? </p><p>oi</p><p>60</p><p>1it</p><p>rPO</p><p>ttO</p><p>FF</p><p>E 0</p><p>DP </p><p>A,B</p><p>,C I.T</p><p>O M</p><p>I</p><p>rz e</p><p>s E</p><p>T-i</p><p>kon </p><p>6'2,</p><p>01</p><p>DP</p><p> 4 </p><p>bP</p><p> e </p><p>bP c</p><p> rkott</p><p>rtgr</p><p>fER</p><p>CS</p><p>DA</p><p>TA</p><p>TO</p><p> ru</p><p>rre</p><p>vz</p><p>1.1.</p><p>467 O</p><p>V</p></li><li><p>Specification of FFT Processor</p><p>The FFT consists of a Nova 820 CPU, an Elsytec 306/MFFT plug-in</p><p>array processor and a program library supplied by Elsytec. It is a mediumspeed FFT processor with the following basic specification:</p><p>No. Real Points 32 64 128 256 512* 1024 2048 4098 8192 16384Time/ms 8.8 14.5 23 39 75 139 280 600 1300 2850</p><p>No. Core Locations 58 114 226 450 898 1794 3586 7170 14338 28674</p><p>*Used by NRAO</p><p>These times are without I/O transfers and without set-up by a master program.</p><p>NRAO has added fractional bit shift corrections to the master program. Forfurther details see Chapter .2.</p><p>1-15</p></li><li><p>CHAPTER 2: Software </p><p>Introduction The present configuration for VLBI processing consists of a Varian</p><p>620-1 minicomputer and a Data General Nova 820 minicomputer. The Nova containsan Elsytec array processor hardware board which permits it to fast Fourier</p><p>transform the cross-correlation function sent by the Varian and to return theresultant spectrum back to the Varian where it is written on 9 track magnetic</p><p>tape.The Varian is, in general, the same software which has been around since</p><p>the processor has been in operation. Therehave been extensive modifications,</p><p>however. These modifications add to, rather than alter the original philosophy.The first task for the Varian program is to read into memory the PREPTAPE</p><p>information. This consists of up to 20 scans. The video tapes should be positionedto within one second of time relative to each other. When the start button is</p><p>pushed on the correlator chassis, the program starts the video tape players(either 2 or 3), insists on 30 consecutive good frames, then aligns the tapesto the sane frame number.</p><p>The delay between station A and B is calculated and strobed in. If thereis a third station the A-C delay is calculated and strobed in. A built in delayof 5 seconds must elapse before data are recorded on 9 track tape. If mode 0or 4 is in effect, the correlator data are sent to the Nova computer to betransformed, then sent back to the Varian to be written on tape.</p><p>A CRT display of fringe amplitude for 12 channels of A-B data and 12 channelsof A-C data is created by the Varian. In case of two station processing, 24channels of A-B data are displayed.</p><p>The source statements fo

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