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  • NATIONAL RADIO ASTRONOMY OBSERVATORY

    CHARLOTTESVILLE, VIRGINIA

    ELECTRONICS DIVISION INTERNAL REPORT No. 187

    THE NRAO VLBI MARK II PROCESSOR

    B. MEREDITH AND B. RAYHRER

    JUNE 1978

    NUMBER OF COPIES: 150

  • INDEX

    PAGE

    CHAPTER 1: Introduction Photograph of the Processor ............... 1-2

    Block Diagram of Control CPU andFFT Processor ....................................... 1-3

    Specification of Buffer ...................... 1-4

    Specification of Correlator ............... 1-13

    Specification of FFT ............................ 1-15

    CHAPTER 2: Software ................................................................................ 2-1

    CHAPTER 3: System Interconnection and Computer I/o's ................... 3-1

    CHAPTER 4: Circuit Description ........................................................... 4-1

    Decoder ................................................................... 4-1

    Buffer A ................................................................. 4-3

    Buffer B(C) ........................................................... 4-6

    Load Control B(C) ................................................ 4-7

    Unload Control B(C) ............................................. 4-8

    Recorder Control 1 .............................................. 4-13

    Recorder Control 2 .............................................. 4-14

    Correlator and Correlator Card ........................ 4-14

    TC Counters ........................................................... 4-18

    Fringe Rotators .................................................... 4-18

    Buffer Interface .................................................. 4-19

    Delay of Fringe Rate Display ............................ 4-19

    TCD Display, Memoscope, Alert .......................... 4-19

    Masterclock ........................................................... 4-20

    Diagnostics and Failures ................................... 4-22

    FFT Interface ........................................................ 4-24

    CHAPTER 5: Mnemonics Index ................................................................... 5-1

  • THE NRAO VLBI MARK II PROCESSOR

    CHAPTER 1: Introduction

    This report describes the hardware developments of the Mark II VLBIprocessor during the past four years. The reader is referred to NRAO

    Electronics Division Internal Report #118, in which the principle of theMark II system is described. The processor control program is described in

    NRAO User's Manual #26. We will limit this report to the processor anddescribe in detail all needed features.

    Summary of changed and added hardware features (see Figures 1.2, 1.3, 1.10):The old 190 channel correlator was replaced by a larger 576 channel

    correlator.

    The new correlator works with eith 1, 2 or 3 stations and processes

    autocorrelation, cross-correlation or a combination thereof in any one of8 modes.

    A self-checking feature was added to the correlator which insures

    that the correlator circuitry is working properly.

    Nine extra channels for total counts were added in addition to the

    correlator dhannels.The fringe rotator was redesigned.

    The two-station (Leach) buffer was replaced by a three-station buffer.

    Buffers B and C were enlarged to 81,920 bits. One may add a delay from

    0 to 19,456 Ps under program control for source switching experiments.The previously open head drum servo loop was closed.

    The audio decoder was redesigned.

    The video decoder was redesigned and accepts MK-II or MK-II-C format.

    The buffer was designed so that VR-660 or IVC-825 video recordersmay be connected on any of the inputs.

    The buffer was designed so that when an error is detected for the512 ps sync word the correlator is blanked during the previous 512 ps of data.

    A blanking circuit was added that insures that invalid data is shiftedout of the correlator before the correlator is unblanked.

    A special FFT processor was added to the system to calculate spectraand correct for fractional bit shift.

    Block diagram Figure 1.2 shows the overall system.

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  • Specification of Buffer:

    Inputs from each of three video recorders:

    ASTRODATA: clipped diphase video signal at 4 Mb/s, 0.3-15 VPP

    into 752

    HEADSWITCH: 30 Hz square wave, 7 V , none for MK II-CPP

    AUDIO 1: diphase time code at 3.84 Kb/s, 0.5-20 VPP

    AUDIO 2: diphase ID code at 3.84 Kb/s, 0.5-20 VPP

    Outputs to each of three video recorders:

    RUN: Relay contact to start-stop recorders

    60 Hz REFERENCE: 60 Hz TTL square wave to which the recorder

    motors lock.

    HEAD DRUM: Analog signal +7V with TC = 5 seconds to

    control phase of head drum servo. Not used

    for MK-II-C.

    Inputs from Correlator Control:

    REFCLK: 4 MHz square wave, master reference

    UCLK B, C: 4 MHz square wave, unload clockMODE 2: correlator mode 2

    ALERT OFF: Disables audible error buzzer

    Outputs to correlator control:

    DAT A, B, C: 4 Mb NRZ data

    FRAME A, B, C

    TCD DAT A, B, C: audio NRZ data

    TCD CLK A, B, C: audio clock

    FLERR A, B, C: error count

    DATOK A, B, C: True when data is decoded properly

    XFER: True when processor is ready to correlate

    Computer I/O to 1 general purpose Varian interface as assigned in

    Chapter 3.

    Block diagram Figure 1.3 shows the buffer.

    The buffer is designed to decode MK II (VR 660) as well as MK II C (IVC 825A)

    formats shown in Figures 1.4, 1.5, 1.6, 1.7, and 1.8. Buffer A has a small

    4,096 bit memory half of which is used to correct for time displacements (jitter)

    of the tape recorders and the other half is used to keep track of bad 512 Ps sync

    patterns. At the end of every 2,048 bits a 8 bit sync pattern is decoded. If

  • this pattern does not appear or if it is decoded at the wrong time, an error inthe pattern or a bit slip has occurred during the last 512 microseconds. Whenthis data is shifted thru the correlator the correlator is blanked by DATOK goingfalse.

    Buffer B and C each have a 81,920 bit memory, of which 4,096 bits performthe same function as Buffer A, and 77,824 bits are used for delay of 0 to

    19,456 ps. This delay is under program control and may be changed rapidly.

    Timing and address relations for Buffer A, B and C are shown in Figure 1.9.

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