nbsingh csir-ceeri-semiconductor-activities

Work done in

Semiconductor Chip Design Area at CSIR-CEERI

Under Leadership of

Narendra Bahadur SinghChief Scientist

MEMS, Memory and Linear ICs Design Laboratory CSIR-CEERI Pilani,

Rajasthan-333031,India.

31 M Tech Dissertationswere supervised.

.

We are working on, • Sensors Design• Data Converters Design• Signal Conditioning ICs Design• PLL Design • 32bit Processor Design• Cryptographic System Design • Memory Design• RF CMOS ICs (QPSK/ASK TRX)• 14 Analogue ICs were fabricated• PC based Test setup development

N B SINGH CSIR-CEERI

Pressure Sensor Process Steps


Simulation Result@ Pressure 5MPa


Ultrasonic Sensor (mem:2mmx1.5mmx15um @8.57MPa)


Thin Film Micro Heater (Poly)


Thick Film Micro Heater


Designed 14 Analogue CMOS ICs

First time Fully indigenous Full Custom Designs were fabricated and some of them were tested in Year 2006.

SCL India Fabrication ICP Process # 1. Five ICs Designs were submitted from CEERI

• 12-bits Digital-to-Analog Converter• 16-bits Digital-to-Analog Converter• Unbalanced Wheatstone Bridge based Sensor’s Signal Conditioning IC• Voltage Controlled Oscillator(VCO) for Voltage to frequency conversion• Instrumentation Amplifier for Micro Sensor’s Signal Conditioner

SCL India Fabrication ICP Process # 2. Nine ICs Designs were submitted from CEERI

• 16-bits High Performance Analog-to-Digital Converter• 12-bits High Performance Analog-to-Digital Converter• High Frequency Phase-Locked-Loop, 14 - 40MHz• Medium Frequency Phase-Locked-Loop, 2.5 - 20MHz• Low Frequency Phase-Locked-Loop, 666KHz - 2MHz• Single Bridge -Sensor’s Signal Conditioner with Temp. Comp. using PGA• Dual Bridge -Sensor’s Signal Conditioner with Temp. Comp. using PGA• Eight-Analog Input Channels Data Acquisition Micro-System (DAMS)• Position/Motion Sensing Capacitive Network Signal Processing Circuit


Photographs of the Mixed Signal ICs Fabricated from SCL


12/16 bits Data converter ICs


PC Based IC Test Set up


4-bit SA ADC Decision Tree


12bit SA ADC Schematic


* Total Nodes: 691* Total Elements: 2172


180nm Tech, Rail-to-Rail Op Amp Design using Constant Current Source and Voltage(BGR)

N B Singh CSIR-CEERI

Sigma Delta ADC Specification• First order Sigma-Delta modulator

• Positive and Negative rails of 2.5V and -2.5V

• 10-bits of digital resolution

• Input frequency of 1 KHz

• Clock frequency of 5 MHz

• Sampling frequency of 77 KHz (i.e. Nyquist rate of 38.5 KHz)


Integrator • Closed loop gain should be small enough so that the output does not rail Defined by the values of R and C• Optimum values of R and C to be chosen C should be small to minimize layout area

Op-Amp • Should have high gain to integrate smoothly• Large bandwidth to pass through all the harmonics of input wave The unity gain BW should be greater than that of the clock frequency to effectively pass the signal• High phase margin for stability

Op-Amp Specifications• Gain = 118 dB • Unity Gain BW = 57 MHz• Phase Margin = 73°• CMRR = 1002:1


First Order SD Modulator Op Amp Specs

Parameter Value

Open-Loop Gain 68.75 db

Phase Margin 76.8 degrees

Gain Bandwidth 9.5 MHz

Offset 151.6µV

Overshoot/Undershoot 272.7/3.9 mV

Slew Rate +180/-150 V/µsec

Delay +721/-904 nsec

Rise/Fall Time 751/1.4 nsec

Settle Time 15.4 µsec


Parameter Value

Rise Time 1.4 nsec

Fall Time 3.2 nsec

Slew Rate +1/-2.3 V/nsec

Delay +3.7/-6.8 nsec

Offset 502 µV

Overshoot 28.7 mV

Undershoot 7.8 mV

Settle Time 0.31 µsec

Comparator Specs Full Custom Layout SD Modulator in 180nm TSMC MM Technology


Result for First Order Sigma-Delta Result of Parasitic Net list Modulator for ±500mV,50KHz with Lumped & DistributedInput and 6MHz Clock. RCC extracted from Modulator Core Layout.


Another Architecture of a Sigma-Delta ADC Modulator Sinusoidal input, peak amplitude = ±500mVSignal Frequency = 50KHzClock Frequency = 6MHz


Decimator Circuit for the SD ADC Verification Circuit for SD ADC 8bit ADC Modulator+Decimator


SD Modulator


Two Stage Modulator


Sigma-Delta Modulator Result


Simulation Result for Modulator of SD ADC


Signal Conditioning Circuit


PLL Schematic


VCO Measurement Result


PLL Simulation Result


IEEE-754 Processor Implementation


Processor RTL Description Page # 1


Processor RTL Description Page # 2


32-Bit Microprocessor Layout


32-Bit Microprocessor Schematic Top


32-Bit Microprocessor Schematic Sheet# 1


Result after exec. of Program to copy 32 memory address


DCT Implementation


DCT Results


DCT Computed Result Stored in the RAM


Efficient Logic Efficient Logic Generation MethodsGeneration Methods

• Methods to estimate gate driving strength and delaysMethods to estimate gate driving strength and delays• Logical effort Logical effort • Computation of logical effortComputation of logical effort• Multistage networks Multistage networks • Condition for minimum delayCondition for minimum delay• Logical effort for skewed gates Logical effort for skewed gates


For static cmos logic style For static cmos logic style 20-bit decoder20-bit decoder

Frequency (MHz) of operation

Delays (ns) Functionality Highest/lowest voltage

Number of transistors

20-bit decoder with sizing

111 MHz 4.3 ns Correct 5v / 0v 17048

20-bit decoder with sizing

5 MHz 2.6 ns Correct 5v / 0v 17048

20-bit decoder without sizing

6 MHz 24.4 ns Spikes at the output

5v / 0v 17048

20-bit decoder without sizing

5 MHz 24.48 ns Spikes at the output

5v / 0v 17048

Table : showing the performance of static cmos 20-bit decoderTable : showing the performance of static cmos 20-bit decoder

AAnalysisnalysis & D& Diiscussionscussion of of RReesultssults


Complete BIST scheme

Fault-free converter

Faulty converter

out4


Memory Floor Planning


SPR Generated Lay out of 1K VSDRAM without pad


Lay out of 1K VSDRAM with pad


24/05/2010

SIGNAL

0

0

I--PATH

Q--PATH

DELAY

Fig. Proposed QPSK Transceiver Architecture 69


System Level Model Of QPSK:24/05/2010

70


COMPARISON OF SIMULATION RESULT

Mathematical Modelling

System Level Modelling

SPICE Simulation

24/05/2010

71


ADDER OUTPUT

Mathematical Modelling

System Level Modelling

SPICE Simulation

24/05/2010

72


CMOS Squarer

Vcc=5V iin=±50µA73


CMOS Rectifier

Vd=5V iin=±50µA Iref=1mA74


Proposed architecture of ASK Transceiver at block level

75


ASK Response of TRx

76 Vc=2V Vs=5V fc=20MHz fs=20KHz


Simulated waveform with 20KHz signal and 20MHz carrier

R=10K C=470pF77


Organization of Memory With RS Code

Auto recovery

Memory ArrayRow Dec.

Con. Logic

Sense Amp./ Buffer

RS Encoder RS Decoder

Input / Output Buffer

Control Unit


Read Solomon Decoder


RS(24) Encoder Architecture


Specifications

Target FPGA Device Vertex II Pro

Word Size (n) 60bit

Data word size (k) 36bit

Parity Size (p) 24bit

Data Encode Cycles 9clocks

Data Decode Cycles 42clock

Block size 4bit

Hardware description language HDL Verilog

Tool Modelsim and Xilinx


RS(24bit) Synthesis Results

Parameter RS Encoder RS Decoder Total

Cell Used 187 766 953

Input arrival time(Min)

before clock

3.440ns 4.871ns

Output required time (Max) after clock

4.097ns 3.702ns

Power ---------------- ---------------- 423mW

Data Path delay

Ambient temp -------------- ---------------- 25ºC

Maximum Frequency

349.284MHz 163.052MHz ----


White Board System Integration on FPGAVGA Camera+Controller+µC+ Light Pen


NAND Flash Securityinvented by Dr. Fujjo Masuoka and Mr Shoji Ariijumi from Toshiba,1980NAND Flash Securities are,• Unique ID 64-bit Serial Number guarantee 264, or 1.8 x 1019 S. Numbers.• One Time Programmable (OTP) uses fixed number of pages• Component authentication used for serial number verification in ICs to check critical system components swapping.• Code authentication to protect system code• Digest number to verify at boot time whether to start or not. • NAND Flash devices can accommodate multiple digest numbers Hacker could mot successfully breach code authentication• Hash Algorithm - To create a code authentication or digest number, apply a hash algorithm to the original version of code, then program this multi byte number into the OTP area. including the unique ID as part of the hash input string, the code authentication number cannot be duplicated, although the code may be duplicated. • CRC-16,CRC-32,MDA-4,MDA-5, SHA-1 and SHA-256 are hash algorithm• SHA-256 is most secure and CRC-16 is the least secure hash algorithm SHA-256 has 32 bits word, 512 bit Block size, less than 264 bits message size, 256 bits message digest and 128 bits security. • AES SHA-256 and RSA-1024 are used as an encryption in SLC and MLC NAND Flash• Unique ID and OTP capabilities offer some of the most secure NAND Flash solutions available.


Reliability Issues in NAND Flash Memory

Data errors corrected by error correction codes except Burst dataEndurance and high temperature data retention are the most important reliability issues of Flash memory.No Reliability Issues with 20nm high-K MG NAND Flash Memory. h-k Materials: HfO2,Al2O3,ZrO2,HfO2/Al2O3,Silicates,AlNy(Ox)Serious limitations as it’s shrunk below 11nm or so. Write endurance plummets, memory retention times are reduced and cell-to-cell interactions increase significantly.Typical sub-90nm NAND Flash cells reliability issues :100k cycle’s(SLC), 5-10k cycles(MLC) NAND endurance and 2 hours High Temperature Storage (HTS: 150ºC, 200ºC & 250ºC).Nit: Interface trap generation & bulk trap generation show the power dependence on program/erase cycle count. Nit Recovery model:dNit/Nit = -k.dt = -k0 exp(-Ea/KbT).dtNit(t) = Nit(0) e-kt , where t is the baking time and Nit(0) is interface charge density at t=0.Based on the Arrhenius approximation, k takes the form:k = k0 exp(-Ea/kbT)


Reliability issues of NAND Flash memory

Endurance and High Temperature Data Retention:In endurance process, the program/erase cycling causes,to raise interface trap(Nit) and oxide trap(Not) generation in tunneling oxide.Trap generation models under constant stress arethermo-chemical (E) model , Scattering-Induced Diffusion (SID) model and reaction-diffusion (R-D) model , can not be directly applied on Flash memory cells, due to its bipolar stress and dynamic electric filed. Widely accepted that the interface trap recovery , IEEE2009 electron-detrapping and Stress Induced Leakage Current (SILC) are regarded, as the important physics mechanisms in the high temperature retention.However, Study is incomplete for HTS NAND Flash.MSP (Memory Signal Processing) technology isa combination of error correction and memory management schemes. MSP2020 supports ONFI com-pliant NAND interfaces (4 to 128 GB) to a host Proc.


Reliability issues in Binary and MLC Flash TechnologyData Reliability : MLC is worse than BinaryLong Term Data Error: Distance between adjacent voltage levels in MLC is much smaller than in Binary flash,MLC flash data error is two order of magnitude w.r.t. Binary,MLC has less long term data stability due to leakage from FG.Program Disturb Error: More in MLC-causes a programming operation on one page to induce a change in bit value on another, unrelated page.Read Disturb Error : Read disturb effect causes a page read operation to induce a permanent, bit value change in one of the read bits.Performance:MLC needs more time for reading a page into Voltage Level Comparisonthe flash buffer, writing a flash buffer into a page, and erasing a flash unit.Sustained Read : voltage gap lessen in MLCSustained write: performance less in MLCFlash Management: Poor due to sequential Programming in MLC and random in Binary.True FFS (Robust Flash Management+ECC+Bad Block Mgmt), Thin Controller (Multi Burst+DMA+EDC+parallel Multi Plane) and Flash media (2 Parallel Planes) to overcome problem.


Encryption Methods

Entropy Encoding (for text and lossless data)Run-Length EncodingHuffman CodingDictionary Based Algorithms:LZ77 : Lempel and Ziv Algorithm proposed in 1977 for variable-length input and fixed-length output (V-F) .

Modified LZ77 Algorithm: LZSS by Storer & Szymanki Here, codeword normally consists of Index and Length without the Innovation Character.Variable Length String Matcher for VLSI structures Algorithms for longest Search Content Addressable Memory (CAM) Byte Associated CAM DES AES


SALIENT FEATURES OF AES

• AES is a block cipher with a block length of 128 bits.• AES allows for three different key lengths: 128, 192, or 256 bits.• Encryption consists of 10 rounds of processing for 128-bit keys, 12

rounds for 192-bit keys, and 14 rounds for 256-bit keys.• Each round of processing consists of 4 steps.• 128- bit block as 4X4 matrix is called a state matrix.


AES OBJECTIVES

• MATLAB SIMULATION FOR AES ALGORITHM.

• RTL IMPLEMENTATION OF THE AES ALGORITHM.

• INCORPORATION OF MORE SECURITY FEATURES.

• VARIOUS CONFIGURATIONS IN IMPLEMENTATION


STRUCTURE OF AES

AES Encryption AES DecryptionN B SINGH CSIR-CEERI

ENCRYPTION KEY AND ITS EXPANSION

2. The four columns words of the key matrix is arranged in form of into a schedule of 44 words. the key expansion takes place on a four-word to four-word basis, in the sense that each grouping of four words decides what the next grouping of four words will be.

4 STEPS for EACH ROUND of PROCESSING

ENCRYPTION ROUNDS DECRYPTION ROUND


Steps of Each Round of Processing

Step#1. Substitute Bytes• This step consists of using a 16 × 16 lookup table to find a replacement

byte for a given byte in the input state array.• The entries in the lookup table are created by using the notions of

multiplicative inverses in GF(28).• Affine transformation function is used in case of encryption and inverse

affine transformation is used in case of decryption. These functions are used for bit scrambling to destroy the bit-level correlations inside each bytes.


AES SIMULATION RESULT

• Ciphering simulation

AES SIMULATION RESULT

• Deciphering simulation

RESOURCE UTILISATION

“Encryption and Decryption”1.Encryption and Decryption modules are separate.


SYNTHESISE AND SIMULATION IN VERILOG HDL

“Encryption and Decryption”1. Encryption and Decryption in a single module.


DES General Architecture

Initial Permutation

Round 1

Round 2

Round 16

Final Permutation

RoundKeyGenerator

K1 48-bit

K2 48-bit

K16 48-bit

64-bit plain text

64-bit cipher text

64-bit key


Flow Chart of DES (Encryption)


Round Function of DES


Resource utilization for Triple DES


Synthesis Result and Resource Utilization

Conti….N B SINGH CSIR-CEERI

Key Sending Scheme Modification

Encryption

Decryption


Applications of DES/Triple DES

• Electronic financial transactions• Secure data communications• Encrypted data storage • Access control• Smartcard Solutions


Miscellaneous TopicsSecurity and Reliability Issues,• Unique ID• One Time Programmable (OTP) page format• Protect critical System Components and Proprietary software (Code) from attacks and alterations using improved coding algorithm Hash algorithm etc.• Reliability issues in High-Speed Interfaces .• Memory Signal Processing(MSP) Technology for error correction and Memory Management.• Process related changes for improved Flash Memory Technology• Write/Erase Endurance and high temperature data retention .• Already ECC/CRC/Huffman Coding for 4/2 bit errors/page but advance and efficient Coding method for error data recovery• 128 GB to 1Tb (8-die) storage HS ONFI 3.0 for 333MTransfer/s for Tablet, Smart Phone and Solid State Drives .• Wired/Wireless Memory data transfer circuit design


THANKS


nbsingh csir-ceeri-semiconductor-activities

Devices & Hardware