network on chip. 4 장. hw/sw co-design for soc 2 copyright ⓒ 2004 levels of ic architecture
TRANSCRIPT
Network on Chip
2Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
Levels of IC architecture
3Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
Emerging Platforms & Architectures
4Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
단일 반도체 칩 상에 통신망 구조를 이식단일 반도체 칩 상에 통신망 구조를 이식 OSI modelOSI model 에 의해서 전송 프로토콜을 정의에 의해서 전송 프로토콜을 정의 DSP/microprocessor/Memory DSP/microprocessor/Memory 등을 등을 H/W-S/W co-design 이용 단일 칩 이용 단일 칩
내에서 연결내에서 연결 코드 최적화 및 저전력 software IP 라이브러리 구축 모듈간 연결을 위한 버스 구조 구성 요소
Region: Region: 특수한 토폴로지특수한 토폴로지 // 네트워크 구조를 허용하는 영역네트워크 구조를 허용하는 영역 BackboneBackbone Wapper : Wapper : 전송되는 메시지를 적절한 형태로 변환전송되는 메시지를 적절한 형태로 변환 , , 복잡하다복잡하다
복잡하고 대형 시스템에 적합복잡하고 대형 시스템에 적합
NoC (network on chip)U.C. BerkeleyU.C. Berkeley
5Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
Wires-Centric Design Exploits logic structure to reduce wire loads Enables use of advanced circuits
wire properties and crosstalk known early and well characterized
Gives a stable design key wire loads don’t change with small logic
changes
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4 장 . HW/SW Co-Design for SoC
Wires dominate - power, area, delay
Problem - Contemporary tools leave wires as an afterthought result is lack of structure, visibility, and control
Solution 1 - wires first design route key wires, then place gates
Solution 2 - route packets, not wires on-chip networks
global wires fixed before the design starts
7Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
Wires-first design
Floorplan
LocalNetlists
Library
ShortW ire
Models
Place &Route
Structure
Layout
ExtractorR & CTim ing
AnalysisSlowPaths
ManualDesign
RTLStructured
RTL
Regions
W ire plan Key W iresP lacem ent
& Loads
Synthesis
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4 장 . HW/SW Co-Design for SoC
On-Chip Interconnection Networks
Replace dedicated global wiring with a shared network
Dedicated wiring C hip
Loca lLogic
R outer
N etworkW ires
Network
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4 장 . HW/SW Co-Design for SoC
10Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
Bus-versus-Network
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4 장 . HW/SW Co-Design for SoC
NoC Challenges:
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4 장 . HW/SW Co-Design for SoC
Physical Issues Challenges
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4 장 . HW/SW Co-Design for SoC
Most Wires are Idle Most of the Time Don’t dedicate wires to signals, share wires across
multiple signals Route packets not wires Organize global wiring as an on-chip interconnection
network allows the wiring resource to be shared keeping wires busy
most of the time allows a single global interconnect to be re-used on multiple
designs makes global wiring regular and highly optimized
14Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
Dedicated wires vs. Network
Dedicated Wiring On-Chip NetworkSpaghetti wiring Ordered wiring
Variation makes it hard to modelcrosstalk, returns, length, R & C.
No variation, so easy to exactlymodel XT, returns, R and C.
Drivers sized for ‘wire model’ –99% too large, 1% too small
Driver sized exactly for wire
Hard to use advanced signaling Easy to use advanced signaling
Low duty factor High duty factor
No protocol overhead Small protocol overhead
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4 장 . HW/SW Co-Design for SoC
Ideas from Networking and VLSI
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4 장 . HW/SW Co-Design for SoC
Communication
Structural layers of NOC
Regions
Resources
Hardware units
Executables
Functions
Applications
Configuration
Product
Channels and protocols
Processors, memorires, configurable HW, logic
System control, product behaviour
Resource types, buses, IO
Region types, switches, network interfaces
RTOS, code, HW configurations
Resource management, diagnostics, applications
Execution control, functions
Network management, allocation, operation modes
17Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
Physical 신호 전압 , 타이밍 , 버스 폭 , 신호
동기 Data link
오류 검출 정정 Arbitration of physical medium
Network IP protocol 데이터 라우트
Transport TCP 프로토콜 End –to-end connection
Physical
Data link
Network
Transport
System/Session
Application
Network protocol
18Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
NOC Platform development
Scaling problem How big NOC is needed? What are the application area
requirements? Region definition problem
What kind of regions are needed? What kind of interfaces between regions? What are the capacity requirements for the regions?
Resource design problem What is needed inside resources? Internal computation type and
internal communication? Application mapping flow problem
What kind of languages, models and tools must be supported? How to validate and test the final products?
19Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
NOC Application Development Mapping problem
How to partition applications for NOC resources? How to allocate functionality effectively? Is the performance adequate? Is the resource usage in balance?
Optimisation problem How to perform global optimisation of heterogenuous applications?
How to define right optimisation targets? How to utilise application/resource type specific tools?
Validation problem Are the contraints met? Are the communication bottlenecks or power
consumption hot spots? How to simulate 10000 GIPS system? How to test all applications?
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4 장 . HW/SW Co-Design for SoC
NoC-Based System Design -I
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4 장 . HW/SW Co-Design for SoC
NoC Based System Design -II
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4 장 . HW/SW Co-Design for SoC
NoC-Based System Design -III
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4 장 . HW/SW Co-Design for SoC
Summary of NoC Systems Design
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4 장 . HW/SW Co-Design for SoC
OSI 모델을 데이터 전송 프로토콜로 사용 칩에 집적된 네트워크 (Network on Chip) 패킷 데이터 전송 대형 시스템이 구성 요소 이종 구성 요소의 칩 레벨 집적에 유리하다 .
S S S
resource
S
resource
S S S
resource
S
resource
S
resource
S
resource
S
resource
S
resource
S S
resource
S
resource
switch
rni
M
P
cre
rniP c
M
rni
MD
c
rni
M
P
cre
rniP c
M
rniP c
M
rni rni
rnirni
rni
rnirnirni
rnirni
mux Selectionlogic
mux
Selectionlogic
mux
Selectionlogic
muxSele
ctio
nlo
gic
mux
Selecti
on
logic
queue
queue
queue
SWITCH
스위치 네트워크 : CLICHE
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4 장 . HW/SW Co-Design for SoC
Square Switch
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4 장 . HW/SW Co-Design for SoC
Regions
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4 장 . HW/SW Co-Design for SoC
Physical Layer
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4 장 . HW/SW Co-Design for SoC
Physical Layer Phenomenon
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4 장 . HW/SW Co-Design for SoC
Data Link Layer
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4 장 . HW/SW Co-Design for SoC
Advanced Bus Techniques*
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4 장 . HW/SW Co-Design for SoC
Network Layer
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4 장 . HW/SW Co-Design for SoC
SPIN NoC*
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4 장 . HW/SW Co-Design for SoC
Transport Layer
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4 장 . HW/SW Co-Design for SoC
Application Program Layer
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4 장 . HW/SW Co-Design for SoC
Application (Software) Layers
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4 장 . HW/SW Co-Design for SoC
NoC Operating System
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4 장 . HW/SW Co-Design for SoC
Performance
CostVariability
SystemQuality
Energyconsumptio
n
Implementation
Development
Modifiability
VolumeFlexibility
Complexity
Functionality
ModularityCohesionCoupling
Programmability
ConfigurabilityApplicability
StructuralFunctional
Control
Manufacturability
LifetimeUsability
EffortTimeRisk
MaterialsLicencingProduction
Capacity
ComputationStorageCommunication
Fault toleranceResult quality (accuracy)Responsiveness
ScalabilityEfficiencyUtilisation
NoC 의 figure of Merit
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4 장 . HW/SW Co-Design for SoC
R. Marculescu
NoC 설계 flow
39Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
BACKBONE
PLATFORMS
SYSTEMS
Baseband platform
Database platform
Multimedia platform
High-perforrmance communication systems
High-capacity communication systems
Virtual reality games
Entertainment devices
Personal assistant
Data collectionsystems
Low Power communication systemsLow Power communication systems
NoC 기반의 응용 분야
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4 장 . HW/SW Co-Design for SoC
Layered Radio Architecture
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4 장 . HW/SW Co-Design for SoC
Stream-based design
Processing
Element 1Stream Packet Stream Packet Stream PacketProcessing
Element 2
InterpretPacket
ConfigurationPipeline
Re-Constr.
Packet
ProcessingPipeline
Bypass Pipeline
Processing Layer
Application Layer Software
I/O Layer
Configuration Layer
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4 장 . HW/SW Co-Design for SoC
NoC 의 저전력 문제어플리케이션 레이어 - DPM, 리소스 관리 , 전력 관리 API
트랜스포트 레이어 - QoS 보장 ( 지연 및 메시지 손실 최소 ) 을 위한 데이터 패킷 관리 문제 , 메시지를 통한 PSM
네트워크 레이어 packetized 데이터 전송시 스위칭 및 라우팅 문제
데이터 링크 레이어 패킷 데이터 에러 손실 감축 및 복구 문제
Physical 레이어 - DVS 에 따른 신뢰성 문제 , 온 칩 동기 문제
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4 장 . HW/SW Co-Design for SoC
Tile-based Architecture PlatformR. Marculescu
44Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
Energy-Aware Mapping for Tile-based Architectures
Objective: minimize the total communication energy consumptionConstraint: meet the communication performance constraints (specified by designer)For a 4X4 tile architecture, 16! mappings
R. Marculescu
45Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
OFDM + CDMA2000 통합 Baseband 프로세서에 적용
Baseband processing
RF
Conversion
to IF
and A/D
CDMA2000
S/W part(DSP)
OFDM
S/W part(DSP)
Interconnection
(NoC)
H/W part
(ASIC)
Modulator
Demodulator
Despreader
Searcher
Time Tracker
AFC
Channel estimator
Lock detector
RAKE combiner
Power control
Channel codec
Rate matching
Multiplexing
I/O controller Process controller Program memory
CDMA2000 HW/SW Co-design
I/Q DemodulatorFFT Mode
Guard Interval Symbol Timing-
RecoveryCarrier Recovery
Channel Estimator Equalizer,
FEC Noise Filter
FFT
OFDM
46Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
NoC Examples [Adriahantenaina et al., 2003] Adriahantenaina, A., Charlery, H., Greiner, A., Mortiez, L., and Zeferino, C. A. (2003). SPIN: a scalable packet switched on-chip micronetwork. In Proceedings of the Design Automation and Test Conference - Designer's Forum, pages 70{79. [Alho and Nurmi, 2003] Alho, M. and Nurmi, J. (2003). Implementation of interface router IP for Proteo network-on-chip. In Proc. The 6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems (DDECS'03), Poznan, Poland. [Goossens et al., 2003] Goossens, K., Dielissen, J., van Meerbergen, J., Poplavko, P., Radulescu, A., Rijpkema, E., Waterlander, E., , and Wielage, P. (2003). Guaranteeing the quality of services in networks on chip. In Jantsch, A. and Tenhunen, H., editors, Networks on Chip, chapter 4, pages 61{82. Kluwer Academic Publishers. [Karim et al., 2001] Karim, F., Nguyen, A., Dey, S., and Rao, R. (2001). On-chip communication architecture for OC-768 network processors. In Proceedings of the Design Automation Conference, pages 678{683. [Nilsson et al., 2003] Nilsson, E., Millberg, M., �Oberg, J., and Jantsch, A. (2003). Load distribution with the proximity congestion awareness in a network on chip. In Proceedings of the Design Automation and Test Europe (DATE), pages 1126{1127.
47Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
Some more technologies John Stockton Ad-hoc wireless networking, networks of sensors
– Emerging Zigbee wireless standard– UC Berkeley’s Smart Dust Project– Dust-Inc. (UC Berkeley spin-off company)– IEEE 802.15.4 Radios
• Hybrid CMOS SOM (System on Module) Solutions:– MEMS structures fabricated on top of CMOS– Film Bulk Acoustic Resonators (FBARs) over CMOS– Chemical sensors over CMOS
48Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
John Stockton’s viewStockLabs Venture Consulting • Software & Compilers will drive chip architecture
– Processor architecture matters less and less– Custom datapaths by compilers replace specialized instrs– 10’s of processors per chip, MIMD becomes a way of life– “Freedom from Choice” - enables SOC scalability
• Chip Industry evolves to three levels of granularity– FPGAs as we know them today, flexible but low performance– Coarse-Grained FPGAs, better perf, but lose some flexibility– Structured ASIC with embedded reprogramability
• Software industry finally “gets it” on reliability / quality– Gains some of the discipline (restrictions) of the IC industry– Trades CPU Cycles for more robust applications
www.stocklabs.com
49Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
Some Companies to watchJohn Stockton
50Copyright 2004ⓒ
4 장 . HW/SW Co-Design for SoC
참고문헌 The Codesign of Embedded Systems : A Unified Hardware/Software
Representation, Sanjaya Kumar, James H.Aylor, Barry W.Johnson, Wm. A. Wulf
Synthesis and simulation of digital systems containing interacting hardware and software components 29th dac
A model and methodology for hardware-software codesign CAP Laboratory Homepage (http://peace.snu.ac.kr/) Pai Chou, Ross Ortega, Gaetano Borriello, "Synthesis of the Hardwar
e/Software Interface in Microcontroller-Based Systems," Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, Santa Clara, CA, November 1992. pp.488-495.