new approach to vlsi buffer modeling, considering

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1568 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 8, AUGUST 2013

New Approach to VLSI Buffer Modeling, ConsideringOvershooting Effect

Milad Mehri, Mohammad Hossein Mazaheri Kouhani,Nasser Masoumi, and Reza Sarvari

AbstractIn this brief, we use the alpha power law model for MOSdevices to reach a more accurate modeling of CMOS buffers in verydeep submicrometer technologies. We derive alpha model parameters of

a CMOS buffer for 90-, 65-, and 45-nm technologies using HSPICEsimulations. By analytical efforts we find the output resistance of aminimum-size buffer and compare it with those extracted from HSPICEsimulations. We propose a new model for the output resistance of a given-size buffer in any technology, which demonstrates 3% error on average

as opposed to the conventional model. Also a new buffer resistanceis proposed analytically and numerically to calculate the crosstalk forinterconnect analysis applications. In addition, we propose a model for

the transfer function zero generated by the gate-drain capacitances ofMOS transistors, which cause the overshooting effect, and develop anaccurate expression for modeling this phenomenon. As the final point,

together with the input-to-output capacitance, the equivalent outputresistors present a simple and accurate macromodel for the CMOS buffer.

Index Terms Alpha-power law, buffer overshooting effect, CMOSbuffer modeling, VLSI buffer.

I. INTRODUCTION

VLSI circuit analysis in the circuit level for the most important

measurements, such as delay and power consumption, depends on

rigorous modeling of their basic components. One of the most

prevailing and underlying elements in digital systems is the CMOS

buffer. A buffer is a simple but principal and critical component

and, as such, has many significant applications and is vastly used for

signal cleaning and the reduction of delay, noise, and crosstalk. This

buffer is popular because of its low power consumption, mainly in

switching phases. With the scaling of CMOS technology into the very

deep submicrometer (VDSM), buffer modeling has been a critical

demand due to its many appearances in the design and analysis

of digital systems. Accurate modeling of this core component can

result in a better inspection through the system, whereas the models

simplicity can cause a fast design time. Hence, many researchers have

addressed this need by proposing various analytical models to present

the behavior of CMOS buffers.

Propagation time delay and power dissipation of buffer are its

major factors that are modeled. However, in some works, the input-

to-output capacitance, which results in overshoot and undershoot

effects, has not been taken into account [1][5] while some others

have incorporated this effect. In [6][11], power estimation models of

a CMOS buffer, accounting for the influence of the input-to-output

coupling capacitance of the buffer in submicrometer technologies,

were given. In [6], [12][15], the nonlinearity induced by the input-

to-output coupling capacitance is taken into account for the analytical

modeling of the gate propagation delay time. The time duration when

the output gets out of the steady-state value of the signal level for

the first time is known as overshoot time. This parameter is currently

one of the key parameters while coping with buffers, since it is

Manuscript received September 10, 2011; revised April 4, 2012; acceptedJuly 21, 2012. Date of publication August 31, 2012; date of current versionJuly 22, 2013.

M. Mehri, M. H. M. Kouhani, and N. Masoumi are with the Depart-ment of E lectrical and Computer Engineering, University of Tehran, Tehran14395-515, Iran (e-mail: [email protected]; [email protected];[email protected]).

R. Sarvari is with the Sharif University of Technology, Tehran 16846-13114,Iran (e-mail: [email protected]).

Digital Object Identifier 10.1109/TVLSI.2012.2211629

1063-8210/$31.00 2012 IEEE

Fig. 1. CMOS buffer.

comparable to conventional propagation delay of the buffer [14]. We

have presented an expression for this parameter based on our novel

macromodel of the overshooting effect. The nonlinear operation of

a MOS transistor results in nonlinear resistance and capacitance in

the model. Averaging these parameters in time interval when the

input signal changes is a typical solution which is used in this brief.

Technology transportability is an advantage of this model which most

of the models may lack. The analytical model for delay in [16]

benefits from the advantage of portability. Likewise, in this brief, we

develop a closed-form expression to estimate the output resistances of

a CMOS buffer. This model depends on device technology parameters

and the input signal transition time. Therefore, there is no need forfitting or extracting parameters, which makes the developed model

technology portable.

What distinguishes this brief from the others is the fact that most

of the overshoot models [6][15] have used the dynamic behavior

equation of an inverter derived from Kirchhoffs Current Law (KCL)

at the output node. In contrast, our new proposed overshoot model is

based on intuition and curve fitting, simultaneously, still completely

in analytical form.

This brief is organized as follows. The alpha power modeling is

discussed in Section II. The output resistance of the buffer, and the

relevant derivations and integration expressions are addressed in this

section. Analytical expressions for the newly proposed model are

presented in Section III. Additionally, simulations and verification

procedures are performed in this section. In Section IV, the over-shooting effect is modeled as a zero generated by the input-to-output

coupling capacitance of MOS transistors in the transfer function.

Finally, summary and conclusion are provided in Section V.

II. ALPHAP OWERM ODELING

In VDSM, the Shockley transistor model is no longer valid.

This happens because of short channel effects such as mobility

degradation, drain-induced barrier lowering, and velocity saturation.

Therefore, in order to accomplish a better analysis, a more accurate

model is required. As such, we utilize the currentvoltage character-

istic of an MOS transistor expressed in [1] and [2] as follows:

iD=

ksub e(vGSvTH) [1 exp(vDS)], @ sub.thre.

kl(vGS vTH)2vDS, @ l in.

ks(vGS vTH)(1 + vDS), @ s at.(1)

A conventional CMOS buffer (simply an inverter) is made of

NMOS and PMOS transistors, as depicted in Fig. 1.

The Cin, Cout, and Rout model the equivalent input and

output capacitances of the transistors, and the output equivalent

resistance, respectively. For timing analysis, all these model elements

must be averaged in time when the input signal transits between two


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TABLE II

MINIMUMBUFFERO UTPUTCAPACITANCE, I NPUTC APACITANCE,

AN DO UTPUTRESISTANCE

Tech. 90 nm 65 nm 45 nm

Cout,fall 0 .534 fF 0.423 fF 0.304 fF

Cout,rise 0 .891 fF 0.632 fF 0.439 fF

Cout_buffer= (Cout,fall+ Cout,rise)/2

0 .713 fF 0.528 fF 0.372 fF

Cin,fall 0 .402 fF 0.289 fF 0.211 fF

Cin,rise 0 .546 fF 0.327 fF 0.195 fF

Cout_buffer= (Cin,fall+ Cin,rise)/2

0 .474 fF 0.308 fF 0.203 fF

RNMOS 7.50 k 12.50 k 20.94 k

RPMOS 11.51 k 16.82 k 25.79 k

Rbuffer= (RNMOS+ RPMOS)/2

9.50 k 14.65 k 23.36 k

TABLE III

ANALYTICALRESULTS FORNMOS, PMOS, A ND BUFFER


RNMOS,fall 7.41 k 12.53 k 20.69 kRNMOS,rise 7.41 k 12.53 k 20.69 k

RPMOS,fall 11.41 k 16.92 k 25.49 k

RPMOS,rise 11.41 k 16.92 k 25.49 k

Rout,fall 9.41 k 9.41 k 9.41 k

Rout,rise 14.73 k 14.73 k 14.73 k

Rbuffer=(Rout,fall+Rout,rise)/ 2 23.09 k 23.09 k 23.09 k

TABLE IV

COMPARISONBETWEENHSPICE A ND A NALYTICALRESULTS

Tech. Error = (Rbuffer,HSPICERbuffer,Analytic)/Rbuffer,HSPICE90 nm 0.95%

65 nm

0.55%

45 nm 1.16%

are shown in Fig. 3(c) and (d). Based on [20], for tpd we have

tpd= L n(2) Rout(Cin + 2Cout)= 0.69Rout(Cin + 2Cout). (9)

Inserting the model parameters from simulation into the analytical

expressions (4)(7) for the resistors, we obtain the results summarized

in Tables II and III.

Table IV shows a comparison between HSPICE simulation results

and those obtained from the analytical expressions. As it can be seen

from this table, the error is less than 2% for 45 nm.The conventional model for an inverter of the size k with respect

to a minimum-size inverter in a given technology is given as follows:

Rout=Rout0

k, Cout= kCout0, Cin= kCin0 (10)

where

k= WPWP0

= WNWN0

(11)

and WN0 and WP0 are the minimum NMOS and PMOS transistor

sizes, respectively. Based on the HSPICE simulation results shown

in Table V, as the technology shrinks, the error of (10) decreases.

The new relations that are based on curve-fitting results for Rout

TABLE V

PERCENTAGEE RROR OFAGREEMENTBETWEENRout AN DHSPICE


(10)

Rout0 7608 11 880 20 790

Min.%Err.

0.00% 30.50% 10.31%

Max.

%Err.

0.24% 51.99% 17.08%

Avg.%Err.

0.03% 45.55% 16.41%

(12)

a 0.002 0.073 0.086

Rout0 7621 12 620 21 480

Min.%Err.

0.00% 0.03% 0.01%

Max.

%Err. 51.92% 42.57% 28.81%

Avg.

%Err. 17.02% 13.30% 8.76%

(13)

a 0.305 0.089 0.123

Rout0 7740 12 260 20 940

Min.

%Err. 0.03% 0.04% 0.13%

Max.

%Err. 51.23% 43.83% 30.04%

Avg.%Err.

16.90% 14.32% 9.79%

(14)

a 0.004 0.004 0.003

Rout0 7130 11 730 20 000

Min.%Err.

0.00% 0.00% 0.01%

Max.%Err.

32.88% 19.79% 9.75%

Avg.%Err.

9.85% 5.89% 2.67%

are as follows:

Rout=Rout0

k+ a

k(12)

Rout=Rout0k2 + ak

(13)

Rout=Rout0

k eak. (14)

Table V presents the results obtained from curve fitting for these

models compared with HSPICE simulations.

For modeling crosstalk on neighboring interconnects in VLSI, oneshould find the value of Rout in coupling situation. When the buffer

of the quiet line, known as victim line, is tied to Vdd or gnd, the

NMOS or PMOS transistor, respectively, is ON and is operated in

the deep triode region. Therefore, the value of Rout depends on the

transition of the signal on the quiet line, and new expressions must

be used. The deep triode region resistance is depicted by RON, and

can be expressed as follows:

RON_N=vDS

iD |vGS=vDD= vDS

klN(vGS vTH)2vDS

= 1klN(vDD vTH)

2

(15)


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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 8, AUGUST 2013 1571

TABLE VI

RONN AN D RONP F OR 90-, 65-, A ND 45-nm TECHNOLOGIES

Tech. HSPIC E ( 15) and (16) %Error

RON_N

90 nm 2.18 k 3.01 k 38%

65 nm 3.42 k 5.12 k 50%

45 nm 6.17 k 10.20 k 65%

RON_P

90 nm 3.50 k 4.82 k 38%

65 nm 5.61 k 8.17 k 46%

45 nm 10.79 k 16.61 k 54%

Fig. 4. Accurate model for CMOS buffer.

RON_P=vSD

iD |vSG=vDD= vSD

klP(vSG |vTH|)2vSD

= 1klP(vDD |vTH|)

2

. (16)

In Table VI we have summarized the results obtained from HSPICE

and analytical expressions for RON_N and RON_P for 90-, 65-, and

45-nm technologies.

IV. MODELING THEOVERSHOOTINGEFFECT

Due to the gate-to-drain capacitance of MOS transistors Cgd , the

input can couple directly to the output. By taking such an influence

into effect, we reach to an equivalent circuit for the buffer involving

the average output resistors as well, as illustrated in Fig. 4. In this

circuit, the transistors are modeled as switches, which are closed or

open depending on the input ramp, falling or rising for the PMOS and

vice versa for the NMOS. By carefully analyzing the circuit shown

in Fig. 4, we find that it would result in the output waveform as an

outcome. However, the classic method of finding the transfer function

using the dynamic behavior equation of an inverter derived from KCL

at the output node would be a laborious. Besides, the topology of

the circuit in Fig. 4 varies several times as the input rises or falls.

This leads to a multistatement expression for the output waveform.On the other hand, the exact times that the circuit topology varies

are also extra parameters, which must be calculated depending on

many characteristics of the circuit. Accordingly, by intuition we have

modeled the output waveform by simple and accurate expressions

[(17) and (18)], which comprised two poles and a zero. These simple

expressions, modeling the overshooting effect, are verified to be in

a good agreement with the HSPICE results. For modeling this fact,

we have assumed that Vout can be written as (17) and (18) for step

fall and rise inputs, respectively.

As it can be seen from Fig. 5, the effect of zero makes the Vout fall

down to 40 percent ofVdd for the CMOS buffer in 90-nm technology.

This phenomenon produces error in estimating the propagation delay.

Fig. 5. Comparison between HSPICE simulation and (17).

Fig. 6. Comparison between HSPICE simulation and (18).

It may also damage the load buffer if it exceeds the breakdown

voltage of MOS in VDSM

Vout,rise(t)= Vdd (1 + kexp(at) (k+ 1) exp(bt)) (17)Vout,fall(t)= Vdd (kexp(at)+ (k+ 1) exp(bt)) (18)

where

a=1 + Cout

Cgd

RoutCgd, b= 1Rout

2 (Cout+CL), k= Cout

(Cout+CL+Cgd) .

(19)

The parameters a, b, and k are achieved by intuition and curve

fitting, simultaneously. Figs. 5 and 6 show the Vout of the buffer

with CL = 1 fF, simulated by HSPICE and calculated using (17)and (18) for the falling and rising input for the 90-nm technology

node

tOvershoot= tUndershoot=1

a bLn

ak

b (k+ 1)

(20)

VOvershoot= Vdd

1 + kexp

a

b aL n

ak

b (k+ 1)

(k+ 1) exp bb aLn

ak

b (k+ 1)

(21)

VUndershoot= Vdd kexp

a

b aLn

ak

b (k+ 1)

+(k+ 1) exp

b

b aLn

ak

b (k+ 1)

. (22)

V. CONCLUSION

In this brief, we studied buffer modeling and derived an expression

for minimum-size buffer resistance. In CMOS buffer modeling, we

employed alpha power law expression for MOS devices. HSPICE

simulations showed that using the alpha power model for the MOS


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in buffer leads to very accurate results. This error was less than 2%

for 45-nm process technology. Also a new expression was proposed

for a buffer ofk-size relative to the minimum buffer size. The average

error of the proposed model for 45-nm technology was less than 3%,

while with the conventional model error was 10% compared to the

HSPICE simulations. Also a new resistance was introduced for the

buffer that can be used in calculation of crosstalk. Eventually, we

improved our macromodel by taking into account the influence of

the overshooting effect which was modeled as a zero generated bythe input-to-output coupling capacitance of MOS transistors in the

transfer function of the component.

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new approach to vlsi buffer modeling, considering

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