new concerto™ f28m35x microcontrollers - Компэл · 2019. 8. 2. · concerto ™ college...

Concerto™ F28M35x Microcontrollers

TI has a broad and growing embedded processing portfolio

Software & Dev. Tools

32-bit ARM ®MCUs

16-bit ultra-low power

MCUs

DSPDSP+ARM®

32-bit ARM ®MPUs

Digital Signal Processors (DSPs)Microcontrollers (MCUs)

32-bit real-time

MCUs

Ultra Low power

DSPs

MulticoreDSPs

TI Embedded Processors

ARM®-Based Processors

Concerto™ College

MPUs – Microprocessors

Stellaris ®ARM® Cortex™-M3MSP430™

Up to 80 MHz

Up to 25 MHz

C2000™Concerto™

Delfino ™

Piccolo ™

40 MHz to 300 MHz

Sitara ™ ARM® Cortex™-A8

& ARM9

C6000™C6-Integra ™

Value line to 600 MHz

Perf. Line to1.5 GHz

300 MHz to >1.5GHz Floating point +

Video Accelerators

C5000™

Up to 10GHzMulti-core,

fixed/floating+ Accelerators

C6000™ DaVinci ™

Video processors

MCUs MCUs DSPs

Up to 300 MHz16-bit fixedpoint + FFT Accelerator

What is C2000™?The 32-bit real-time microcontroller family

System IntegrationC2000

Processing Performance

• Embedded Flash

• On-chip analog

• Ease of use

• Scalability

• DSP performance

• Up to 300-MHz CPU

• Control optimized

• Fixed and floating point

• Best of both worlds

• Math-optimized 32-bit core

• Analog integration

• Powerful peripherals

Concerto™ College

• DSP performance within a Microcontroller architecture

– 40-300MHz C28x™ CPU• Built-in DSP functions• Single-cycle 32×32-bit MAC

– Control Law Accelerator– Floating-point unit– Viterbi and Complex Math Unit– Embedded flash

• Fine-tuned for real-time control– Optimized core– Fast interrupts– Flexible interrupt system– Real-time debugging

• Comprehensive Peripheral Set– Best-in-class ADC performance– Flexible high-resolution PWMs– Advanced capture, Quadrature encoder interfaces– CAN, LIN, SPI, I2C, SCI/UART, McBSP, USB

• Broad portfolio of configurations– 40-300 MHz – Fixed- and floating-point devices– Multi-core with ARM® Cortex™-M3– 16-1024KB of Flash– From sub $2 to $20– Software compatibility across C2000 platform

Solar Power Inverters

Wind Power Inverters

C2000LED Street Lighting

White Goods Industrial Drives & Motion Control

E-bike

Power Tools

DC/DC Converters

Renewable Energy

Digital Power

Digital Motor Control

Lighting

C2000 Sample Applications

Concerto™ College

C2000

Telecom / Server AC/DC Rectifiers

Uninterruptable Power Supplies

Electric Power Steering

Radar / Collision Avoidance

LED TV Backlighting

Hybrid Electric Vehicles

Auto HID

Power Line Communication

Laser Ranging

RFID Readers

Medical Oxygen Concentrators Optical

Networking

Automotive Precision Sensing & Control

Concerto™ College

What is Concerto™ ?

Concerto™ Family: New System Architecture

Host Controller

CommunicationsLogic/Profile

Sequencing/Monitoring

Communications (ENET, CAN, SERIAL)

Loop Controller

Real-Time ControlFaster /More Loops

Small Sampling Windows

Classic Control- Additional complexity- Dual developments plusinterface challenges / latency

- Necessary solution depending on isolation boundary trade-offs

Interrupt

Concerto™ College


Host Controller




Loop Controller





Interrupt


Controller

Real-Time Interrupt Priority

Standard MCU- Compromise between idealhost and control capability

Concerto™ College

Real-Time Interrupt PriorityFast Closed Loops

Small Sampling WindowsBackground task for host functionsSub-Prioritization of host functions

host and control capability- Complex tasking / prioritization- Still appropriate for deeply embedded systems

Interrupt


Host Controller




Loop Controller





Interrupt


Controller

Real-Time Interrupt Priority

Standard MCU- Compromise between idealhost and control capability

Concerto™ College


Concerto- Independent sub-systems on asingle device

- Tightly coupled interface- Single platform for development- No compromises

Control Subsystem



Host Subsystem



Real-Time Interrupt PriorityFast Closed Loops

Small Sampling WindowsBackground task for host functionsSub-Prioritization of host functions

host and control capability- Complex tasking / prioritization- Still appropriate for deeply embedded systems

Interrupt

Interrupt

Ecosystem–Operating Systems–Middleware–Software Infrastructure

Communications

Host MCUARM 32b Cortex-M3

Precision Control

–Industry Leading Computational Performance for Control–Latest DSP+ Accelerator HW

Real-Time ControlTI 32b F28x w/ FPU

Control or Communications…Why Compromise? Concerto™

Indu

stry

’s #

1 M

CU

for

gene

ral

purp

ose&

com

mun

icat

ion

rich

Industry’s #1 MC

U for pow

er electronics &

power

Concerto™ College

Communications–Ethernet–USB–CAN, Serials–Wireless–Various Field Busses

Application Layer–Sequencing, Profiles–Diagnostics, Monitoring

–Flexible Highest Resolution, Best Synchronization PWMs–Lowest Control Loop Latency–Robust Control SW Support–High Speed Precision Synchronized Analog–Fine-tuned Control Architecture

+ ADDITIONAL INDUSTRIAL SAFETY

Indu

stry

’s #

1 M

CU

for

gene

ral

purp

ose&

com

mun

icat

ion

rich

Industry’s #1 MC

U for pow

er electronics &

power

-line modem

Control + Connectivity. No compromise.

SharedControl Subsystem

C28x 32-bit CPU VCU Comms Analog Temp Sense ARM® Cortex™-

Host Subsystem

System & Clocking

Control SubsystemPrecision Control

• Industry leading computational performance

• Expanded instruction set

• Industry’s highest-resolution PWMs

Host SubsystemEcosystem for Developers

• Operating System

• Middleware

• SW Infrastructure

Robust Communications• Ethernet• Fieldbus• USB

• Low-latency control loops

• Real-world, modular control software

• High-speed precision analog

• Fine-tuned control architecture

Additional functions• Natural user interface• Motion profile• Safety

• CAN• Serial

Pwr & Clocking• 10 MHz / 30 KHz INT OSC

• 4-20 MHz EXT

• Clock Fail Detect

• 3.3V VREG

• POR/BOR

C28x 32-bit CPUUp to 150 MHz

FPU

VCU

• Viterbi

• CRC

• Complex MPY

• FFT

System6Ch DMA

Comms

• McBSP/SPI/

• I2S

• UART

256-512 KB

ECC Flash

20 KB ECC RAM

64 KB ROM

128-bit Security

16 KB Parity RAM

Memory

Control Modules

3 x 32-bit eQEP

6 x 32-bit eCAP

9x ePWM Modules:

18x Outputs / 16x HR

Fault Trip Zones

12b, 10ch, 2SH, 3 MSPS

3ch Analog Comparator

Analog

12b, 10ch, 2SH, 3 MSPS


Temp Sense

2 KB Message

Parity RAM

2 KB Message

Up to 64 KB

ARM® Cortex™-M3

32-bit CPUUp to 100 MHz

Communications

4x SSI

2x I2C

5x UART

2x CAN

USB OTG FS PHY

10/100 Ethernet MAC

1588 w/ MII

256-512 KB

ECC Flash

16 KB ECC RAM

64 KB ROM

16 KB Parity RAM

Memory

External Interface

2x128-bit Security

System & Clocking

32Ch DMA

4 Timers

2 Watchdogs

10

Starting at

$6.99 @ 1K

F28M35x – First Series in Concerto Markets: Advanced Metering, Automotive EPS, Motion Control & Drives, UPS, Renewable Energy, Power & Protection, Medical Process Control, Smart Sensors

• Multiple Performance Options– 60, 75, 100, 150 MHz C28x Floating Point– 60, 75, 100 MHz Cortex-M3 CPU

• Large Internal Memory– 512kB to 1MB Embedded Flash– 72kB to 132kB Embedded SRAM– ECC, Parity, and HW BIST

• Robust Communications– 10/100 Ethernet MAC with 1588– USB 2.0 OTG w/ integrated PHY– Dual CAN– Multiple SPI, UART, I2C

F28M35xARM Cortex-M3


Sh

ared

Communications

4x SSI

2x I2C

5x UART

2x CAN

USB OTG FS PHY

10/100 Ethernet MAC

1588 w/ MII

12b, 10ch, 2SH, 3MSPS

AnalogPwr & Clocking• 10 MHz / 30 KHz INT OSC

256-512 KB

ECC Flash

16 KB ECC RAM

64 KB ROM

16 KB Parity RAM

Memory

2 KB MessageParity RAMDebug

Mas

ter

Su

bsy

stem

System & Clocking32Ch DMA

Temp Sense

External Interface

2x128-bit Security

4 Timers; 2 Watchdogs

uCRC Engine

11

144 QFP 0.5mm; 208/256 BGA 1mm (15x15) 1050C/1250C and Q100

– Multiple SPI, UART, I2C– 8/16/32-bit External Memory Interface

• Flexible Control Peripherals– Enhanced PWMs w/ ~150ps resolution per

channel and new flexible fault management– Two high-speed 12-bit ADCs each with 2S/H

and Jitter measurement – Analog Comparators w/ Internal DAC

Reference

• 144-pin PowerPad QFP, 256 BGA• Industrial and Automotive Temp

– -40 to 1050C, -40 to 1250C (AEC Q100)

• Functional Safety Documentation


FPU

Control Modules

3 x 32-bit eQEP

6 x 32-bit eCAP

9x ePWM Modules:


Co

ntr

ol S

ub

syst

emS

har

ed 12b, 10ch, 2SH, 3MSPS3ch Analog Comparator

• 10 MHz / 30 KHz INT OSC

• 4-20 MHz EXT


• 3.3V VREG

• POR/BOR

2 KB Message

2 KB MessageRTJTAG

VCU• Viterbi

• CRC

• Complex MPY

• FFT

System6Ch DMA

Comms•McBSP/I2S/SPI

•SPI

•I2C

•UART

256-512 KB

ECC Flash

20 KB ECC RAM

64 KB ROM

128-bit Security

16 KB Parity RAM

Memory



Fault Trip Zones

Up to 64 KB

Masterable

75 / 75

150 / 75or

100 / 100

F28xFPU / CM3 (MHz)

F28M35x Series

H20B2 H22B2 H50B2 H52B2

H20C2 H22C2 H50C2 H52C2

H32B2

H32C2

E20C1 E22C1 E50C1 E52C1

M20B1 M22B1 M50B1 M52B1

M20C1 M22C1 M50C1 M52C1

H20B1 H22B1 H50B1 H52B1

H20C1 H22C1 H50C1 H52C1

E32C1

M32B1

M32C1

H32B1

H32C1

Available 3Q12

FLASH2 = 256 KB each core3 = +256 KB *5 = 512 KB each core

60 / 60

* +256 KB is for the M3 in Connectivity devices, for the C28x in Base devices

E20B1 E22B1 E50B1 E52B1

E20C1 E22C1 E50C1 E52C1

E32B1

E32C1

Part Number Decoder: F28M3 5 H 5 2 C 1 RFP TF28M3 = Concerto™SERIES NUMBER

PERFORMANCEH = 150 / 75 MHz or 100 / 100 MHzM = 75 / 75 MHzE= 60 / 60 MHz

RAM0 = 132 KB2 = + 64 KB masterable

PERIPHERALSC = ConnectivityB = Base

PINS1 = 144-pin QFP2 = 283-pin BGA

PACKAGE

TEMPERATURET = -40C to 105CS = -40C to 125CQ = -40C to 125C Q100

F28M3CM-3

MHz

C28x

MHz

Flash

(KB)

RAM

(KB)

VREG

(POR

/BOR)

F

P

U

V

C

U

C

L

A

Analog

Comp.

12-bit

ADC Chan. /

Speed

PWM

(HRPWM)

Outputs

Capture

InputsQEP

USB

(OTG) /

Ethernet

Comm

PortsPkg/ Temp I/O Pins

5E20 60 60 512 72 Yes Y Y - 6 20 / 4.6MSPS 18+6† (16) 6 3 Option* 5 SPI/UART, 6SCI, 3 I2C, 2 CAN, 1 McBSP LQFP-144, Up to 125°C 64


5E32 60 60 768** 136 Yes Y Y - 6 20 / 4.6MSPS 18+6† (16) 6 3 Option* 5 SPI/UART, 6SCI, 3 I2C, 2 CAN, 1 McBSP LQFP-144, Up to 125°C 64



5M20 75 75 512 72 Yes Y Y - 6 20 / 4.6MSPS 18+6† (16) 6 3 Option* 5 SPI/UART, 6SCI, 3 I2C, 2 CAN, 1 McBSP LQFP-144, Up to 125°C 64


5M32 75 75 768** 136 Yes Y Y - 6 20 / 4.6MSPS 18+6† (16) 6 3 Option* 5 SPI/UART, 6SCI, 3 I2C, 2 CAN, 1 McBSP LQFP-144, Up to 125°C 64

Concerto™ 5 -Series



5H20 75/100 150/100 512 72 Yes Y Y - 6 20 / 4.6MSPS 18+6† (16) 6 3 Option* 5 SPI/UART, 6SCI, 3 I2C, 2 CAN, 1 McBSP LQFP-144, Up to 125°C 64


5H32 75/100 150/100 765** 136 Yes Y Y - 6 20 / 4.6MSPS 18+6† (16) 6 3 Option* 5 SPI/UART, 6SCI, 3 I2C, 2 CAN, 1 McBSP LQFP-144, Up to 125°C 64



* Each coguration has a “C” version for Connectivity, which includes USB and Ethernet, and a “B” version for Base, without USB and Ethernet** An extra 256KB of Flash is provided to the Cortex-M3 in the Connectivity versions, but in Base versions the 256KB of Flash is provided to the C28x.† Each capture unit can provide one additional PWM output when not used as a captureNote: Prices are budgetary and subject to change

• Performance/Memory:• 28x Core : Up to 150 MHz, Floating Point Unit• ARM Cortex M3: Up to 125 MHz• Up to 1.5MB Flash (1024 KB ARM / 512 KB 28x)• >200 KB SRAM, Up to 128 KB ROM

• Features:• Interfaces: UART, SPI, I2C, CAN 2.0, USB 2.0,

Ethernet MAC 10/100, DMA , 16-bit EPI• Multi-channel buffered serial port (McBSP) • VCU Accelerator• Up to 18 enhanced PWM channels (ePWM)

Concerto™ Concerto™ -- F28M36x SeriesF28M36x SeriesF28M36x

Sh

ared

Communications

4x SSI

2x I2C

5x UART

2x CAN

USB OTG FS PHY

10/100 Ethernet MAC

1588 w/ MII



AnalogPower & Clocking• 10 MHz / 30 KHz INT OSC

• 4-20 MHz EXT


• 3.3V VREG

• POR/BOR

256-1024 KB

ECC Flash

16 KB ECC RAM

64 KB ROM

112 KB Parity RAM

Memory

2 KB MessageParity RAM

2 KB Message

Debug

RTJTAG

Ho

st S

ub

syst

em




Temp Sense

External Interface

2x128-bit Security

Up to 64 KB

Masterable

4 Timers

2 Watchdogs

ARM Cortex-M332-bit CPU

Up to 125 MHz

• Up to 18 enhanced PWM channels (ePWM)• High resolution PWM channels, 150ps resolution• Dual 12-bit ADC, up to 3 MSPS, (Shared)• Up to 6x analog comparators + 10-bit DAC with

slope compensation • 32-bit enhanced input capture module (eCAP)• Quadrature encoder interfaces (QEP) • Dual on-chip oscillators with clock fail detect• Automotive Q100 qualified with full temp range

• Applications:• Motor Control & Drives, Automotive

Transportation, Renewable Energy, Power & Protection, Smart Metering

14

Control Modules

3 x 32-bit eQEP

6 x 32-bit eCAP

12x ePWM Modules:


Co

ntr

ol S

ub

syst

em


•SPI

•I2C & UART

256-512 KB

ECC Flash

20 KB ECC RAM

64 KB ROM

128-bit Security

16 KB Parity RAM

Memory

Fault Trip Zones

Masterable

C28x 32-bit CPU150 MHz

Floating Point Unit

VCU Accelerator

System6Ch DMA

TMX Samples: 2Q’12, RTP 4Q’12

150 / 75or

F28xFPU / CM3 (MHz)

H63B2 H63B2 H63B2 H63B2

H63C2 H63C2 H63C2 H63C2

H63B3

H63C2

F28M36x Series

125 / 125

FLASH2 = 256 KB each core3 = +256 KB *5 = 512 KB each core6 = 1MB on M3 Core

15

Part Number Decoder: F28M3 6 P 6 3 C 2 ZWT TF28M3 = Concerto™

SERIES NUMBER

PERFORMANCEP = 150 / 75 MHzor = 125/ 125 MHz

RAM0 = 72 KB2 = + 64 KB masterable3 = + 96 KB M3

PERIPHERALSC = ConnectivityB = Base

PINS2 = 289-pin BGA

PACKAGE

TEMPERATURET = -40C to 105CS = -40C to 125CQ = -40C to 125C Q100

Concerto Safety Features

F28M35x

ARM Cortex-M332-bit CPU

Up to 100 MHz

Communications

4x SSI

USB OTG FS PHY

10/100 Ethernet MAC

1588 w/ MII

256-512 KB

ECC Flash

16 KB ECC RAM

Memory

Mas

ter

Su

bsy

stem

System & Clocking 2x128-bit Security

Two core independent redundancy with

monitoring

CPU BIST (self test), Real-time Memory PBIST,

Power-on Self Test

Flash and RAM ECC: 1-bit auto-correct, 2-bit

detect

3 Memory Secure Zones

• Helping customers certify their SYSTEM to IEC61508 or ISO26262

• Exida Certification in process for use in SIL3 safety systems


FPU

Control Modules

3 x 32-bit eQEP

6 x 32-bit eCAP

9x ePWM Modules:


Co

ntr

ol S

ub

syst

emS

har

ed

4x SSI

2x I2C

5x UART

2x CAN



AnalogPwr & Clocking


• 4-20 MHz EXT


• 3.3V VREG

• POR/BOR

64 KB ROM

16 KB Parity RAM

2 KB Message

Parity RAM

2 KB Message

Debug

RTJTAG

Mas

ter

Su

bsy

stem

VCU

• Viterbi

• CRC

• Complex MPY

• FFT

System6Ch DMA


•SPI

•I2C

•UART

256-512 KB

ECC Flash

20 KB ECC RAM

64 KB ROM

128-bit Security

16 KB Parity RAM

Memory




Fault Trip Zones

Temp Sense

External Interface

2x128-bit Security

Up to 64 KB

Masterable

4 Timers; 2 Watchdogs

uCRC Engine

ADC Calibration, Self Test, Redundancy, Fail

Monitoring, DAC Checker

System clock auto-switch, On-Chip clock

and oscillator, soft-shutdown, PWM trip

Lock protection on GPIO and system registers

Smart, uncorruptableshared memory, secure

inter-processor communication

Memory CRC, Interrupt parity, SRAM parity, CAN

parity …

Concerto Safety Features

Redundancy for functionsError detection and correction

• Two cores allow each core to check on the other to ensure accurate execution

• Two ADCs give ability to reliably monitor input measurements

• Up to 1MB of 65nm Flash & 132K RAM with error correction (ECC)

• Parity on CAN and interrupt registers

• Cyclic Redundancy Checking (CRC)

Security

• Lock protection on GPIO and registers• Memory protection for software IP safeguarding• Permanently disable JTAG for anti-theft protection

• Two clocks for backup

• Multiple system watch dogs

• Cyclic Redundancy Checking (CRC)

• Comparators for over-current & over-voltage protection

ADC and PWM Verification• ADC verification

– Both converters share (4) inputs• ADC1A0 = ADC1A0 & ADC2A1• ADC1B0 = ADC1B0 & ADC2B1• ADC2A0 = ADC1A1 & ADC2A0• ADC2B0 = ADC1B1 & ADC2B0

– Redundant channels do not waste pins– Both converters have DACs to test

ADCs over full voltage range– Results available to both M3 and C28

18

• PWM verification– Connect PWM output to ADC input via

RC filter– Connect PWM output to input captures

• Inverter verification– Connect PWM signal from the inverter

phases to inputs captures

• Fault-safe– PWM trip zones disable PWMs in 20ns

Communications Verification• DCAN

– Mailbox RAM Parity– Internal Loopback

• TX signal internally connected to RX

• RX input buffer disconnected• TX buffer is active• Acknowledge bits are ignored

– External Loopback• TX needs to be connected

externally to RX• Acknowledge bits are ignored

• SCI– Internal Loopback


• TX and RX FIFO active– M3 can “listen” to C28 SCIA TX

• C28.SCIA connected to M3.UART4

• SPI– Internal Loopback


19

• Acknowledge bits are ignored• Tests in addition the RX and TX

path– Internal Loopback with Silent Mode

• Internal loopback with TX buffer disabled

• Allow test of DCAN controller without affecting connected CAN network

RX• TX and RX FIFO active

– M3 can “listen” to C28 SPIA TX• C28.SPIA connected to M3.SSI3

Concerto™

Concerto™ College

Concerto™Applications Examples

Concerto™ -based Drive or Soft Start

ControlMultiple Loops

Meta Language Tools

HostOS / RTOS

Communication BridgeMotion Profile

Supervisor

Fieldbus, ENET, USBCAN, SPI, UART

SDRAMFLASH

SENSORS

WIRELESS

REDUNDANTCONTROL LOOP CHECKS

Meta Language Tools

PWMsENCODERSERIALADC INTF

ISOLATION

COMMS TO OPTIONALSAFETY MCU

Concerto ™

I

MAXCUM

ABCDE kWhREACTEST kW

SCI

1.8V 3.3V

TL3842Isolated AC/

DC

TPS70251Dual LDO

SCI

Concerto™ -based E -meterwith Firmware Upgradeable Power Line Communications

CC2530 Zigbee SoC802.15.4

Home Area Network

HostSystem Management

MSP430FE42xAE-Meter SoCRTC, LCD

I

VESP..

.

SCI

Metrology

SCI802.15.4

MCU,Radio, PA/LNA

AFE03x

PLC front End

Power Line ModemFirmware Upgradeable

PRIME, G3 OFDM

System ManagementInterface to AFE and HAN

Concerto™ -based Solar Inverter (string)

ControlMPPT

BOOST

HostOS / RTOS

Communication BridgeSafety & Supervisory

ENET, USBCAN, UART, I2C, SPI

SDRAMFLASH

SENSORS

WIRELESS

SYSTEM IO & DIAGNOSTICS

META LANGUAGECONTROL LOOP DESIGN TOOLS

DATALOG

BATTERYBOOST

INVERTERISLANDING

18 PWMMulti-Rail

12-bit ADCSERIAL HSADC INTF

ISOLATION

DC MUX DC BOOST

DC-AC INVERTER

MAINS

BATTERYCHARGING

Concerto™ -basedElectric Power Steering

ControlPrecision- Low Latency

HostRTOS

CAN NetworkSupervisor

ISOLATION CAN

EEPROM-CAL


SYSTEM ADC- Temp, Ref V- Tach- Redundant

Checks

Precision- Low LatencySafety CriticalMotion Control

PWMsRedundant PWMs

Safety Trips

ENCODERSADC- Resolver- V, I, Torq- Commands- Wheel Pos

Concerto™ -basedIntegrated Power Monitor

ControlPower Supply Analysis

HostOS / RTOS

Communication BridgeSupervisor

ENET, USBCAN, UART, SP

SDRAMFLASH

SENSORS

WIRELESS

HMIDISPLAY


Power Supply AnalysisMulti-ChannelDSP Capability

PWMs12-BITHS ADC

H-RESADC INTF

ISOLATION

Getting Started with Concerto™

Concerto™ College

C2000 Software and ecosystem: controlSUITEDownload from www.ti.com/controlSUITE

1. Main Navigation

2. Expand on a kit, device, or topic

3. Find projects, 3. Find projects, documentation, and more

View this video demo of controlSUITE!

IPC

Messaging A

PI

Control

Concerto ™ ecosystem: controlSUITE ™

Host

BIOS RTOS FreeRTOS

Middleware (Ethernet, USB, CAN)BIOS RTOS SafeRTOS

Customer application codeCustomer application code

C28xFPU ARM-CM3

C28x Header Files

C28x Math & DSP Libs

IPC

Messaging A

PI

C28x Application Libs & API

M3 Headerfiles (MWare)

ARM® Cortex™-M3 Application Libs

ARM Cortex-M3 Graphics & USB Libs

Middleware (Ethernet, USB, CAN)Freeware or 3P

SP

I / UA

RT

IN P

AC

KA

GE

BIOS RTOS SafeRTOS

Concerto ™ ecosystem: CCSv4

Breakpoints on one can cause break event on the other (cross-triggering)

28x Real-time while debugging M3

Concerto Hardware Development Tools

H52C1 Experimenter Kit - $139

H52C1 controlCARD - $99

Plug-and-play with any existing controlCARD-based development kit• Includes Ethernet, microSD, and microUSB OTG

ports• JTAG emulation on-board via USB• Orderable part number: TMDXCNCDH52C1

30

DC/DC LED Kit

PLC Modem Developer’s Kit

High Voltage Sensorless FOC DMC + PFC Developer’s Kit

controlCARD can be plugged into existing C2000 kits such as:

H52C1 Experimenter Kit - $139

controlCARD and prototyping area in one kit

• Includes the controlCARD, docking station, and cables

• Orderable part number: TMDXDOCK28069

All development tools examples, software, and hardware files available

free in controlSUITE!

5Vin, Cost Sensitive, Small Solution

DC/DC converter with Integrated FETs

5V, High Efficiency

LDO power solution

*Please visit ti.com/processorpower for COMPLETE power solutions

• 3MHz for Small Inductor

• Low Noise: up to 90dB PSRR

• Low Iq = 22uA

• 12mm 2 solution size

• More fixed Output voltages available

• 2.25 MHz Fixed Frequency Operation

• Fixed Output Voltage Options

• Typ. 15-µA Quiescent Current

• Small SON packaging

Power Options for Concerto™

TPS622911000mA LDO

Used on the H52C1 controlCARD

TPS62237500mA

DCDC ConverterFixed 3.3Vout

12Vin, High Efficiency , Small solution

DCDC Converter with fast

AC line and load transient response

TPS621601000mA

Adjustable Vout

• Input Voltage Range: 3.0V-17V

• Efficiency >90%

• Shutdown current 1.5uA (typ.)

• Small 2x2 QFN package

• More fixed Output voltages available

12Vin, Cost Sensitive

Synchronous DCDC Converter with Integrated FETs

TPS73033200mA LDO

• Wide Input Voltage Range 4.5V–18V

• Low Standby Current

• Short-Circuit Current Limiting

• Small 8 pin DDA with Power pad

• Suitable for ceramic output caps

TPS542272 Amp

DCDC Converter

Concerto™ Details

Concerto System:

�Clocking

Concerto™ College

� Resets and Power

� GPIO MUX

� Boot

F28M35x Clocking

GPIO_XCLKIN

ExternalOscillator

Clocking, Power, Resets

XRSn

PLL

USB PLL

System Reset

/1/2/4

M3 Mastersubsystem

CPU & Peripherals

C28xcontrol

subsystem

USB

CAN x23.3V +/- 10%

OFF/1

100 MHz MAX

150 MHz MAX

Digital VREGVMON

X1

M3: Watchdog 0/1

Oscillator4-20MHz

VREG Analog Reset

10MHz10MHzOSC

32KHzCLK

PLL

OFF/1/2/4/8

AXRSn

subsystem CPU and

Peripherals

/1

37.5 MHz MAX

ANALOGsubsystem

VMON

Clock MonitorLow Power Modes

X2

Missing Clock

System PLL/1/2/4/8*

OSCCLK

SystemPLL

0*1

PLLSYSCLK150 MHz Max

M3 Read/WriteC28x Read Only**

XPLLCLKOUT Pin/1/2/4*

Master (M3)subsystem

100 MHz Max/1/2/4*

Control (C28x)subsystem

150 MHz Max

on*off

/1

C28x Read/Write

M3 Read/Write

* Default at reset** Semaphore request write

External Xtal4-20MHz

X1

X2

subsystemoff0

37.5 MHz Max

Analog

off/1/2/4/8*

System PLL supports a spread spectrum mode

C28x MHz M3 MHz Analog MHz ADC MSPS EPI MHz

System Clock Configurations

Maximum Frequencies

C28x MHzCLKIN

M3 MHzM3SSCLK

Analog MHzADCCLK

ADC MSPSADCCLK/13

EPI MHzM3SSCLK/2

150.0 100.0 37.5 2 x 2.885 50.0

Possible Combinations

C28x MHz M3 MHz Analog MHz ADC MSPS EPI MHz

150.0

150.0 (/1) 150.0 (/1)

75.0 (/2) 75.0 (/2) 37.5

37.5 (/4) 37.5 (/4) 2 x 2.885 18.75

18.75 (/8) 2 x .480

100.0 100.0 (/1) 25.0 (/4) 2 x 1.923 50.0

60.0 60.0 (/1) 30.0 (/2) 2 x 2.308 30.0

C28x CLKIN == PLL System Clock

M3 Read/Write

Master Subsystem Clocking

Clock EnablesRun-Mode

Sleep-Mode

Deep Sleep-Mode

WDT1OSCCLK

M3 CPU

M3 Peripherals

SSI, UARTGPIO, EMAC…

M3SSCLK

* Default at reset

USBPLL USB

0*1

OSCCLK

GPIO_XCLKIN 0*

1

60 MHz

GPIO, EMAC…

0*12

OSCCLK Bit Clock

GPIO_XCLKIN

CAN0,CAN1

C28x Read/Write

Control Subsystem Clocking

C28x SYSCLKOUT

NMI WDePWMeCAPeQEPon*

PLLSYSCLK

M3 Read/Write

Clock Enables

C28x CPU

eQEPGPIOI2C…

on*off

HSPCLK SOC PulseSOC Pin

0

* Default at reset

McBSP, SCI, SPILSPCLK

SOC (start of conversion) pulse for ADC – controlled by ePWM logic

Missing Clock Detection Logic

YesClock Fail?

OSCCLK == 10 MHz Internal ClockBypass PLL

No

ePWMsTZ5

Generate NMIStart NMI WD Counters C28x NMIM3 NMI

C28xResponse

?

Handle Error &Standby

Yes

C28 NMI C28 NMI WD

Timeout

No

NoControl subsystem

Reset

Yes

M3Response

?

M3 NMI WD

Timeout

Handle Error

DeviceReset

Yes

Yes

No

No

F28M35x Resets & Power

Device Power and Resets3.3V +/- 10%

(1.2V Optional)Digital

VREG / VMON M3 WDT0M3 WDT1

Missing Clock

M3 NMI WD

M3 CPU(Software & Debugger)

XRSnDevice System Reset Master subsystem Reset

Analog VREG / VMON

C28x Debugger Reset

C28x NMI WD

Analog ResetAXRSn

Control subsystem Reset

F28M35x GPIO MUX

GPIO MUX Overview

PWM Trip

C28x DAT1100

MasterMUX

System(Default)

ControlMUX

System

C28x Read/Write M3 Read/Write

M3 assigns each pin to master (default) or control subsystem. Assignment is then locked for safety.

Pin

Low Power

Qualification

PWM Trip 1100

(Default)

Open Drain

Pull-up:Disabled by defaultEnabled only by M3

GPIOCSELGPIOLOCK

GPIOPUR

Example of GPIO MUX Subsystem Assignment Options

MUX Options Based on Subsystem Assignment

Pin If Assigned to the Master Sub-System

If Assigned to theControl Sub-System

GPIO4 C28x EPWM3AM3 SSIORX CAN0RX U1DSRGPIO4 C28x GPIO

EPWM3A

GPIO5

M3GPIO

M3 GPIO

SSIORX

SSIOTX

CAN0RX

CAN0TX

U1DSR

U1RTS C28xGPIO

EPWM3B

Master GPIO MUX SubsystemAlternate Pin Mapping

C2000 Like

1212 1515

Peripheral Peripheral 12

….….

……Peripheral

15

GPIOPCTL

1100

1515….….

Peripheral 15

….….


Primary Pin MappingStellaris Compatible

Peripheral 1

GPIOPCTL

•• 1100GPIODATAGPIODIR

M3 Interrupt �� NVIC

GPIO or Peripheral

M3 Read/WriteGPIOAMSEL

GPIOPCTLGPIOPCTL

1100

GPIOAPSEL


Control GPIO MUX Subsystem

11

00

22

33

GPxDAT

GPIO Logic

Peripheral Peripheral 2GPxDIR

GPxSETGPxCLEAR

GPxTOGGLE


GPxMUX1/2GPxDAT

Input Qualification

GPxQSEL1/2GPxCTRL

C28x Low Power Wakeup

GPIO0 - 63 ePWM TripeCAP InputXINT1 - 3

C28x Read/Write

GPxMUX1/2

GPTRIPxSEL

F28M35x Boot

Master Subsystem Boot

ResetM3 begins executionBasic device config

WIR

C28x enters idle and waits for an IPC command from

M3 application code

Flash or serial boot determined by

Release C28x and analog from reset

NoWIR?

determined by state of GPIO pins

UART0SSIOI2C0CAN

Flash(Default)

RAMM3 boot ROM flow

EMU0/1 Pins

EMU0/1 Pins

Yes

No

Control Subsystem Boot

WIR?

ResetRelease

from M3?

EMU0/1

Yes

No

NoSetup PIE for IPC commands

C28x boot ROM flowReset held

M3 boot ROM releases the C28x reset

EMU0/1 Pins Yes

Respond to IPC message

Boot as requested by M3 application

Enter IDLE mode

Stay in idle

YesIPC?

M3 application sends IPC command:

Boot to SCI/SPI/I2C, RAM, Flash

No

Wakeup

Concerto™ Details

Host Subsystem�M3 subsystem overview�Interrupt mechanism�Memory

Concerto™ College

�Serial communication (UART, SSI, I²C)�CAN interface�Ethernet interface�USB interface�µDMA�µCRC

Cortex M3 core: architecture• Harvard architecture

• Privileged access and user access

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JTAGDebug port

CortexM3 Interrupts

• Nested Vectored Interrupt Controller (NVIC):– prioritize and handle all exceptions– Automatic interrupt service– Pre-emptive/Nested interrupts implementation– full access from privileged mode

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• Exceptions:– 10 Cortex M3 core exceptions types– Up to 91 peripherals interrupts (GPIOs, UART, USB,..)– Priority grouping

• Process and Main (Handler) stacks

Exception Model• Exception Model handles all interrupts, synchronous faults

and SVC exceptions– Exceptions cause current machine state to be stacked– Stacked registers conform to EABI

• Exception handlers are trivial as register manipula tion carried out in hardware

– No assembler code required – Simple ‘C’ interrupt service routines:

void IRQ(void) { /* my handler */ } PendSVSystick

IRQ0

IRQ1

IRQ91

0x0038

0x003C

0x0040

0x0044

0x0048

0x0118

-2

-1

0

1

91

14

15

16

17

107

VectorOffset IRQnumber

Exceptionnumber

Concerto™ College

PREVIOUS TOP-OF-STACK VALUE

xPSRPCLRR12R3R2R1R0IRQ top of stack

Pre-IRQ top of stack

Initial SP value

Reset

Hard Fault

Memory mgt fault

Bus fault

Usage fault

Reserved

SVCall

Reserved

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

0x002C

-14

-13

-11

-10

-5

-12

1

2

4

5

11

3

NMI

6

CortexM3 interrupts: Tail ChainingHighest

IRQ1

IRQ2

Cortex-M3 Interrupt Handling

ISR 1 PopISR 2

6 Cycles 12 Cycles

Push

12 CyclesTail-Chaining

Concerto™ College

� 12 cycles from IRQ1 to ISR1 (Interrupti ble/Continual LSM)� 6 cycles from ISR1 exit to ISR2 entry� 12 cycles to return from ISR2� 65% cycle overhead saving vs ARM7

Cortex-M3

Interrupt Response – Example

Highest

IRQ1

IRQ2

NMI

IRQ3

Concerto™ College

ISR 2 Start

PopISR 3Push NMI ISR 1 ISR 2Push

�Push for ISR1 begins

�Pre-empted by NMI

�New instruction fetch in parallel minimises time to NMI

�Following NMI processor tail-chains into ISR1

�ISR2 Completed

�Pop only occurs on return to “Main”

CortexM3 Interrupts: tasks&priorities

• Main application runs as foreground (base level)t

High priority ISRs (eg. Timers, fault)

Low priority ISRs (eg. Communication)

Main application (foreground)

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• Main application runs as foreground (base level)– Easy to write since no “factoring” – just normal application or RTOS based– Can use PLC style state-machine poll loop safely: ISRs keep data available

• ISRs for System control are highest priority(ies)– Timer(s), Fault (may be highest), Temp sensor, etc

• ISRs for communications below that– Ethernet, CAN, and/or serial

• May use other priorities as needed– Very fast interrupt response time, true nested interrupts, priority masking, easy ISR

setup all contribute to making an easy solution– Application uses priority masking vs. interrupt-disable if needs critical region

CortexM3 Memory Protection Unit• Cortex M3 memory is split in 8 Protection regions + 1 background region

• Independent settings for each region– Location start address– Size configurable from 32 B to 4 GB– Independent attributes for each region

• Access Privilege (AP)

Privilege Unprivilege Permission faultSuperuser User

R/W R/W noR write by unprivilegedno access from unprivileged

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• Access Privilege (AP)– no access– R/W– Read only

• Overlapping protection regions with region priority

• MPU mismatches and permission violations invoke MemManage fault handler

R R writesno write + read from unpriv

no no all

Host side Memory map

• 64 kB ROM• 512 kB Flash• Up to 96 kB RAM• 4 kB RAM for IPC

0x0000 0000 ROM

0x0020 0000 Flash

0x2000 0000 RAM

0x2000 8000 shared RAM

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0x2000 8000 shared RAM

0x2000 8000 IPC RAM

0x4000 0000 Peripherals

0x6000 0000 EPI

ECC protection

Host side ROM

• Size 64 kBytes (start from 0x0000 0000)

• Access single cycle

• Contains

Concerto™ College

» M3 bootloader code» Mathematic tables» IPC code» AES cryptography table

• Access from M3 only

Host side Flash

• Size 512 kBytes14 sectors

• Access 25 nsec• Access from M3 only

M3 frequency

Wait state Efficiency Effective speed

40 MHz 0 100 % 40 MHz

80 MHz 1 96 % 77 MHzM3 core

Flash performance

Concerto™ College

100 MHz 2 92 % 92 MHz

FLASH Bank (with ECC)

Pre-Fetch Buffer (128-bit)

Fetch Buffer (128-bit)

64

64

32

M3 core

DataCache

interface

InstructionCache

Host side RAM

• Size 96 kB• Access single cycle• Each block is SARAM

C0

C2

S0

S2

S1

S3

C3

C1

C0-C1 C2-C3 S0-S7shared

M2C C2MRead

M3

RR

RRConcerto™ College

S4

S6

M2C

S5

S7

C2M

shared Read

Size 8 kB 8 kB 8 kB 2 kB 2 kB

µDMA No Yes Yes Yes Yes

C28x No No Shared Read Yes

Safety ECC parity parity parity parity

C28

RR

RR

RR

R

RDedicated to M3

Shared with C28 ECC safety

Accessible from µDMA

EPI

Ext

erna

l Per

iphe

ral i

nter

face

Cortex M3

Concerto™ College

Ext

erna

l Per

iphe

ral i

nter

face

µDMA

Serial communication peripherals - UART

• 5 independant UARTs• Max baud rate 12.5 Mbps• Fully programmable serial interface characteristics:

– 5, 6, 7, or 8 data bits– Even, odd, stick, or no-parity bit generation/detection– 1 or 2 stop bit generation

• Efficient transfers using µDMA

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• Efficient transfers using µDMA

• Flexible modes– IrDA serial-IR encoder/decoder for up to 115.2 Kbps half-duplex

– ISO 7816 Support (SmartCard communication)

– Full modem handshake (UART1 only)

Serial communication peripherals - I²C

• 2 independent I²C modules

• Master or Slave - Simultaneous operation as both a master and a slave

• 2 transmission speeds:– Standard (100 Kbps)

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– Standard (100 Kbps) – Fast (400 Kbps)

• Master and slave interrupts support

• Access from M3 only

• Loopback mode available

Serial communication - SSI

• 4 independent SSI• Master or slave modes• Max speed 25 Mbps• Separate Tx and Rx FIFOs

– 16 bits wide

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– 16 bits wide– 8 locations deep

• Frame size from 4 to 16 bits• Efficient transfers using µDMA• loopback mode available

CAN interface

• 2 independent CAN modules compliant with CAN protocol version 2.0 part A/B

• Bit rates up to 1 MBit/s

• 1kB message RAM– 32 message objects– with Individual identifier & mask– Programmable FIFO mode

1 kByte

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– Programmable FIFO mode

• Test features:– Programmable loop-back modes– Direct access to Message RAM

• Automatic bus on with programmable delay • Wake up from deep sleep mode

• No access from µDMA

(safety)

Ethernet MAC

• MAC layer only• 10BASE-T and 100BASE-TX/RX IEEE 802.3

Full/Half-Duplex support• Programmable MAC address• Hardware support for Precision Time Protocol

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• Hardware support for Precision Time Protocol (IEEE 1588 PTP Promiscuous mode support)

• 2KB Transmit FIFO / 2KB Receive FIFO• Efficient transfers using µDMA

USB interface

• Integrated controller with integrated PHY• USB 2.0 full-speed (12 Mbps) / low-speed (1.5 Mbps)• Devices with OTG/Host/Device or Host/Device• Transfer: Control, Interrupt, Bulk and Isochronous• Up to 32 Endpoints

– 1 dedicated control IN endpoint

Concerto™ College

– 1 dedicated control IN endpoint – 1 dedicated control OUT endpoint– 4 KB Dedicated Endpoint Memory

• µDMA efficient data transfer

µDMA

• 32-channels - dedicated for supported peripherals– 8,16 or 32 bits data sizes– Two levels of priority, Maskable device requests

• Multiple transfer modes:

Offset Channel

0x0 0 Prim

ary

0x10 1

…

0X1F0 31

Offset Description

0x0 Source end pointer

0x4 Destination end pointer

Channel Control Structure

Control Structure Memory Map

Concerto™ College

– Basic– Ping-pong– Scatter-gather

• Interrupt on transfer completion with a separate interrupt per channel

0X1F0 31

0x200 0 Alternate

0x210 1

…

0x2F0 31

0x4 Destination end pointer

0x8 Control word

0XC unused

uCRC

• Memory check on M3 sideROM, Flash and RAM (mirrored)

• Polynomials supported– CRC8 Poly 0x07– CRC16 Poly-1 0x8005 CRC8

M3 core

DCODE bus

SYSTEM bus

Flash

RAM

ROM

Concerto™ College

– CRC16 Poly-1 0x8005– CRC16 Poly-2 0x1021– CRC32 Poly 0x04c11db7

• Ability to run on secured memory

µcrcCONFIG

µcrcRES

µcrcCONTROL

CRC8unit

CRC16unit

CRC32unit

SEC-DATA µCRCCRCLock

Concerto™ Details

Control Subsystem�C28 subsystem overview

Concerto™ College

�Processing units�Interrupt mechanism�Memory�DMA �ePWM�Benchmarks

C28 subsystem overview

Sectored

Flash

Program Bus

RAMBoot

ROM

eQEP1-3

ePWM1-9

eCAP1-6

DMA

6 Ch.

DMA Bus

ADC

COMP

Common Interface Bus

M3

Bus

µDM

A B

us

Concerto™ College

32x32 bit

Multiplier

Data Bus

32-bit

Auxiliary

Registers3

32-bit

Timers CPU

Register Bus

R-M-W

Atomic

ALU

PIE Interrupt Manager

eQEP1-3

Watchdog

I2CA

SCIA

SPIA

FPU

McBSPA

VCU

VCU Module

VR0

VR1

VR2

VR3

VR4

VR5CPI I/F

C28x

VCUVCU

ExecutionRegisters

VSTATUS

CRC Unit (CU)

• Supports efficient SW implementation of Viterbi decoder by performing the ADD-Compare-Select and trace back operation in hardware

– 1 cycle branch metrics initialization for CR=1/2 and 2 cycle branch metrics initialization for CR=1/3

– 2-cycle Viterbi butterfly operation– 3-cycle Viterbi traceback operation per Viterbi stage

• Supports generation of CRC8, CRC16 and CRC32 on data stored in memory

– Byte-wise calculation to support PRIME

Viterbi Unit (VU)AU(compleX-

numberarithmetic Unit,

supports Complexnumber

multiplication,MAC and ADD)

Concerto™ College

VR6

VR7

VT0

VT1

C28xCore

VCRC

C28x Mem Bus

VR8 • Supports complex number arithmetic and FFT calculation– 2 cycle complex-number multiplication with

16-bit x16-bit = 32-bit real and imaginary parts– 1 cycle complex-number addition– 2-cycle Complex multiply-and-accumulate (MAC)– A repeat Complex-MAC operation– Instruction to support 5-cycle 16-bit FFT butterfly

Arithmetic Unit (AU)VU

(Viterbi Unit,supports Viterbi ADD-Compare-

SelectOperation)

CU(CRC Unit,

supports CRC8, CRC16

and CRC32)

VCU benefits

0

5

10

15

20

25

Viterbi Viterbi Trace 16-bit Complex 16-bit Complez 16-bit CRC for

250

Cyc

les

~ 7X faster

~ 7X faster ~ 10X

faster

~ 4X faster

~ 25X faster

• Optimized implementation of Viterbi decoder- Performs ADD-Compare-Select & trace back operation

in H/W

• Complex number arithmetic and FFT calculation– 2 cycle complex-number multiplication; 1 cycle

complex-number addition– 2-cycle Complex-MAC

• Generate CRC8, CRC16 and CRC32 on data

Viterbi Unit (VU)

Complex Math Unit (CMU)

CRC Unit (CU)

C28x implementation

VCU implementation

Concerto™ College

RealReal

ImagImagADC 4X faster

16-bit complex

FFT butterflyPower line modem

example

25X perf.

increase

ADCCMU

Complex FFT

VU

ViterbiDecode

7X faster butterfly

5X faster traceback

CU

CRC Check

CMU

Complex Filter

OutOut

ViterbiButterfly

Viterbi TraceBack*

16-bit ComplexMPY/ADD/SUB

16-bit ComplezFFT Butterfly

16-bit CRC forblock length of

10 bytes

* Cycles per stage

• Generate CRC8, CRC16 and CRC32 on data stored in memory

– Byte-wise calculation to support PRIME

C28 + FPU + VCU pipeline

Concerto™ College

C28 interruptPIE C28 CPU

PIECTRL RegPIEACK RegPIEIER1 RegPIEIFR1 Reg

PIEIER12 RegPIEIFR12 Reg

PIERAM Vector

Table(128 vectors)

IER RegIFR Reg

ST1 (INTM flag) Reg

DBGIER Reg

INT1n (highest)

PeripheralSCI, ePWM, eCAPeQEP,ADC, McBSP

DMA, FPU

INT1.1n to INT1.8n

INT12.1n to INT12.8n

Memory wrapperFlash - RAM

WAKEINTLowPower

XINT1Ctl

GPIO0int

Concerto™ College

• 2 non-maskable interrupts (RS, “selectable” NMI)• Interrupt priority is fixed

• 14 maskable interrupts (INT1 – INT14)– 12 multiplexed interrupts through PIE

INT12n (lowest)INT12.1n to INT12.8n

CPU Timer 0

CPU Timer 1

CPU Timer 2

XINT3

XINT2Ctl

Ctl

GPIO0int…

GPIO63int

TINT0

TINT1

TINT2

INT13

INT14

NMINMINT

Control side Memory map

• 64 kB ROM• 512 kB Flash• Up to 100 kB RAM• 4 kB RAM for IPC

0x0000 0000 RAM

0x0000 8000 RAM

0x0000 A000 RAM

0x0000 0AE0 Periph Reg

Concerto™ College

0x0000 C000 shared RAM

0x0003 F800 IPC RAM

0x0010 0000 Flash

0x003F 8000 ROM

Control side ROM

• Size 64 kBytes (start from 0x003F 8000)

• Access single cycle

• Contains

Concerto™ College

• Contains» C28 bootloader code» IPC handline code» math tables for IQ, FPU and PLC

• Access from C28 only

Control side Flash

• Size 512 kBytes14 sectors

• Access 25 nsec (expected)• Access from C28 only

C28 frequency

Wait state Efficiency Effective speed

40 MHz 0 100 % 40 MHz

80 MHz 1 96 % 77 MHz

100 MHz 2 94 % 94 MHz

150 MHz 3 91 % 137 MHzC28 core

Flash performance

Concerto™ College



DataCache

interface


128

32

Control side RAM

• Size 100 kB• Access single cycle• Each block is SARAM

L0

L2

S0

S2

S1

S3

L3

L1

M0-M1 L0-L1 L2-L3 S0-S7shared

M2CRead

C2M

C28

RR

M0 M1

Concerto™ College

S4

S6

M2C

S5

S7

C2M

shared Read

Size 2 kB 8 kB 8 kB 8 kB 2 kB 2 kB

DMA No No Yes Yes Yes Yes

M3 No No No Shared Yes Read

Safety ECC ECC parity parity parity parity

M3

RR

RR

RR

Dedicated to C28

Shared with M3 ECC safety

Accessible from DMAR

R

Direct Memory Access (DMA)

Peripheral Interrupt Trigger Sources

DMA Controller• 6 channels with independent PIE interrupts• Event-based machine• Channel 1 has the ability to be a high-priority channel• 4 cycles/word throughput (5 for McBSP)• Arbitration handing when CPU and DMA both try to access the same interface concurrently

Concerto control subsytem contains a 6-channel DMA

Trigger sourceCPU Timers, McBSPXINTn, ePWM, ADC

McBSPModule

ePWM

DMA Bus

Concerto™ College81

Peripheral Interrupt Trigger Sources• ADC sequencers• external interrupt (XINT1-3)• McBSP• CPU Timers• ePWM Start-of-conversion signals

Data Sources / Destinations• Some RAM zones• ADC result/COMP registers• McBSP transmit/receive buffers• ePWM 1-9 registers

SARAMZones

ePWMModules

ADC/COMPModule

PIE

interrupt

CIB

DMA6-ch

Controller

EPWM Module Enhancements

HR-ACMPA

ActionQualifier

CMPA

CMPB

TBPRD

TBPHS TBPHSHR

FED

RED

CMPAB

16-bitCOUNTER

TBCNT

PWMA

TripAction

PWMB

EPWMTZINTn (to CPU)

MultipleAsyncTripInputs

Analog Comp

CMPAHR

High Res Duty On B Also(~150psec Resolution)

HR-B

CMPBHR

FEDHR

REDHR

CHOPPER

Action Qualifier A

Action Qualifier B

EventFiltering,

Qualification& Blanking

Interrupt

SOC

integer . frac of cycle

Increased Number Of Trigger InputsAnd Logical Combinations

TBPRDHR

Dead-Band(with HR)

Concerto™ College

SOC&

InterruptGen

EPWMINTn (to CPU)

SOCA/C (to ADC)

SOCB/D (to ADC)

Use Dead-Band To Phase Shift B Output Relative To A Output

(~150psec Resolution)

High Res Dead-Band(~150psec Resolution)

31 16.15 8 7 0

integer cycles frac of cycle 0...0

24 bits of PWM Step Range

CMPC

CMPD

CMPC

CMPD

CMPC & CMPD For Finer Positioning Of ADC Start Of Conversion Or Interrupts

•Simultaneous Update Of PRD/CMP RegistersAcross Multiple Modules

FLASH Bank

Pre-Fetch Buffer (64-bit)


64

64

32

C28-CPU/FPU


Pre-Fetch Buffer ( 128-bit )

Fetch Buffer ( 128-bit )

64

64

32

C28-CPU/FPU

180nm, F05 FLASH Technology(all C2000 devices to date)

65nm, F021 FLASH Technology(future C2000 devices, starting with F28M35x)

FLASH Technology & Performance

Data cache

Concerto™ College

FLASH Bank

(Flash: 36ns access time, 27.7MHz)


(Flash: 25.0ns access time, 40MHz)

Math Benchmark: PIDDevice

MHz180nm, F05 FLASH, 64-bit Fetch 65nm, F021 FLASH, 128 -bit Fetch

36ns, 27.7MHz 25.0ns, 40MHz

50 48.0 (1-wait) 96% 48.0 (1-wait) 96%

80 73.6 (2-wait) 92% 76% for FPU (see next slide)

76.8 (1-wait) 96%

100 81.0 (3-wait) 81% 94.0 (2-wait) 94%

150 93.0 (5-wait) 62% 136.5 (3-wait) 91%

Arithm Benchmark(with div, no atan, sin, cos)

FLOAT math IQ math FLOAT math IQ math

Code Running From FLASH (2-wait) Code Running From R AM (0-wait)

Single iteration: 278 (76% FLASH efficiency)

(29% faster then IQ math)

394(94% FLASH efficiency)

210 (44% faster than IQ math)

372

Loop mode:(10 iterations)

2859(76% FLASH efficiency)

(30% faster then IQ math)

4096 (92% FLASH efficiency)

2161(43% faster than IQ math)

3781

TMS320F28335 benchmarks (180nm, F05 FLASH Technolog y)

Benchmark analysis

Concerto™ College

math)

Concerto benchmarks (65 nm, F021 technology)

• Using C28-FPU improves benchmark by 44% over IQ mat h

Arithm Benchmark(with div, no atan, sin, cos)

Float mathCode running from flash(3-wait)

Use parallel instruction(supported by compiler)

150 MHz CPU freq 231 cyc 175 cyc

250 MHz CPU freq 247 cyc 198 cyc

Concerto™ Details

Analog Subsystem�ADCs

Concerto™ College

�Comparators

F28M35xARM Cortex-M3


Sh

ared

Communications

4x SSI

2x I2C

5x UART

2x CAN

USB OTG FS PHY

10/100 Ethernet MAC

1588 w/ MII


AnalogPwr & Clocking• 10 MHz / 30 KHz INT OSC

256-512 KB

ECC Flash

16 KB ECC RAM

64 KB ROM

16 KB Parity RAM

Memory

2 KB MessageParity RAMDebug

Ho

st S

ub

syst

em


Temp Sense

External Interface

2x128-bit Security

4 Timers

2 Watchdogs

Analog Modules – Shared Peripherals



Analog Temp Sense

Concerto™ College86


FPU

Control Modules

3 x 32-bit eQEP

6 x 32-bit eCAP

9x ePWM Modules:


Co

ntr

ol S

ub

syst

emS

har

ed 12b, 10ch, 2SH, 3MSPS3ch Analog Comparator


• 4-20 MHz EXT


• 3.3V VREG

• POR/BOR

2 KB MessageRTJTAG

VCU• Viterbi

• CRC

• Complex MPY

• FFT

System6Ch DMA


•SPI

•I2C

•UART

256-512 KB

ECC Flash

20 KB ECC RAM

64 KB ROM

128-bit Security

16 KB Parity RAM

Memory



Fault Trip Zones

Up to 64 KB

Masterable




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Analog Sub -System

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• Differences from Piccolo ADC– 37.5MHz max ADCCLK– ADC1 & ADC2 shared resources

• (4) shared channels• (8) shared triggers

• ADC based on (2) Piccolo ADCs– (2) 12b converters + (4) S/H– Hybrid, SAR or Pipeline– Ratiometric conversion– (16) or (20) input channels– (32) result registers– (6) analog comparators with

(6)10b DACs– Temp Sensor connected to ADC

1&2

Analog Sub -System

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1&2– (4) or (8) digital inputs, AIOs– VREG with POR/BOR

Accessibility• Round-robin arbitration

1. M32. M3 uDMA3. C28 read4. C28 write5. C28 DMA read/write

• Control system use:– Control loop

• ADC1 & ADC2 triggered for (4) S/H (~us rate)• C28 reads ADC results • C28 writes to DAC, sets comparator threshold

– Safety loop• M3 monitors results from uDMA reads(~ ms rate)• M3 uDMA reads ADC results

• Data acquisition use:– Signal processing

• C28 DMA reads ADC1 results, writes to RAM

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Resource C28 DMA

C28 M3 uDMA

M3

ADC Results yes yes yes yesCOMP_DAC yes yes - -ADC Config yes yes - -

GPIO yes yes - -

• C28 DMA reads ADC1 results, writes to RAM – Network communication

• M3 uDMA reads ADC2 results, writes to RAM

ADC Clock Tree• ADCCLK is synchronous to C28x• CIBCLK = C28CLK/CLKDIV

– CLKDIV= 1, 2, 4, or 8 (default at reset)

– CIB = Common Interface Bus• ADCCLK = CIBCLK

– ADCCLK = (150MHz/4) = 37.5MHz– At reset, ADCCLK = 10MHz OSC

Device ConfigurationExamples

C28 M3 CIBCLK = ADCCLK

ADC1 & ADC2

MHz MHz (Div Ratio To

C28 MHz)

MHz (Div Ratio To

C28 MHz)

MSPS (ADCCLK/13)

Max MIPS Device

150.0 75.0 (/2) 37.5 (/4) 2 x 2.885

Max M3 MIPS Device

100.0 100.0 (/1) 25.0 (/4) 2 x 1.923

Low End MIPS Device

60.0 60.0 (/1) 30.0 (/2) 2 x 2.308

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• 5.77 MSPS Max conversion rate – Each ADC Sample Rate

• 37.5MHz/13 = 2.885MSPS

ADC1 Pin Connections• (6) Analog-only input pins

– A0, B0, A3, B3, A7, B7• (4) shared with AIO & COMP

– A2, A4, B4, A6• (3) DAC outputs to ADC inputs

– B2,B6 (no pin connection)– B4

• COMP2 = (2) analog signals• Temperature on A5

ADC-1 12-bit

16-ch

2 S/HTempSensor

(3.3V) VDDAADC1VREFHI

ADC1A4

ADC1A3

ADC1B4

ADC1B3

DAC 10-bitAIO4

B4

A4B3A3

DAC 10-bit

AIO2

A2

B2

A1B1

A0B0

ADC1A0ADC1B0

VREFHIVDDAVSSAVREFLO

(agnd) VSSA

COMP2A

COMP2B

COMP1A

COMP1

COMP2

ADC1A2

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• Temperature on A5• VREFLO on B5• AIO configured as inputs and

disabled at reset

ADC1B4

ADC1B7

DAC 10-bitADC1A7

AIO6

A6

B6A7B7

B5A5B4

AIO12

COMP2B

COMP3A

COMP3

ADC1A6

ADC2 Pin Connections• (6) Analog-only input pins

– A0, B0, A3, B3, A7, B7• (4) shared with AIO & COMP

– A2, A4, B4, A6• (3) DAC outputs to ADC inputs

– B2,B6 (no pin connection)– B4

• COMP5 = (2) analog signals

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• VREFLO on B5• AIO configured as inputs and

disabled at reset

Shared Analog Inputs• (4) Shared analog input pins:

– ADC1A0 = ADC1A0 & ADC2A1– ADC1B0 = ADC1B0 & ADC2B1– ADC2A0 = ADC1A1 & ADC2A0– ADC2B0 = ADC1B1 & ADC2B0

• Redundant channels do not waste pins

• ADC safety verification– Critical signals converted by (2) ADCs

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– DAC outputs exercise ADCs– (6) independent 10-bit DACs are

connected to (6) ADC inputs:• ADC1B2• ADC1B4• ADC1B5

• ADC2B2• ADC2B4• ADC2B5

Comparator Outputs • COMPnOUT 1-3 can trip PWM

• All (6) COMPnOUT to GPIO pins

• CACOUT to GPIO pin

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Concerto™ DetailsInter-Processors Communications (IPC) Subsystem

�IPC Device Features�Shared SARAM�Message SARAM

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�Message SARAM�IPC Message Registers�IPC Interrupts and Flags

�IPC Software Options�Basic (no drivers)�IPC-Lite Drivers�Main IPC Drivers

IPC Device Features

�Shared SARAM

�Message SARAM

�IPC Message Registers

�IPC Interrupts and Flags

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�IPC Interrupts and Flags

Shared SARAM

OwnershipMaster Subsystem Control Subsystem

M3 CPU uDMA C28x DMA

Up to 8 blocks (S0 – S7), 8 kbytes each

Normally used by the applicationCan also be used to pass messages

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OwnershipM3 CPU uDMA C28x DMA

Master Subsystem* R/W/Exe R/W R R

Control Subsystem R R R/W/Exe R/W

* default

IPC Message SARAMs

2 blocks, 2 kbytes eachUsed to pass messages or data between the CPU’sAlways enabled. Configuration is fixed.

Message RAMMaster Subsystem Control Subsystem

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Message RAMMaster Subsystem Control Subsystem

M3 CPU uDMA C28x DMA

Master to Control (“MtoC”) R/W R R R

Control to Master (“CtoM”) R R R/W R

IPC Message Registers• Provides very simple and flexible messaging

• Dedicated registers mapped to both CPUs

• IPCCOMMAND• IPCADDR• IPCDATAWRITE• IPCDATAREAD

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• The definition (what the register content means) is up to the application software.

• TI’s IPC-Lite drivers use the IPC message registers

C28x Memory Map

IPC Interrupts and Flags

C28xC28 to M3 IPC

C28 to M3 IPC

R/W

M3 Memory Map

CTOMIPCSTSCTOMIPCFLG

M3

CTOMIPCSET

NVIC

Set Q

Clear

CTOMIPCACKR/W

CTOMIPCCLR

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MTOCIPCCLR

MTOCIPCSET

M3 to C28 IPC

MTOCIPCFLGMTOCIPCSTS

M3 to C28 IPC

Clear

Q Set

PIEMTOCIPCACK

IPC via Serial CommunicationSerial port loopback enables IPC through peripherals

UART4 to SCIASSI3 to SPIA

The master subsystem can enable or disable this capabilityDoes not require an external connection between the peripherals.

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IPC Software Solutions

� Basic (no drivers)

� IPC-Lite Drivers

� Main IPC Drivers

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Concerto IPC Software Solutions

Basic Option: No Software drivers needed– Uses IPC registers only (simple message passing )

IPC-Lite Software API Driver– Uses IPC registers only (no memory used)– Limited to 1 IPC interrupt at a time– Limited to 1 command/message at a time

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– Limited to 1 command/message at a time– M3 can use IPC-Lite to communicate with C28 boot ROM.

Main IPC Software API Driver– Uses circular buffers message RAMs– Can queue up to 4 messages prior to processing (configurable)– Can use multiple IPC ISRs at a time– Requires additional setup in application code prior to use.

Concerto IPC Software SolutionsThe Concerto IPC is easy to use!Basic Option: NO Software Drivers Needed!• Use the message RAM’s and shared SARAM’s (Sx blocks) to pass

data between processors at a known address.

• Use the IPC flag registers to tell the other processor that data is ready.

C28 Application

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MtoC MSG RAM

CtoM MSG RAM

Sx Shared SARAM’s

M3 Application C28 Application

Message1: Write a message to MtoC MSG RAM.

MTOCIPCFLG MTOCIPCSTS

2: Write 1 to MTOCIPCSET bit.

3: sees MTOCIPCSTS bit is set.

4: read message

5: write 1 to MTOCIPCACK bit.

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IPC-Lite Software Drivers• Requires no additional setup beyond adding appropri ate files to

M3 and C28 projects:

M3

ipc_lite.c Contains all M3 IPC-Lite API functions.

ipc_util.c Contains M3 IPC utility functions used by both IPC driver options, or for standalone usage. Also includes support to execute C28 peripheral bootloader.

ipc.h Header file used by both IPC-Lite and main IPC drivers. Function prototypes are

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main IPC drivers. Function prototypes are also included here.

C28

F28M35x_Ipc_Lite.c Contains all M3 IPC-Lite API functions.

F28M35x_Ipc_Util.c Contains M3 IPC utility functions used by both IPC driver options, or for standalone usage.

F28M35x_Ipc.h Header file used by both IPC-Lite and main IPC drivers. Function prototypes are also included here.

IPC Software Drivers• The following files must be added to both the M3 an d C28

projects in order to use the main IPC drivers:

M3

ipc.c Contains all main M3 IPC API functions.

ipc_util.c Contains M3 IPC utility functions used by both IPC driver options, or for standalone usage.

ipc.h Header file used by both IPC-Lite and main IPC drivers. Function prototypes are also included here.

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also included here.

C28

F28M35x_Ipc.c Contains all main M3 IPC API functions.

F28M35x_Ipc_Util.c Contains M3 IPC utility functions used by both IPC driver options, or for standalone usage.

F28M35x_Ipc.h Header file used by both IPC-Lite and main IPC drivers. Function prototypes are also included here.

IPC Drivers: Details

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Concerto™ Details

Code Composer Studio

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Code Composer Studio

Code Composer Studio Support

• Concerto Class devices are supported in version 4.2.xx of CCS and later– Concerto Class devices are NOT supported in any earlier version (i.e. 3.x)

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Compiler Support

• Concerto devices have two different cores– Therefore, a different compiler must be used for each core

• TMS470 Code Generation Tools – for Cortex-M3 Master Subsystem– Version 4.6.4 or later

• C2000 Code Generation Tools – for C28x Control Subsystem– Version 5.2.10 or later

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Emulator Support

• Concerto class devices are support by

– XDS100v2

– XDS510

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– XDS560

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Dual Core Debug Setup

• Create a new target configuration– File, New, Target Configuration File

• Name it f28m35x.ccxml• Select your emulator• Select F28M35x in the list• Save configuration

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• Save configuration

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Launching Dual Core Debug

• Open Target Configuration View– View, Target Configurations

• Launch appropriate target configuration– Right click on f28m35x.ccxml

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– Right click on f28m35x.ccxml– Launch Selected Configuration

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• After launching the target config

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– Connection to emulator is established– Connection to cores in still needed

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• Connect to each core

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– Right click on each core– Connect Target

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• After connecting to each core

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• Debug window controls which core is “selected

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• To load a program for debug– Select desired core– Target, Load Program

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– Repeat process for second core

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• …Something isn’t right– Master Subsystem runs to main and stops– Control Subsystem gets stuck in c_int00() ?!?!?

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– What’s going on here?

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• Remember– Master Subsystem has ultimate authority– At boot C28 Core is held in reset by M3RSnIN bit @

0x400FB8C0• Master must release C28 core from reset before it can run to

main

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main• OR an 0x10000 into 0x4000FB8C0 (EALLOW Protected!)

• Reload C28 program and it will run to main ☺

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Dual Core Debug

• Code Composer includes dual core debug capabilities (implemented in software)

– Supports:

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• Start• Stop• Restart• Step Operations

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Dual Core Debug

• Concerto class devices make debugging complex multi-core algorithms easy with cross triggering– Cross-Triggering – Hardware synchronized halt across

both cores

– Enabled in breakpoint window

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– Enabled in breakpoint window• Add “Cross Trigger” to each core

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new concerto™ f28m35x microcontrollers - Компэл · 2019. 8. 2. · concerto ™ college...

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