new ese370: circuit-level modeling, design, and optimization for...
TRANSCRIPT
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ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Lec 12: September 30, 2019 Scaling
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Today
! VLSI Scaling Trends/Disciplines ! Effects ! Alternatives (cheating)
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Scaling Technology
! Premise: features scale “uniformly” " everything gets better in a predictable manner
! Parameters: # λ (lambda) -- Mead and Conway (L=2λ) # F -- Half pitch – ITRS (F=2λ=L) # S – scale factor – Rabaey
# F’=F/S # S>1
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Half Pitch (= Pitch/2) Definition
(Typical MPU/ASIC)
(Typical DRAM)
Poly Pitch
Metal Pitch
Source: 2001 ITRS - Exec. Summary, ORTC Figure, Andrew Kahng Penn ESE 370 Fall 2019 - Khanna 4
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Microprocessor Trans Count 1971-2015
5 Kenneth R. Laker, University of Pennsylvania, updated 20Jan15
Curve shows transistor count doubling every
two years Pentium
4004 8006
8080 Mot 6800
8086
Mot 68000 80286
80386
80486
MOS 6502 Zilog Z80
80186
AMD K5 Pentium II
Pentium III AMD K7
Pentium 4 AMD K8
AMD K10 AMD 6-Core Opteron 2400 4-Core i7
2-Core Itanium 2 6-Core i7 6-Core i7 16-Core SPARC T3
10-Core Xenon IBM 4-Core z196 IBM 8-Core POWER7
4-Core Itanium Tukwilla
2015: Oracle SPARC M7, 20 nm CMOS, 32-Core, 10B 3-D FinFET transistors.
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Intel Cost Scaling
6
http://www.anandtech.com/show/8367/intels-14nm-technology-in-detail
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Moore’s Law Impact on Intel uComputers
7 2010 YEAR
Serial data links operating at 10 Gbits/sec.
Increased reuse of logic IP, i.e. designs and cores.
2BT µP (Intel Itanium Tukwila) 4-Core chip (65 nm) introduced Q1 2010.
3BT mP (Intel Itanium Poulson) 8-Core chip (32 nm) to be introduced 2012.
Introduces 22 nm Tri-gate Transistor Tech.
Complexity - # transistors Double every Two Years 0.022um
2011
0.032um 2009
Min Feature
Size
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More Moore $ Scaling
! Geometrical Scaling " continued shrinking of horizontal and vertical physical
feature sizes
! Design Equivalent Scaling " design technologies that enable high performance, low
power, high reliability, low cost, and high design productivity even if neither geometrical nor equivalent scaling can be used
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22nm 3D FinFET Transistor
9
Tri-Gate transistors with multiple fins connected together
increases total drive strength for higher performance
http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf
High-k gate
dielectric
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ITRS Roadmap
! International Technology Roadmap for Semiconductors " Try to predict where industry going
! ITRS 2.0 started in 2015 with new focus " System Integration, Heterogeneous Integration,
Heterogeneous Components, Outside System Connectiviy, More Moore, Beyond CMOS and Factory Integartion.
! http://www.itrs2.net/
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More-than-Moore
11
“More-than-Moore”, International Road Map (IRC) White Paper, 2011.
International Technology Road Map for Semiconductors
Scal
ing
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Preclass 1
! Scaling from 32nm $ 22nm? " Scaling minimum gate length " And pitch distance
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MOS Transistor Scaling - (1974 to present)
1/S=0.7 per technology node
[0.5x per 2 nodes] Pitch Gate
Source: 2001 ITRS - Exec. Summary, ORTC Figure, Andrew Kahng Penn ESE 370 Fall 2019 - Khanna 13
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250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
0.7x 0.7x
N N+1 N+2
Log
Hal
f-P
itch
Linear Time
1994 NTRS - .7x/3yrs
Actual - .7x/2yrs
14 Penn ESE 370 Fall 2019 - Khanna Source: 2001 ITRS - Exec. Summary, ORTC
Figure, Andrew Kahng
Node Cycle Time:
Scaling Calculator
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Scaling
! Channel Length (L) ! Channel Width (W) ! Oxide Thickness (tox) ! Doping (Na) ! Voltage (VDD,Vt,)
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Full Scaling (Ideal Scaling)
! Channel Length (L) 1/S ! Channel Width (W) 1/S ! Oxide Thickness (tox) 1/S ! Doping (Na) S ! Voltage (VDD,Vt,) 1/S
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Effects on Physical Properties and Specs?
! Area ! Capacitance (Cox, Cgate) ! Resistance ! Current (Id) ! Gate Delay (τgd) ! Wire Delay (τwire) ! Power
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Area
! λ’ % λ/S ! Area impact? ! Α = L × W!
! 32nm % 22nm ! 50% area ! 2 × transistor capacity
for same area
L
W 1/S=0.7
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Area
! λ’ % λ/S ! Area impact? ! Α = L × W! Α’ % Α/S2
! 32nm % 22nm ! 50% area ! 2 × transistor capacity
for same area
L
W 1/S=0.7
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Capacitance
! Capacitance per unit area scaling?
" Cox= εSiO2/tox
" t’ox% tox/S
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Capacitance
! Capacitance per unit area scaling?
" Cox= εSiO2/tox
" t’ox% tox/S" C’ox % Cox×S
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Capacitance
! Gate Capacitance scaling?
# Cgate= A×Cox
# Α’ % Α/S2
# C’ox % Cox×S
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Capacitance
! Gate Capacitance scaling?
# Cgate= A×Cox
# Α’ % Α/S2
# C’ox % Cox×S# C’gate % Cgate/S
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Wire Resistance
! Resistance scaling? ! R=ρL/(W*t)
" L, t remain similar (not scaled)
! W$ W/S
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Wire Resistance
! Resistance scaling? ! R=ρL/(W*t)
" L, t remain similar (not scaled)
! W$ W/S ! R $ R×S
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Current
! Which Voltages matters here? (Vgs,Vds,Vth…) ! Transistor charging looks like
voltage-controlled current source ! Saturation Current scaling?
Id=(µCOX/2)(W/L)(Vgs-VTH)2
Vgs=V’$ V/S
V’TH$ VTH/SW’$ W/SL’$ L/SC’ox $ Cox×S
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Current
! Which Voltages matters here? (Vgs,Vds,Vth…) ! Transistor charging looks like
voltage-controlled current source ! Saturation Current scaling?
Id=(µCOX/2)(W/L)(Vgs-VTH)2
Vgs=V’$ V/S
V’TH$ VTH/SW’$ W/SL’$ L/SC’ox $ Cox×S I’d=(µCOXS/2)((W/S)/(L/S))(Vgs/S-VTH/S)2
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Current
! Which Voltages matters here? (Vgs,Vds,Vth…) ! Transistor charging looks like
voltage-controlled current source ! Saturation Current scaling?
Id=(µCOX/2)(W/L)(Vgs-VTH)2
Vgs=V’$ V/S
V’TH$ VTH/SW’$ W/SL’$ L/SC’ox $ Cox×S I’d$Id/S
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Current
! Velocity Saturation Current scaling?
Vgs=V’$ V/S
V’TH$ VTH/S L’$ L/S W’$ W/SC’ox $ CoxS
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Current
! Velocity Saturation Current scaling?
Vgs=V’$ V/S
V’TH$ VTH/S L’$ L/S W’$ W/SC’ox $ CoxS V’DSAT $ VDSAT/S I’d$ Id/S Penn ESE 370 Fall 2019 - Khanna 30
€
VDSAT ≈Lνsatµn
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IDS ≈νsatCOXW VGS −VTH −VDSAT
2%
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Gate Delay
# Gate Delay scaling? # τgd=Q/I=(CV)/I # V’$ V/S
# I’d $ Id/S# Cg’ $ Cg/S
Note: Ids modeled as current source; V is changing with scale
factor
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Gate Delay
# Gate Delay scaling? # τgd=Q/I=(CV)/I # V’$ V/S
# I’d $ Id/S# Cg’ $ Cg/S
# τ’gd $ τgd/S
Note: Ids modeled as current source; V is changing with scale
factor
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Wire Delay
# Wire delay scaling? # τwire=R×C
# R’ $ R×S # C’ $ C/S
! Again assuming (logical) wire lengths remain constant
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Wire Delay
# Wire delay scaling? # τwire=R×C
# R’ $ R×S # C’ $ C/S # τ’wire $ τwire
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! Again assuming (logical) wire lengths remain constant
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Power Dissipation (Dynamic)
! Capacitive (Dis)charging scaling?
! P=(1/2)CV2f
! V’$ V/S
! C’ $ C/S
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Power Dissipation (Dynamic)
! Capacitive (Dis)charging scaling?
! P=(1/2)CV2f
! V’$ V/S
! C’ $ C/S
! P’$ P/S3
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Power Dissipation (Dynamic)
! Capacitive (Dis)charging scaling?
! P=(1/2)CV2f
! V’$ V/S
! C’ $ C/S
! P’$ P/S3
! Increase Frequency?
! τgd $ τgd/S
! So: f $ f×S
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Power Dissipation (Dynamic)
! Capacitive (Dis)charging scaling?
! P=(1/2)CV2f
! V’$ V/S
! C’ $ C/S
! P’$ P/S3
! Increase Frequency?
! τgd $ τgd/S
! So: f $ f×S
! P $ P/S2
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Effects?
! Area 1/S2 ! Capacitance (Cox, Cg) S, 1/S ! Resistance S ! Threshold (Vth) 1/S ! Current (Id) 1/S ! Gate Delay (τgd) 1/S ! Wire Delay (τwire) 1 ! Power 1/S3, 1/S2
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1/S=0.7
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Power Density
! P’ % P/S2 (increased frequency)
! P’ % P/S3 (same frequency)! A’ % A/S2
! Power Density: P/A two cases?
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Power Density
! P’ % P/S2 (increased frequency)
! P’ % P/S3 (same frequency)! A’ % A/S2
! Power Density: P/A two cases? " P/A % P/A increase freq. " P/A % (P/A)/S same freq.
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Cheating…
! Don’t like some of the implications ! High resistance wires ! Higher gate capacitance ! Atomic-scale dimensions
! …. Quantum tunneling
! Need for more wiring ! Not scale speed fast enough
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Improving Resistance
! R=ρL/(W×t) ! W’$ W/S
" L, t similar
! R’ $ R×S
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Improving Resistance
! R=ρL/(W×t) ! W’$ W/S
" L, t similar
! R’ $ R×S
What might we do? Didn’t scale t quite as fast $ now taller than wide.
Decrease ρ (copper) – introduced 1997 http://www.ibm.com/ibm100/us/en/icons/copperchip/
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Capacitance and Leakage
! Capacitance per unit area " Cox= εSiO2
/tox
" t’ox% tox/S" C’ox % Cox×S
What’s wrong with tox = 1.2nm?
source: Borkar/Micro 2004
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Capacitance and Leakage
! Capacitance per unit area " Cox= εSiO2
/tox
" t’ox% tox/S" C’ox % Cox×S
What might we do? Reduce dielectric constant, ε, and increase
thickness to mimic tox scaling. Penn ESE 370 Fall 2019 - Khanna 46
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High-K dielectric Survey
Wong/IBM J. of R&D, V46N2/3P133—168, 2002 Penn ESE 370 Fall 2019 - Khanna 47
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Wire Layers = More Wiring
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Gate Delay
# τgd=Q/I=(CV)/I # V’$ V/S
# I’d $ Id/S# Cg’ $ Cg/S
# τ’gd $ τgd/S
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How might we accelerate?
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Gate Delay
# τgd=Q/I=(CV)/I # V’$ V
# I’d=(µCOXS/2)((W/S)/(L/S))(Vgs-VTH)2
# I’d $ Id×S
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How might we accelerate?
Don’t scale V!
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Gate Delay
# τgd=Q/I=(CV)/I # V’$ V
# I’d=(µCOXS/2)((W/S)/(L/S))(Vgs-VTH)2
# I’d $ Id×S# Cg’ $ Cg/S
# τ’gd $ τgd/S2
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How might we accelerate?
Don’t scale V!
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But… Power Dissipation (Dynamic)
! Capacitive (Dis)charging
# P=(1/2)CV2f # V’$ V# C’ $ C/S # P’$ P/S
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But… Power Dissipation (Dynamic)
! Capacitive (Dis)charging
# P=(1/2)CV2f # V’$ V# C’ $ C/S # P’$ P/S
! Increase Frequency? # f’ $ f×S2 # P’ $ P×S
If don’t scale V, power dissipation doesn’t scale down!
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…And Power Density
! P’$ P×S (increase frequency)! Α’ $ Α/S2
! What happens to power density?
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…And Power Density
! P’$ P×S (increase frequency)! Α’ $ Α/S2
! What happens to power density?
! P/A $ S3×P
! Power Density Increases!
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Historical Voltage Scaling
! Frequency impact? ! Power Density impact?
http://software.intel.com/en-us/articles/gigascale-integration-challenges-and-opportunities/
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Scale V separately with Factor U
! τgd=Q/I=(CV)/I ! V’$V/U
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Scale V separately with Factor U
! τgd=Q/I=(CV)/I ! V’$V/U
! I’d=(µCOXS/2)((W/S)/(L/S)(Vgs/U-VTH/U)2
! I’d $ S/U2×Id
! C’ $ C/S
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Scale V separately with Factor U
! τgd=Q/I=(CV)/I ! V’$V/U
! I’d=(µCOXS/2)((W/S)/(L/S)(Vgs/U-VTH/U)2
! I’d $ S/U2×Id
! C’ $ C/S
! τ’gd $ ((1/(SU))/(S/U2))×τgd
! τ’gd $ (U/S2)×τgd
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Scale V separately with Factor U
! τgd=Q/I=(CV)/I ! V’$V/U
! I’d=(µCOXS/2)((W/S)/(L/S)(Vgs/U-VTH/U)2
! I’d $ S/U2×Id
! C’ $ C/S
! τ’gd $ ((1/(SU))/(S/U2))×τgd
! τ’gd $ (U/S2)×τgd
! f’ $ (S2/U)×f
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Scale V separately with Factor U
! τgd=Q/I=(CV)/I ! V’$V/U
! I’d=(µCOXS/2)((W/S)/(L/S)(Vgs/U-VTH/U)2
! I’d $ S/U2×Id
! C’ $ C/S
! τ’gd $ ((1/(SU))/(S/U2))×τgd
! τ’gd $ (U/S2)×τgd
! f’ $ (S2/U)×f
Penn ESE 370 Fall 2019 - Khanna 61
Ideal scale factors: S=100 U=100 τ=1/100 fideal=100
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Scale V separately with Factor U
! τgd=Q/I=(CV)/I ! V’$V/U
! I’d=(µCOXS/2)((W/S)/(L/S)(Vgs/U-VTH/U)2
! I’d $ S/U2×Id
! C’ $ C/S
! τ’gd $ ((1/(SU))/(S/U2))×τgd
! τ’gd $ (U/S2)×τgd
! f’ $ (S2/U)×f
Penn ESE 370 Fall 2019 - Khanna 62
Ideal scale factors: S=100 U=100 τ=1/100 fideal=100
Cheating factors: S=100 U=10
How much faster are gates?
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Scale V separately with Factor U
! τgd=Q/I=(CV)/I ! V’$V/U
! I’d=(µCOXS/2)((W/S)/(L/S)(Vgs/U-VTH/U)2
! I’d $ S/U2×Id
! C’ $ C/S
! τ’gd $ ((1/(SU))/(S/U2))×τgd
! τ’gd $ (U/S2)×τgd
! f’ $ (S2/U)×f
Penn ESE 370 Fall 2019 - Khanna 63
Ideal scale factors: S=100 U=100 τ=1/100 fideal=100
Cheating factors: S=100 U=10 τ=1/1000 fcheat=1000
How much faster are gates?
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Scale V separately with Factor U
! τgd=Q/I=(CV)/I ! V’$V/U
! I’d=(µCOXS/2)((W/S)/(L/S)(Vgs/U-VTH/U)2
! I’d $ S/U2×Id
! C’ $ C/S
! τ’gd $ ((1/(SU))/(S/U2))×τgd
! τ’gd $ (U/S2)×τgd
! f’ $ (S2/U)×f
Penn ESE 370 Fall 2019 - Khanna 64
Ideal scale factors: S=100 U=100 τ=1/100 fideal=100
Cheating factors: S=100 U=10 τ=1/1000 fcheat=1000
fcheat/fideal=10
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Power Density Impact
! P = (1/2)CV2 f ! P $ (1/S) (1/U2) (S2/U) = S/U3
! P/A $ (S/U3) / (1/S2) = S3/U3
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Power Density Impact
! P = (1/2)CV2 f ! P $ (1/S) (1/U2) (S2/U) = S/U3
! P/A $ (S/U3) / (1/S2) = S3/U3
! U=10 S=100 ! P/A $ 1000 (P/A)
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Power Density Impact
! P = (1/2)CV2 f ! P $ (1/S) (1/U2) (S2/U) = S/U3
! P/A $ (S/U3) / (1/S2) = S3/U3
! U=10 S=100 ! P/A $ 1000 (P/A) ! Compare with ideal scaling: ! P/A $ S3×P (ideal scaling) ! P/A $ 1,000,000 (P/A) (ideal scaling)
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Scaling Methods
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uProc Clock Frequency
The Future of Computing Performance: Game Over or Next Level? National Academy Press, 2011
http://www.nap.edu/catalog.php?record_id=12980
MHz
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uP Power Density
Watts
The Future of Computing Performance: Game Over or Next Level? National Academy Press, 2011
http://www.nap.edu/catalog.php?record_id=12980 Penn ESE 370 Fall 2019 - Khanna 70
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42 Years of uP Trend Data
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Conventional Scaling
! Ends in your lifetime ! Perhaps already:
" "Basically, this is the end of scaling.” " May 2005, Bernard Meyerson, V.P. and chief technologist for
IBM's systems and technology group
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ITRS 2.0 Report 2015
! “After 2021, the report forecasts, it will no longer be economically desirable for companies to continue traditional transistor miniaturization in microprocessors.”
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BUT…
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Source:https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/09/mark-bohr-on-continuing-moores-law.pdf
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BUT…
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Source:https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/09/mark-bohr-on-continuing-moores-law.pdf
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Big Ideas
! Moderately predictable VLSI Scaling " unprecedented capacities/capability growth for
engineered systems " …but not for much longer
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Admin
! HW5 " More transistor practice " Prepares you for design project 1 " Due Friday
! Midterm " Back on Wednesday
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