next big thing : ddr4 3ds - jedec.org · – 3ds rdimm 1dpc performance is similar to ddp lrdimm...
TRANSCRIPT
Next Big Thing : Next Big Thing : Next Big Thing : Next Big Thing : DDR4 3DSDDR4 3DS
Server Forum 2014 Copyright © 2014 [JS Choi Samsung]
AgendaAgenda
• Memory Requirement
• How to Address
• What’s 3DS• What’s 3DS
• It’s IN PRODUCTION
DRAM Market & ApplicationDRAM Market & Application
• 47% of DRAM for Server and PC application
ServerServer
(15%)(15%)
Mainframe
Supercomputer
Server
Workstation
PCPC(32%)(32%)
Desktop
MobileMobile
(25%)(25%)Tablet
Smart Phone
Cellular Phone
7%7%
Industrial
Military
Aerospace
Notebook
Mini laptop
ConsumerConsumer
& & GfxGfx
(21%)(21%)
TV/ LCD/ Printer
Set-top box/ D.Camera
Navigation/ Black Box
Gfx card / Video Game
Home Appliance
Cellular Phone
EDP (Electronic Data Processing)
Source : Gartner(‘14.1Q)
• Memory RAS and Low TCO are required for server
Server Application TrendServer Application Trend
Server Virtualization Moving to Cloud Big Data
Low TCO Enhanced RAS High Performance
• Operating voltage• Stand-by power• Core & I/O power
• Better S/I• Reinforced resiliency
• High bandwidth• Better efficiency
Source : Gartner(‘14.1Q)
High Capacity
High Performance/Watt
High Reliability
But Low Cost
4th Generation of DDR SDRAM4th Generation of DDR SDRAM
• Successor of DDR3 from 2014 supporting all Computing system
GDDR GDDR2 GDDR3 GDDR4 GDDR5
’02 ’14’07’05 ….
C:\>
PC66 -133 DDR DDR2 DDR3 DDR4
MDDR MDDR2 LPDDR3 LPDDR4
TSV technology for 3DSTSV technology for 3DS
• Enables DRAM stacking with better electrical characteristics
TSVVIA
TSV SolutionsTSV Solutions
Master Chip
<4H TSV Package>
Conventional Stack SolutionsConventional Stack Solutions
Wire-BondRDL*
<QDP Wire-bond Package>
Slave Chip
MemoryController DRAM
(Master)
IntegratedBuffer
Less I/Opower
<3DS TSV RDIMM>
MemoryController
DRAM
DataBuffer
<QDP LRDIMM>
Number of loading limits high speed operations
Only master chip communicates with controller regardless of number of stacking
*RDL : Re-distribution Layer
3DS DDR4 Architecture3DS DDR4 Architecture
• Mater, sub-control of CA/CTL/Data
3DS DDR4 Architecture3DS DDR4 Architecture
• Micrograph of 3DS DDR4 SDRAM– (a) Chip Micrograph– (b) Vertical section – (c) Shmoo
Check List for 3DS (1) Check List for 3DS (1)
• Encoded Address : 1CS# + 2Chip ID
Increase Max Density with Limited CS#
Check List for 3DS (2)Check List for 3DS (2)
• Additional Latency for De-Skew PVT
Better Matching with RDIMM rather than LRDIMM
Check List for 3DS (3) Check List for 3DS (3)
• MR Setting only for Master
• All Logical Ranks enter Self Refresh / Power Down together
Simpler Initialization / Power control
Check List for 3DS (4) Check List for 3DS (4)
• Staggering Refresh only within Logical Ranks
No Difference in Package Rank Interleaving
Tips to maximize 3DS performanceTips to maximize 3DS performance
• Make Sure your controller support All-Ranks Interleaving
– Can Maximize Efficiency if you control PKG Ranks and Logical Ranks in the different way
• Use 3DS only at Same Channel
• Reduce Staggering Refresh Interval
1 0.99 1.03
Power Efficiency of 3DS SolutionPower Efficiency of 3DS Solution
• 3DS solution shows similar performance to buffered solutions
• Significant less power by removing additional ICs
~24% ~28%
Performance & Latency Power Consumption
1 1 0.96
LR TSV TSV_LR
*Performance: SPECjbb benchmark, Latency: ATE, Power: Samsung memory stress PGM @ system
1
0.81 1.04
DDP LRDIMM TSV RDIMM TSV LRDIMMDDP 32GB LRDIMM
4H 3DS64GB RDIMM
4H 3DS64GB LRDIMM
DDP 32GB LRDIMM
4H 3DS64GB RDIMM
4H 3DS64GB LRDIMM
Performance Latency
4H 3DS DRAM consumes same as conventional 2stack3DS RDIMM performs the same as buffered solutions
Performance Performance BenchmarkBenchmark
• 3DS RDIMM shows better overall performance
– 3DS RDIMM shows best performance with 2DPC (less idle time from large number of ranks)
– 3DS RDIMM 1DPC performance is similar to DDP LRDIMM (larger idle time from more
refresh)
52000
54000
56000
58000
Stream
Stream
Higher the
better(B/W)
45.0
50.0
55.0
60.0
65.0
70.0
Lmbench
Lmbench
Lower the
better(latency)
46000
48000
50000
DDP LRDIMM 3DS RDIMM DDP LRDIMM 3DS RDIMM
1DPC 2DPC
170
175
180
185
190
195
200
205
210
DDP LRDIMM 3DS RDIMM DDP LRDIMM 3DS RDIMM
1DPC 2DPC
SPECcpu
SPECcpu
32000
32200
32400
32600
32800
33000
33200
33400
DDP LRDIMM 3DS RDIMM DDP LRDIMM 3DS RDIMM
1DPC 2DPC
SPECjbb max-jOPS
SPECjbb max-jOPS
Higher the better(Performance)
Higher the better(Performance)
30.0
35.0
40.0
45.0
DDP LRDIMM 3DS RDIMM DDP LRDIMM 3DS RDIMM
1DPC 2DPC
Unveiled 1st TSV product, 64GB RDIMMUnveiled 1st TSV product, 64GB RDIMM
• 64GB RDIMM with TSV is IN PRODUCTION• 64GB RDIMM with TSV is IN PRODUCTION
Infrastructure Readiness for HBMInfrastructure Readiness for HBM
300mm wafer process line is ready for “Mass Production”
Fab process qualification is completed with “State of the art” facilities
FAB Post-FAB Assembly
Bump Carrier Bond Back-side Pad Debond & SawTSV Stacking
Chip on PCBChip on wafer
Samsung Memory for All Computing DeviceSamsung Memory for All Computing Device