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Flash Forward: Flash Memory Storage SolutionsFlash Forward: Flash Memory Storage Solutions
Perry KellerProgram Manager
Digital Applications and StandardsAgilent Technologies
Next Generation Design and Test for Next Generation
Memory
Flash Forward: Flash Memory Storage Solutions
Memory’s Jump to “High Speed”
Power and Cost Budget
Spe
ed *
Inte
rcon
nect
Com
plex
ity
Graphics
Computer
Embedded / Mobile / Flash
Convergence?Signaling
Signal Integrity Threshold
“Low Speed”
“High Speed”
Flash Forward: Flash Memory Storage Solutions
What is High Speed?Tx RxPCB Trace (Tpd)
10 200 30
0.2
0.4
0.6
0.8
0.0
1.0
time, nsec
filt_
out
10 200 30
0.5
1.0
1.5
0.0
2.0
time, nsec
tline
_out
Tr > 5 x Tpd
- Complex behavior, harder design• Ringing, crosstalk, reflections must
be carefully managed• Termination is critical• Everything becomes 1st order
Tr < 5 x Tpd
+ Simple behavior, simple design+ Easy to model and understand
• Capacitance is king- Only low data rates possible- Sensitive to noise
Memory speed AND interconnect complexity matter
Flash Forward: Flash Memory Storage Solutions
Drivers, Receivers and Spec Must Adapt
Tx RxMemory Channel
Tx Changes
• On die termination• More differential signaling• Loopback modes• CDR based recovery• Real time error feedback and
command cancel on error• Equalization
Rx Changes• Z0 calibration• More differential signaling• Training/Retraining sequences• Fine grained timing adjustment• Retry on error
• Pre/De-emphasis
• Source synchronous / Forwarded clock• Slew Rate derating• Ts/Th -> tPW/skew -> Jitter tolerance• N-Cycle TJ > Rj/Dj @ BER
Specification Changes
Flash Forward: Flash Memory Storage Solutions
Some Old Challenges Still Remain
Memory Controller Rank 0
Address and Command
CK
DQS / WCK
DQSn…
CS_D[0:?]#
CS_A[0:?]#CS_B[0:?]#CS_C[0:?]#
EDC Feedback
~30-300
~20-500
100’s of signals to measureSome points very hard to probe
Flash Forward: Flash Memory Storage Solutions
Order in a Changing World• Access to signals at Memory and controller
• Signal integrity across entire bus
• Large number of test cases and setups
• Complex causes and effects
• Design for Signal Integrity to minimize problems
• Accelerate validation, characterization and debug:• Engineer your probing strategy
• Put the right hooks into your design
• Discard old assumptions
• Expect more from your instrumentation
Key Requirements
An Ounce of Prevention….
Flash Forward: Flash Memory Storage Solutions
Designing for Signal Integrity
Package SimulationPhysical Design
Verification
Interconnect Modeling
Design for interoperability
Driver/Receiver Design and Optimization
Channel modeling / simulation
• Adopt tools and techniques from RF/Microwave world• What was 2nd or 3rd order are now 1st order effects• Everything becomes part of the schematic• Tuning and optimization are key
Flash Forward: Flash Memory Storage Solutions
Design Optimization Saves Time / Money• Reduces size of test matrix, allows greater mfg/vendor variance• Essential when using low cost or “no frills” design structures• Example: DIMM resistor value, mother board transmission line width, spacing and
length are defined as optimization parameters
Before After
Flash Forward: Flash Memory Storage Solutions
Probing Design at the System Level
Engineer probing as part of developing your design
BGA Device Interposers
Soldered Probes
Socketed Probes
Midbus Probing
Standard Connector Interposers
Scope/LA Adapters
Flash Forward: Flash Memory Storage Solutions
Memory Controller Measurement DFx
Protocol Engine
Clk Delay
Addr/Cmd/Ctl Delay
DQ Delay
DQS Delay
PHY
Rank 0
Cha
nnel
Memory Controller + Pkg
Test Control
• Timing/voltage sweep• Pattern gen/check• Repetitive Training• Single line control• Instrumentation interface for automation
CS_ABCD
Flash Forward: Flash Memory Storage Solutions
Getting More From Your Instrumentation
• Logic Analyzers– Still the tool for protocol and data flow– What about AC timing and signal integrity across the entire
bus?• Oscilloscopes
– Still the definitive tool for ultimate measurement accuracy– How do you get from where you can probe to where you
must measure, like the memory controller or die pad?• Improve coverage and efficiency with automation linked to
your design test controller
Flash Forward: Flash Memory Storage Solutions
Most Memory AC Parameters = Delay/Skew
• Time position of one edge relative to another
Flash Forward: Flash Memory Storage Solutions
Traditional Timing AnalysistIStIH
1)Place markers
2)Measure Δt
Simple approach
Works as long as edge rate << of timing sample rate and edge position is stable across measurements.
DOES NOT WORK at higher data speeds due to ISI and instrument jitter
Flash Forward: Flash Memory Storage Solutions
Analyzer Sample Point
Input
Output
V
V
VThreshold
Sample Jitter
Analyzer Jitter and Measurement ErrorV
Internal Analyzer
Clock
Input
Threshold
Comparator
Output (0 or 1)V
Latch VOutput
• Limited front end BW converts noise to timing jitter and creates ISI
• Noise and internal clock jitter show up on “measured” signal
• Error doubles when comparing two signals
• Any oversampling above 1/(pk-pk jitter) adds NO information
• Typical pk-pk jitter of 90-150ps -> 8Ghz is maximum useful rate
• Error becoming larger than the timing parameters to be measured!
BW = 3-4 Ghz
Flash Forward: Flash Memory Storage Solutions
Data+
Vthresh Data-
+ _
Clk+
Vthresh Clk-
+ _
Delay @ 5 ps/step
Data Path
Clock Path
Next Gen LA Timing and Eye Capture
Signal
Clock
• Logic analyzer sequencer establishes trigger point for measurement• Sweep across time@threshold -> data valid window and edge/edge timing• Sweep across time and threshold -> eye diagram / waveforms• Synchronous sampling eliminates common mode jitter and SSC• Zero dead time capture of up to 1E8 events captures low BER events• Edge time set at peak of jitter histogram eliminates LA front end random jitter error• Protocol/pattern sequence trigger isolates ISI induced jitter and complex events
5ps resolution
5mV resolution
Counter
Logic Analyzer
Sequencer
Edge to edge
Flash Forward: Flash Memory Storage Solutions
Case Study – DQ Signal Quality
Clean open eyes for most Data Read lines.
Closed or small DQ EyesLA Threshold?Probing issue?Design issue?
(Small eyes OK for LA as long as some window exists)
Signal activity vs. time snapshots entire bus
Flash Forward: Flash Memory Storage Solutions
Time& Voltage Sweep Opens Eye Diagram
Data_61 eye closed
Issue isn’t threshold setting.
DQ62 eye open with limited margin also
DQ60 eye open but margin is limited
Flash Forward: Flash Memory Storage Solutions
Burst Waveforms Reveal Detail Behavior
DQ62 eye has same problem but mostly on 0’s. Eye is not truly open!
DQ61 eye closure due to limited swing on first few cycles of burst • True for both 1’s and 0’s
ODT Timing? Crosstalk?
Flash Forward: Flash Memory Storage Solutions
Oscilloscope Now Knows Where to Focus
DQS
DQ61
Command
Data
Address
Trigger from scope to logic analyzer or LA to scope
Flash Forward: Flash Memory Storage Solutions
Using De-embedding for “Virtual Probing”
PCB Topology
Via~Die Pad(incl. PKG)S-Parameter
OrSchematic
• Long established technique for calibrating network analyzers (a frequency domain instrument)
• Traditionally used to remove test fixture and loading effects from raw measurement data to measure true DUT behavior
• Time domain equivalent on scope enables probing anywhere a connection model is available
• DRAM -> Memory controller or even die pad• 2-port model enables probe BW and even loading compensation• 4-port S-parameters enable crosstalk and reflection removal
S-ParameterOr
Schematic
Flash Forward: Flash Memory Storage Solutions
System Model for Virtual Probing
RxController
TxDRAM
ChannelS-parameters
Scope probeImpedances
Package Probe S-parameters
Tx, Rx Impedance Package S-parameters, RLC
Flash Forward: Flash Memory Storage Solutions
How Does it Work?
Simulated Signal
Measured Signal
Transfer Function H(s)
Measured Signal
Simulated SignalTransfer Function H(s)
═Frequency Domain
InvFFT(1/H(s))
(d/dt)
Measured Signal
Simulated Signal═
Time Domain
Flash Forward: Flash Memory Storage Solutions
Putting Virtual Probing to Work
Measured waveform at the probing point
Simulated waveform at the DRAMSimulated waveform at the controller
- simulation- measurement
- simulation- measurement
Flash Forward: Flash Memory Storage Solutions
Automation Pre-Configured or CustomizedSpecification requirements, characterization algorithms and analysis scripts can
be encapsulated in automated suites, including remote control of DFx IP
HTML reports easily shared between teams or suppliers/customers
Protocol and timing violations checking
Encapsulate and automate proprietary or IP protected procedures
Pre-configured JEDEC parameter and design characterization measurements
Flash Forward: Flash Memory Storage Solutions
Conclusion• The next generation of memories require a next
generation approach to design and test, with a focus on signal integrity
• The keys to success are already available:• Design with signal integrity in mind• Engineer probing and measurement along with the design• Discard old assumptions about what instruments can do
• Hundred channel wide eye diagrams with logic analyzer• Ultra high resolution delay/skew measurement• Oscilloscope virtual probing at controller and die using simulation models• Pre-configured and customized measurement automation linked to
measurement acceleration IP
Embrace them and pull way ahead of the competition!