nikhef 27 feb 2007relaxd serial readout status1 relaxd serial readout - status motherboard master...

NIKHEF 27 Feb 2007 RELAXd Serial Readout Status 1

RELAXd Serial Readout - Status

Motherboard MASTER

RELAXd Chipboard – SLAVE

ADC DACs Flash Power

FPGA LatticeSC15 MPix0

Serial data up to 600Mbps

control

MPix1

MPix2

MPix3

up to 3Gbps

Ext. inputs(ext. shutter etc.)

SLAVE 2

SLAVE 3 etc.

serial

8b/10b

Idea:


Master – Slave Communication Protocol

16bit words

SOPHeader

Index++, length

Command ID

CommandCommand

Parameters/Data

CRCEOP

Trailer

16bit words

SOP

Index++, length

Data

CRCEOP

Header

Trailer

• Only one command (Mpix_Mode, Read_Status, Set_Config, Set_Int_DAQ) in each command block (no command list necessary)

Commands/data sent from Master to Slave Data sent from Slave/MPix to Master


Implementation - Schematics of Data Path

PCS 8b/10b

FIFO_Out16b x 512

OSCA130MHz

Pcs_OutSM

16b1b

1b

3GHz 150 MHz

16b

FIFO_In16b x 512

Pcs_InSM

16b16b

SM reset

SDR_Out_0

600 MHz

SDR_Out_1

SDR_Out_2

SDR_Out_3

4b

4b

4b

4b

1b

to MPixQuad

to Master SDR_In_0

SDRSM

16b SDR_In_1

SDR_In_2

SDR_In_3

4b

4b

4b

4b

1b

1b

1b

1b

1b

1b

1b

16b

fClock_inInt. DAQ ControlSM

FPGA

Data_Out

Data_In

M0, M1,Shutter, Enable_In, Reset

Enable_out

Ext_shutterExt_clk

delay0

delay1

delay2

delay3

PLL DLL

reset

type TX_STATE_TYPE is (IDLE, SENDING_DATA); type RX_STATE_TYPE is (ERROR, IDLE, READING_DATA, M_RESET);type MPIX_STATE_TYPE is (ERROR, IDLE, READ_COMMAND, SET_MPIX_MODE, SETTING_MATRIX, READING_MATRIX, SETTING_DACS, COUNTING, RESETTING_MATRIX);


SDR Block – gearing 4 to 1

Channel data_out to fast_clock alignment


Clock Path (backup)

PCS 8b/10b

FIFO_Out16b x 512

OSCA

130MHz

Pcs_OutSM

3GHz 150 MHz

FIFO_In16b x 512

Pcs_InSM

SDR_Out_0

600 MHz

SDR_Out_1

SDR_Out_2

SDR_Out_3

1b

to MPixQuad

to Master SDR_In_0

SDRSM

SDR_In_1

SDR_In_2

SDR_In_3

1b

1b

1b

1b

1b

1b

1b

fClock_in

FPGA

Data_Out

Data_In


Enable_out

Ext_shutterExt_clk

delay0

delay1

delay2

delay3

PLL DLL

reset

fClk

DIV/4 sClk

rx_clk

rx_refClk

tx_refClk


Clock Path (baseline)

PCS 8b/10b

FIFO_Out16b x 512

OSCA

130MHz

Pcs_OutSM

3GHz 150 MHz

FIFO_In16b x 512

Pcs_InSM

SDR_Out_0

600 MHz

SDR_Out_1

SDR_Out_2

SDR_Out_3

1b

to MPixQuad

to Master SDR_In_0

SDRSM

SDR_In_1

SDR_In_2

SDR_In_3

1b

1b

1b

1b

1b

1b

1b

fClock_in

FPGA

Data_Out

Data_In


Enable_out

Ext_shutterExt_clk

delay0

delay1

delay2

delay3

PLL_ref

DLL

reset

fClk

DIV/4 sClk

rx_clk

rx_refClk

tx_refClk

PLL


entity top is port (

-- CMOS global_reset: in std_logic; -- reset button ? ext_clk: in std_logic; -- clock from ext. oscilator ext_shutter: in std_logic; -- LVDS medipix mpix0_data_in: out std_logic; mpix1_data_in: out std_logic; mpix2_data_in: out std_logic; mpix3_data_in: out std_logic;

mpix0_fclock_in: out std_logic; mpix1_fclock_in: out std_logic; mpix2_fclock_in: out std_logic; mpix3_fclock_in: out std_logic;

mpix0_enable_in: out std_logic; mpix1_enable_in: out std_logic; mpix2_enable_in: out std_logic; mpix3_enable_in: out std_logic;

mpix0_data_out: in std_logic; mpix1_data_out: in std_logic; mpix2_data_out: in std_logic; mpix3_data_out: in std_logic;

mpix0_enable_out: in std_logic; mpix1_enable_out: in std_logic; mpix2_enable_out: in std_logic; mpix3_enable_out: in std_logic; •

-- CMOS medipix mpix_reset: out std_logic; -- active low!

mpix0_shutter: out std_logic; -- or common to all? mpix1_shutter: out std_logic; mpix2_shutter: out std_logic; mpix3_shutter: out std_logic;

mpix_M: out std_logic_vector(1 downto 0); --- mpix0_spareFSR: out std_logic; -- only in mpix2.1 --- mpix1_spareFSR: out std_logic; --- mpix2_spareFSR: out std_logic; --- mpix3_spareFSR: out std_logic; mpix_polarity: out std_logic; mpix_p_s: out std_logic; --set to 0 !! mpix_enable_tpulse: out std_logic;

-- pcs serial inputs/outputs pcs_hdinp_0, pcs_hdinn_0 : in std_logic; pcs_hdoutp_0, pcs_hdoutn_0 : out std_logic

);end;

ADC/DAC/Power IO not included yet!

Total: LVDS I/O - 8/12 + serdes 1/1 CMOS I/O - > 3/10

FPGA Inputs/Outputs


FPGA Inputs/Outputs notes:

• Serdes CH0, for debugging maybe also useful another channel (CH1)• external shutter• Ref clock (CMOS ?)• Reset and Load_Config buttons• would be nice to have some probe pins (2 to 4 ?)• additional switches (2 ?)• and status LEDs (4 ?)• DAC/ADS/Power chip IO’s …• something else ???


SC15 IO Data Sheet

•Fpga LatticeSC15 – 139 IO pins, 4 SERDES, 17x17mm (256-ball fpBGA pack).


1

2

3

45

7

6


FPGA SC15 Utilization


FPGA SC15 Power Calculation


Test Bench Setup – SC25 Evaluation Board

PCS 8b/10b

FIFO_Out16b x 512

Pcs_OutSM

16b1b

1b

3GHz150 MHz

16b

FIFO_In16b x 512

Pcs_InSM

16b16b

Reset_bypass

SDR_Out_0

SDR_OutSM

16b

600 MHz

SDR_Out_1

SDR_Out_2

SDR_Out_3

4b

4b

4b

4b

1b

to MPix

to MasterSDR_In_0

SDR_InSM

16b SDR_In_1

SDR_In_2

SDR_In_3

4b

4b

4b

4b

1b

1b

1b

1b

1b

1b

1b

CommandStatus

Registers16b x 16

CommandSM

16b

fClock

MPix ControlSM

FPGA

Jtag_Tracy“Logic Analyzer”

OSCA Clk_130MHz

“Master”Control

Emulator

1b

1b

PCSm

Jtag-USB

PCSethernet

MarvellEthernetBoard

ethernet

TracyFIFO

LatticeSCM Evaluation Board

SWITCHES

Out pins,LED’s


Current Test Setup: LatticeSC Evaluation Board + Medipix (one chip)


Measured speed without errors

FPGA I/O only: > 532 MHz (higher not tested yet), Master-Slave 2.66 Gbit/s;

Medipix 2.1: • Fast Shift Register – 266 MHz (FSR test mode)• Set/Read matrix – 83 MHz ok (100 MHz with a data shift in bits 0 of pixel row 0

and errors in the last pixel column) ;

Medipix MXR (with default DAC settings): • FSR – 166 MHz (matrix setting mode)• S/R matrix – 100 MHz ok, 166 MHz with errors in the last or first column;• should be faster when better DAQ (lvds) settings loaded (not tested yet)

fast 8b/10b serial link and communication between Lattice SC FPGA and Medipix work.


FPGA SC25 Eval Board Utilization


FPGA SC25 Eval Board Power Calculation


LatticeSC15FPGA

EPROM

DACADC

CSMA

JTAGPWR

C

V-bias

FLEX ?

Standard serial< 3.4 Gbits/s 8b/10b(clock encoded in data)

Lattice SCEvaluation board(“master”)

ethernet

Marvell ethernet board

Planned Test Bench with Slave BoardSlave board prototype


To Do:

• Designing the Slave board prototype and Quad chip carrier (see Bas v.d. Heijden talk) 10 Lattice SC15 Fpga’s already received (see pic);

• Connect the Lattice evaluation board with PC over ethernet via Marvell board and get FPGA-SDRAM interface running, so eval. board can be used as “master” for a slave board evaluation. (Marvell board already in our hands.) • Complete the firmware for slave board.• Test clock scheme using rx_clock from Master!• PCS checksum, FIFO setup/hold time, SDR internal DAQ, external shutter• Error handling etc.

nikhef 27 feb 2007relaxd serial readout status1 relaxd serial readout - status motherboard master...

Documents

sdr sm sdr

master sdr

b fclock

slave data

logic mpix0

logic mpix1

logic mpix2

channel data