nimmi james
TRANSCRIPT
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CONTENTS
ARM History
Applications
ARM Members Architecture
Arm CONTROLLERS
INSTRUCTIONS
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Brief history of ARM
Founded in 1990.
ARM -Advanced Risc Machines
32bit RISC processor from ARM Holdings.ARM Holding is a joint venture between
Acron computers, Apple computers and VLSI
Technology.
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ARM PARTNER
ARM Holdings - supplies ARM processor Core
doesnt manufacture ARM processor chips .
designs the ARM processor core licences its ARM IP to their networked
partners.
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ARM POWERED PRODUCTS
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Why ARM here?
most licensed ;widespread processor cores in
the world
low power consumption( 3.0v to 3.6v)reasonable performance
used in portable devices like mobilephones.
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ARM MEMBERS
ARM 1
ARM 2
ARM3
ARM4
ARM5
ARM6
ARM7
ARM8
STRONG ARM ARM9
ARM10
ARM11
ARM11 Series - Performanceprocessors based on the
ARMv6 architectureARM9 Series- Popular processorsbased on the the ARMv5architecture
ARM7 Series- Classic processorsfor general purpose
applications
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OPERATING MODES1. User Mode- Normal program execution state
2. Fast Interrupt Processing (FIQ) Mode - when a highpriority interrupt is raised.
3. Normal Interrupt Processing (IRQ) Mode- when anormal priority interrupt is raised.
4. Supervisor /Software Interrupt Mode- Protected modefor operating system support .Eg: when reset /software interrupt instruction isexecuted.
5. Abort Mode - when data or instruction fetch is aborted.
6. System Mode for running Operating system tasks.
7. Undefind Instruction Mode-when processor tries toexecute an undefined instruction.
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REGISTERS OF ARMARM7 register set thirty-seven 32bit registers. 30 are general purpose registers
16 general purpose registers(R0 to R15) are available
in ARM-mode (user mode) Register structure depends on mode of operation
R13 - Stack Pointer (SP)
R14 - subroutine Link Register for branch and link
instructions R15 - Program Counter (PC)
R16 - state register (CPSR, Current Program StatusRegister)
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CPSR-Current program status register CPSR holds execution status of the processor,processor operation mode,interrupt
enable bit status,etc.
N=1:The result of ALU operation is negative.
Z=1:The result of ALU operation is zero.
C=1:carry generated as a result of the operation executed in ALU.
V=1:ALU operation resulted in overflow.
J bit : whether the processor is Jazelle state or not .
T bit : whether the ARM is using 32-bit ARM instructions or 16-bitThumb instructions.
I and F flags are used for disabling interrupts.
If I= 1,NORMAL interrupts are disabled.
IfF=1 ,FAST interrupts are disabled.
B31B31 B30 B29 B28 B27 B25 to B26 B24 B8 to
B23
B7 B6 B5 B0 toB4
NN Z C V Q J I F T ModeSelect
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Pipelines
splitting one task in to multiple subtasks
executing the subtasks of successive tasksparallely
in multiple hardware units or sections.ARM processors:
FIRST GENERATION-3 stage pipelining
ARM73 stage pipelining
ARM9 5 stage
ARM10 6 stage
ARMARM111188
stage
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ARM7TDMI
TDMI = (?)
Thumb instruction set
Debug-interface (JTAG/ICEBreaker) Multiplier (hardware)
Interrupt (fast interrupts)
The most used ARM-version
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DSP enhancement
To improve the ARM architecture for digital
signal processing and multimedia applications,a few new instructions were added to the set.
These are signified by an "E" in the name of
the ARMv5TE and ARMv5TEJ architectures. E-
variants also imply T,D,M and I.
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ARM Jazelle Technology
Provides a highly-optimized implementation
of the Java Virtual Machine (JVM).
Speeds up execution times. Provides consumers with an enriched user
experience on their mobile devices.
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ARM MEDIA EXTENSIONS
streaming media performance (film,
video phone, music and more)
more human-oriented interfaces
(voice and handwriting recognition)
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ARCHITECTURE VERSIONS AND
VARIANTS
Sixmajor versionsof the instruction
set have been defined to date, denoted by ARMv1,ARMv2,ARMv3-26-bit architecture.
ARMv4
ARMv5 ARMv6
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ARM ARCHITECTUREArchitect
ure
THUMB DSP Jazelle Media
ARMv4
TX
ARMv5
TEX X
ARMv5TEJ
X X X
ARMv6 X X X X
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General Purpose Microprocessor
SystemDATA BUS
ADDRESS BUS
General
Purpose
Micro-
processor
RAM ROMI/O
PORTTIMER
SERIALCOM
PORT
CPU
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MICROCONTROLLERS based
onARM7TDMI
The LPC2131/32 microcontrollers are based
on 16/32 bit ARM7TDMI
One 8 channel 10-bit A/D Converters ,withconversion time as low as 2.44micro sec.
MULTIPLE Serial interfaces.
Two32
-bit timer/counters.
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COMPARISON
ARM
1. Low powerconsumption (3.0vto 3.6v).
2. High speed.
3. Supports DSP,Media.
4. Supports 8/16/32 bit
instructions.
5. High cost.
PIC
Power consumption5v
Low speed
Do not support DSP
Supports8
bit instruction
Low cost
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ARM
INSTRUCTIONS
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The Instruction Set Architecture(ISA) of supportsdifferent types of Instruction sets,namely:
1. ARM INSTRUCTION SET-The original ARMinstruction.Here all instruction are32bitwideand word aligned.since all instructions are wordaligned,one single fetch reads four 8bit memory
locations.
2. THUMB INSTRUCTION SET-These instructionscan be considered as a 16bitcompressed form
of the orginal32
bit ARM instruction.These instructions can be executed bydecompressing the instruction to the original32bit ARM instructions
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3.JAZELLE INSTRUCTION SET- Jazelle is a
technique that allows Java Bytecode to be
executed directly in the ARM architecturea.
4.DATA PROCESSING INSTRUCTION-The data
processing instructions includeOPERATION CATEGORY INSTRUCTION
Arithmetic ADD,ADC,SUB,SBC,RSB,RSC
Logical AND,ORR,EOR,BIC
Comparison CMP,CMN,TST,TEQ
Data movement MOV,MVN
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5.BRANCHING INSTRUCTIONS-diverts theprogram flow.BX,B,BL etc.
6.MULTIPLIC
A
TION Instruction-MUL,MLA,MLL,MLAL.
7.CO-PROCESSOR SPECIFIC INSTRUCTIONS-
ARM does not execute certain instructions
and lets a co-processor to execute these
instructions.CDP,LDC,STC,MRC,MCR.
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CONDITIONAL INSTRUCTIONS
All ARMinstructions areconditional.
Std formopcodeoperands
eg 1: ADDALr0,r1,r2
eg 2:ADDEQ
r0,r1,r2
CONDITIO
N CODE
DESCRIPTION FLAG TO
TEST
EQ Check the equality Z==1
NE Check the non-equality Z==0
CS/HS Carry C==1
CC/LO No carry C==0
MI Negative N==1
PL Positive or zero N==0
VS Overflow V==1
VC No overflow V==0
AL Execute always None
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SUMMARY
32-bit RISC-processor core (32-bit instructions)
37 pieces of32-bit integer registers (16 available)
Pipelined (ARM7: 3 stages)
Cached (depending on the implementation) Von Neuman-type bus structure (ARM7),
Harvard (ARM9)
8 / 16 / 32 -bit data types
7 modes of operation (usr, fiq, irq, svc, abt, sys,und)
Simple structure
Good speed/powerconsumption ratio
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REFERENCES
Computer organisation and architecture-carl
hamacher.
The 8051 microcontrollers-Muhammad alimazidi
www.armprocessorsmanuval.com
www.arm.architecture.com
www.arm7processor.com
www.arm7processors,family.com
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THANK YOUTHANK YOU
THANK YOUTHANK YOU