noc, noc! who's there? rabi n. mahapatra texas a&m university
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April 19, 2023 Rabi N. Mahapatra - IIT Delhi 2
Agenda Why NoCs? What are NoCs? NoC Research Areas NoC Research @ TAMU
Core Network Interface Architecture Design
Concurrent On-Line Testing (COLT) in NoC-based SoCs
Useful Resources Summary
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 3
Why NoCs? Era of multi-core SoCs
Communication intensive applications
Bus-based communication infrastructures suffer from scalability, predictability and performance limitations
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 4
What are NoCs? Networks-on-a-Chip (NoC) are
essential
Features: Higher availability Easier power management Higher performance Predictable operation
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 5
Typical NoCs Regular topologies Simple non-blocking routing
IP Core
CNI
Router Logic
To/ From Network
Network Tile
Figure 1: NoC Architecture
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 6
Some NoC Research Areas Application Mapping Architecture design and synthesis Fault Tolerance Flow control/congestion control Power management On-chip routing NoC Testing Core Interfacing Communication reliability
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 7
NoC Research Summary Over 29 Academic Institutions
worldwide
Industrial Companies Arteris (www.arteris.com) ST Microelectronics Intel
Over 800 publications…and counting.
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 8
NoC Research @ TAMU Mapping heuristic for communicating
resources to target regular topology On-chip communication reliability
FEC in NoCs Core-Network Interface
Architecture Concurrent On-Line Testing
(COLT) in NoCs Peak Power Management in NoCs
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 10
Core-Network Interface (CNI) IP cores have two types of interfaces
Standard interfaces: OCP-IP, VSIA, etc Non-standard/in-house interfaces:
proprietary to a particular corporation
NoCs have differing configurations too! Topology, routing policies, flow control,
reliability configuration.
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 11
CNI CNI lets IP cores talk the language of
NoC
Basic operation: Packetization De-packetization
IP Core data
NoC configuration data
Power management data
CNIIP Core CNI IP Core
NoC
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 12
Related Research CNI first studied in BhojwaniVLSID’03
Packetization cost assessment for 3 techniques:
software, hardware wrapper and on-chip co-processor (Xtensa)
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 13
CNI Requirements Need for a customizable CNI
architecture IP core interface On-chip communication reliability NoC configuration
Additional features Dynamic power/thermal management IP core test support NoC reconfiguration
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 14
CNI Architecture
IP Core
IP Core
IP Core
IP Interface Arbiter
TC
Link Controller
CNIC
ENC
DEC
ST
Address/Data Signals
Test Signals
PACK
De-PACK
CNI-PM
CNI-CS
DT/RT Legend
DT/RT – Destination Table/Route TableENC – Reliability EncoderDEC – Reliability DecoderCNIC – CNI ControllerST – State TableTC – Test ControllerCNI-PM – CNI Power ManagerCNI-CS – CNI Communication SchedulerPACK – PacketizerDe-PACK – De-Packetizer
CNI Data lines
CNI Signal lines
Buffer element
[Bhojwani ISQED’06]
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 15
CNI Architecture
Interface Arbiter Replays interface protocols of the IP Cores Receives and forwards communication
request and responses
IP Core
IP Core
IP Core
IP Interface Arbiter
TC
Link Controller
CNIC
ENC
DEC
ST
Address/Data Signals
Test Signals
PACK
De-PACK
CNI-PM
CNI-CS
DT/RT Legend
DT/RT – Destination Table/Route TableENC – Reliability EncoderDEC – Reliability DecoderCNIC – CNI ControllerST – State TableTC – Test ControllerCNI-PM – CNI Power ManagerCNI-CS – CNI Communication SchedulerPACK – PacketizerDe-PACK – De-Packetizer
CNI Data lines
CNI Signal lines
Buffer element
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 16
CNI Architecture
Link Controller Interfaces to on-chip router Receives and forwards flits from and to
NoC
IP Core
IP Core
IP Core
IP Interface Arbiter
TC
Link Controller
CNIC
ENC
DEC
ST
Address/Data Signals
Test Signals
PACK
De-PACK
CNI-PM
CNI-CS
DT/RT Legend
DT/RT – Destination Table/Route TableENC – Reliability EncoderDEC – Reliability DecoderCNIC – CNI ControllerST – State TableTC – Test ControllerCNI-PM – CNI Power ManagerCNI-CS – CNI Communication SchedulerPACK – PacketizerDe-PACK – De-Packetizer
CNI Data lines
CNI Signal lines
Buffer element
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 17
CNI Architecture
Encoder and Decoder Provide end-to-end communication
reliability via coding schemes Support for ED+R, FEC
IP Core
IP Core
IP Core
IP Interface Arbiter
TC
Link Controller
CNIC
ENC
DEC
ST
Address/Data Signals
Test Signals
PACK
De-PACK
CNI-PM
CNI-CS
DT/RT Legend
DT/RT – Destination Table/Route TableENC – Reliability EncoderDEC – Reliability DecoderCNIC – CNI ControllerST – State TableTC – Test ControllerCNI-PM – CNI Power ManagerCNI-CS – CNI Communication SchedulerPACK – PacketizerDe-PACK – De-Packetizer
CNI Data lines
CNI Signal lines
Buffer element
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 18
CNI Architecture
Packetizer and De-packetizer Prepare and extract data to and from flits
IP Core
IP Core
IP Core
IP Interface Arbiter
TC
Link Controller
CNIC
ENC
DEC
ST
Address/Data Signals
Test Signals
PACK
De-PACK
CNI-PM
CNI-CS
DT/RT Legend
DT/RT – Destination Table/Route TableENC – Reliability EncoderDEC – Reliability DecoderCNIC – CNI ControllerST – State TableTC – Test ControllerCNI-PM – CNI Power ManagerCNI-CS – CNI Communication SchedulerPACK – PacketizerDe-PACK – De-Packetizer
CNI Data lines
CNI Signal lines
Buffer element
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 19
CNI Architecture
CNI Controller Manages CNI data-paths Responsible for issuing NoC management
commands
IP Core
IP Core
IP Core
IP Interface Arbiter
TC
Link Controller
CNIC
ENC
DEC
ST
Address/Data Signals
Test Signals
PACK
De-PACK
CNI-PM
CNI-CS
DT/RT Legend
DT/RT – Destination Table/Route TableENC – Reliability EncoderDEC – Reliability DecoderCNIC – CNI ControllerST – State TableTC – Test ControllerCNI-PM – CNI Power ManagerCNI-CS – CNI Communication SchedulerPACK – PacketizerDe-PACK – De-Packetizer
CNI Data lines
CNI Signal lines
Buffer element
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 20
CNI Architecture
Communication Scheduler (CNI-CS) Sets QoS parameter for on-chip communication
Power Manager (CNI-PM) Manage communication power with injection
control
IP Core
IP Core
IP Core
IP Interface Arbiter
TC
Link Controller
CNIC
ENC
DEC
ST
Address/Data Signals
Test Signals
PACK
De-PACK
CNI-PM
CNI-CS
DT/RT Legend
DT/RT – Destination Table/Route TableENC – Reliability EncoderDEC – Reliability DecoderCNIC – CNI ControllerST – State TableTC – Test ControllerCNI-PM – CNI Power ManagerCNI-CS – CNI Communication SchedulerPACK – PacketizerDe-PACK – De-Packetizer
CNI Data lines
CNI Signal lines
Buffer element
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 21
CNI Architecture
Test Controller Interface to Test Wrapper of attached IP
cores
IP Core
IP Core
IP Core
IP Interface Arbiter
TC
Link Controller
CNIC
ENC
DEC
ST
Address/Data Signals
Test Signals
PACK
De-PACK
CNI-PM
CNI-CS
DT/RT Legend
DT/RT – Destination Table/Route TableENC – Reliability EncoderDEC – Reliability DecoderCNIC – CNI ControllerST – State TableTC – Test ControllerCNI-PM – CNI Power ManagerCNI-CS – CNI Communication SchedulerPACK – PacketizerDe-PACK – De-Packetizer
CNI Data lines
CNI Signal lines
Buffer element
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 22
CNI Analysis IP Core interface: OCP-IP 2.0
compliant NoC configuration:
4x4 2D folded torus Source routing
SystemC functional model integrated into NoCSim
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 24
Why Test Concurrently ? Design complexity Noise margins Some sources of failure:
Electro-migration, stress migration, time-dependent dielectric breakdown, thermal cycling.
Reducing lifetimes Need to assess system health
before recovery schemes can be activated
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 25
On-Line Test What do we mean by OLT?
In-field confidence in the correct functional operation of the system
Precursor to reconfiguring system to address a fault
Can by achieved at 100% overhead by using a parallel execution stream for comparison!
Our goal to keep it much lower Possibly < 10%! But at other costs…
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 26
On-Line Test Challenges Test cost
Test power (up to 2x) Test time Test volume
These make on-line test management a challenge!
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 27
On-Line Testing in Research Manufacturers insert Infrastructure
IP (I-IP) into SoC to improve yield and to provide test support within designs
Reuse these I-IPs to perform the on-line SoC test
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 28
OLT in Research Detect idle periods of execution and
test SoC components using I-IPs non-concurrent on-line testing
But detecting the idle periods is a challenge itself!
Another option is needed!
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 29
Concurrent On-Line Test Concurrent On-Line Testing
(COLT) Test in the presence of executing
applications No need to “turn off” applications
Challenges to COLT Test + Application under power budget Test has to be restorative in nature Test Intrusion into Application has to be
minimized
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 30
Test Infrastructure IP (TI-IP) Introduce a Test Infrastructure-IP
(TI-IP) into the SoC to manage COLT Use the NoC as Test Access
Mechanism (TAM) Manage test intrusion challenge!
[Bhojwani ISQED’07]
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 31
Conceptual NoC enabled SoC + TI-IP
NoC
TestI-IP
TestI-IP
CNI
CNI
CNI
CNI
CNI
IPCore
IPCore
IPCore
IPCore
IPCore
BIST
BIST
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 32
Proposed TI-IP Architecture TI-IP
Components Input/Output
Queues Test Memory TI-IP Engine
TEST
MEM
TI-IPENGINE
Figure 4: On-line Test I-IP Architecture
ON-LINE TEST I-IP
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 33
COLT in Action CNI determines when IP core test is
required Request sent to TI-IP TI-IP determines if OLT of IP core is
feasible Involves
System Snapshot Collection, Test Vector Routing, Test Scheduling
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 34
Time
Core 1
Core 2
Core 3
Core n
Normalmode
Test mode
TR SSD TA TD TAP
On-line Test Stages of Operation
Figure 5: SoC operation timeline with on-line test integrated
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 35
WAIT
TIIPConfig
SSIssue
Test Routing & Acceptance
Test Delivery
SS Process
tiip_configtreq
ss_info
ss_not_complete
ss_complete
treq
tresp
ss_i
nfo
ss_r
eq
Figure 6: TI-IP FSM
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 36
Multi TI-IP Configuration COLT has to be scalable Proximity of TI-IP affects test power
consumption
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 37
Multi TI-IP Multiple TI-IPs in NoC working co-
operatively TI-IP testing is needed too Token Ring of TI-IPs helps in
addressing this challenge
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 38
Robust COLT Protocol Robust protocol is essential Identify potential hazards Embed mitigation techniques into
COLT Protocol
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 39
TReq
CNI TI-IP
(a)
TReqResp
System Snapshot Collection
Test Acceptance
Test Vector Delivery
Test Request
Event
Test Response
Event
SSReq
SSReq
SSReq
SSResp
SSResp
SSResp
TI-IP CNI CNI CNI
(b)
CNIAlarm
TThrottleTThrottle
TThrottle
CNI TI-IP CNI CNI CNI
(d)
TV1
TV1
TV1
TV2TV2
TV2TV3TV3
TV3TV1
TV1
TV1
TI-IP CNI CNI CNI
(c)
TestManageToken
TestManageToken
TestManageToken
TestManageToken
TI-IP 1 TI-IP 2 TI-IP 3
Token Transfer Period
Token Transfer Period
Token Transfer Period
(e)
Figure 8: (a) Test Request protocol step, (b) System snapshot collection protocol step, (c) Test Vector Delivery protocol step, (d) Test Throttle protocol step and (e) Test Management Token protocol step assuming 3 TI-IP configuration
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 40
Experimental Setup Two SoC configurations built around
NoCSim Embedded System Synthesis Benchmark
Suite (E3S) provide application configuration
ITC’02 SoC Test Benchmarks provide SCAN test configuration information
Only considering SCAN for now due to test data availability
Only testing IP cores (for now)
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 41
Experimental Setup Assign 1 TI-IP to an SoC and let it
occupy a whole NoC tile For a 22mm x 22mm chip laid out as a
4x4 2D torus, each tile could be 5mm x 5mm [Towles DAC’01]
5.2% area overhead Multi TI-IP configurations also
prepared and validated in NoCSim environment
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 42
Test Configurations
soc_config1 soc_config2
TI-IP Core
Office Automation
Consumer
Networking
Auto industry
Telecom
Legend
Each network tile consists of an IBM 405GP. (area constraints)
Task graph assignment done by hand.
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 45
Test Throttling response to misbehaving applications
Energy Profile demonstrating effect of Test Throttling on misbehaving application
2.00E-09
3.00E-09
4.00E-09
5.00E-09
6.00E-09
7.00E-09
8.00E-09
9.00E-09
1.00E-08
1 2160 4319 6478 8637 10796 12955 15114 17273 19432
Time
En
erg
y (
J)
No test throttling Test throttled application
Energy profile demonstrating TI-IP Test Throttling effect on misbehaving application
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 46
COLT Protocol – Avoiding Starvation
Normal on-line test mode vs Starvation Hazard test mode energy profile
2.50E-09
3.00E-09
3.50E-09
4.00E-09
4.50E-09
5.00E-09
5.50E-09
6.00E-09
0
11
9
23
8
35
7
47
6
59
5
71
4
83
3
95
2
10
71
11
90
13
09
14
28
Time
En
erg
y (
J)
Normal on-line test mode Mitigating starvation impact on test
Energy profile demonstrating starvation hazard mitigation
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 47
TI-IP Synthesis Results With Synopsys Design Compiler
using Virginia Tech VLSI for Telecommunications TSMC-0.25um, 2.5V standard cell library
Gate Count: 83K Power: 520mW Leakage: 32uW
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 48
Summary Multi-core systems are here to stay Address communication challenges
with NoCs Interfacing with a variety of IP cores
require the use of a generic CNI architecture
Lowering reliability under higher costs of testing requires concurrent on-line test of on-chip components
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 49
Summary Need for COLT benchmarks
April 19, 2023 Rabi N. Mahapatra - IIT Delhi 50
Useful Resources On-Chip Network Research Resources
Pagehttp://www.cl.cam.ac.uk/~rdm34/onChipNetBib/noc.html