node list tolerance analysis

Node ListToleranceAnalysisEnhancing SPICE

Capabilitieswith Mathcad

Other Related Titles of Interest Include:

Tolerance Analysis of Electronic Circuits Using MATLABRobert R. Boyd, University of California, Irvine, CaliforniaISBN: 0849322766

Tolerance Analysis of Electronic Circuits Using MATHCADRobert R. Boyd, University of California, Irvine, CaliforniaISBN: 0849323398

The Electronics Handbook, Second EditionJerry Whitaker, Technical Press, Morgan Hill, CaliforniaISBN: 0849318890

PSPICE and MATLAB for Electronics: An Integrated ApproachJohn O. Attia, Prairie View A&M University, TexasISBN: 0849312639

Electronics and Circuit Analysis Using MATLAB, Second EditionJohn O. Attia, Prairie View A&M University, TexasISBN: 0849318920

7028_C000.fm Page ii Thursday, January 19, 2006 11:05 AM

Node ListToleranceAnalysis

A CRC title, part of the Taylor & Francis imprint, a member of theTaylor & Francis Group, the academic division of T&F Informa plc.

Boca Raton London New York

Enhancing SPICECapabilities

with Mathcad

Robert R. Boyd

Published in 2006 byCRC PressTaylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300Boca Raton, FL 33487-2742

2006 by Taylor & Francis Group, LLCCRC Press is an imprint of Taylor & Francis Group

No claim to original U.S. Government worksPrinted in the United States of America on acid-free paper10 9 8 7 6 5 4 3 2 1

International Standard Book Number-10: 0-8493-7028-0 (Hardcover) International Standard Book Number-13: 978-0-8493-7028-1 (Hardcover) Library of Congress Card Number 2005052136

This book contains information obtained from authentic and highly regarded sources. Reprinted material isquoted with permission, and sources are indicated. A wide variety of references are listed. Reasonable effortshave been made to publish reliable data and information, but the author and the publisher cannot assumeresponsibility for the validity of all materials or for the consequences of their use.

No part of this book may be reprinted, reproduced, transmitted, or utilized in any form by any electronic,mechanical, or other means, now known or hereafter invented, including photocopying, microfilming, andrecording, or in any information storage or retrieval system, without written permission from the publishers.

For permission to photocopy or use material electronically from this work, please access www.copyright.com(http://www.copyright.com/) or contact the Copyright Clearance Center, Inc. (CCC) 222 Rosewood Drive,Danvers, MA 01923, 978-750-8400. CCC is a not-for-profit organization that provides licenses and registrationfor a variety of users. For organizations that have been granted a photocopy license by the CCC, a separatesystem of payment has been arranged.

Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used onlyfor identification and explanation without intent to infringe.

Library of Congress Cataloging-in-Publication Data

Boyd, Robert (Robert R.)Node list tolerance analysis : enhancing SPICE capabilities with Mathcad/ Robert R. Boyd.

p. cm.Includes bibliographical references and index.ISBN 0-8493-7028-0 (alk. paper)1. Electric circuits, Linear. 2. Analog electronic systems. 3. Electric circuit analysis. 4. Tolerance

(Engineering) 5. Mathcad. 6. SPICE (Computer file)

TK454.B66 2006621.3815--dc22 2005052136

Visit the Taylor & Francis Web site at http://www.taylorandfrancis.com

and the CRC Press Web site at http://www.crcpress.com

Taylor & Francis Group is the Academic Division of Informa plc.

7028_Discl.fm Page 1 Thursday, January 12, 2006 3:09 PM

Preface

The purpose of this book is to provide an improved SPICE-like, worst-case analysis(WCA) capability using Mathcad. To achieve more accurate WCA methods, aSPICE-like netlist or node list method of nominal circuit analysis was developedfirst. Subprogram routines were then added to perform tolerance analyses usingRoot-Sum-Square (RSS), Extreme Value Analysis (EVA), and Monte Carlo Analysis(MCA) in the DC, frequency, and time domains.

Note that SPICE is a generic term referring to the public domain softwaredeveloped by the University of CaliforniaBerkeley in the early 1980s. Severalcompanies were started after converting the Fortran code to C and adding a graphicsinterface. These commercial versions are very capable in nominal circuit analysisand, correspondingly, expensive.

There are many areas in SPICE WCA that range from nonexistent or weakcapability to erroneous analyses. Most if not all of these deficiencies still exist inmany commercial versions. These areas are:

A 400-sample Monte Carlo limitation not nearly enough for adequatestatistical confidence levels

No RSS capability No direct method of handling asymmetric component tolerances, e.g.,

+2%, 4% No Fast Monte Carlo Analysis (FMCA) capability* No single-run method of tolerancing inputs No direct method of detecting nonmonotonic components, which cause

erroneous WCA outputs No AC frequency sweep sensitivity capability No predefined beta (skewed) or bimodal (gapped) distributions available

for MCA

In addition, the SPICE random number generator used for MCA repeatedlysupplies the same set of random numbers with each analysis run. To correct this, anew seed must be supplied before each new run. (This is equivalent to having thesame 20 numbers come up every time in a Las Vegas keno game.) Some commercialversions may have improved a few of these areas, as most companies want to makea good product better.

All of these deficiencies have been addressed and corrected in the suppliedMathcad software on the CD and demonstrated using many examples in this book.For example, the number of Monte Carlo samples is now limited only by the amount

*

Boyd, R.,

Tolerance Analysis of Electronic Circuits Using Mathcad

, CRC Press, Boca Raton, FL, 1999,p. 87.

7028_C000.fm Page v Thursday, January 19, 2006 11:05 AM

of memory on the computer platform used. Those readers knowledgeable in statisticsknow that in Monte Carlo analysis, more is better.

It is the authors hope that this book will provide a much less expensive andmore accurate method of performing tolerance analysis of electronic circuits.

7028_C000.fm Page vi Thursday, January 19, 2006 11:05 AM

The Author

Robert R. Boyd was a technical instructor in the United States Air Force for 19years. Upon his retirement in 1971, he enrolled at the University of New Mexicoand received a B.S.E.E. degree with honors in 1974. He was subsequently employedin the aerospace industry, including 8 years with Hughes Aircraft Co., in analogcircuit design until 1993 and as a consultant until 2002. He taught courses intolerance analysis at the University of California Extension, Irvine, in 1998 and 1999.

He has authored two books,

Tolerance Analysis of Electronic Circuits UsingMATLAB

and

Tolerance Analysis of Electronic Circuits Using Mathcad

, both pub-lished by CRC Press in 1999.

7028_C000.fm Page vii Thursday, January 19, 2006 11:05 AM

This page intentionally left blank

Acknowledgments

I would like to give my thanks and credit to the following people at Taylor &Francis/CRC Press:

Engineering Editor, Nora Konopka for her successful presentation of mymanuscript to the publishing committee and for pleasant email conversation.

Editorial Project Development Manager, Helena Redshaw for her patience anddiligence in guiding me and the book material through to production.

Associate Editor, Allison Taub for smoothing out the rough spots and helpingwith the reviews.

Project Editor, Amber Stein for putting up with my frequent changes to themanuscript.

They have all been easy to communicate with and helped make the work ofwriting this book less painful than it would have otherwise been; and all this in spiteof several hurricanes!

Robert Boyd

Placerville, CA

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Table of Contents

PART I

Nominal Analysis

Chapter 1 Introduction

........................................................................................3

1.1 Nominal Analysis .............................................................................................31.1.1 Introduction ..........................................................................................31.1.2 The NDS Method of Nominal Circuit Analysis..................................41.1.3 General Guidelines...............................................................................5

1.2 Introduction to Node List Circuit Analysis .....................................................61.2.1 Rules and Definitions...........................................................................6

Chapter 2 Passive Circuits

...................................................................................9

2.1 Introduction to Node List Circuit Analysis (Part One)...................................92.2 Introduction to Node List Circuit Analysis (Part Two).................................162.3 All-Capacitive Circuit ....................................................................................212.4 All-Inductive Circuit ......................................................................................232.5 Twin-T RC Network ......................................................................................242.6 Broadband Pulse Transformer Model............................................................272.7 All-Capacitive Loops (ACL)..........................................................................302.8 All-Inductive Cutsets (ICS) ...........................................................................312.9 All-Capacitive Loop Example .......................................................................32References................................................................................................................34

Chapter 3 Controlled Sources

...........................................................................35

3.1 Controlled (Dependent) Sources....................................................................353.1.1 Voltage-Controlled Current Source (VCCS) .....................................353.1.2 Current-Controlled Current Source (CCCS) .....................................353.1.3 Voltage-Controlled Voltage Source (VCVS) .....................................353.1.4 Current-Controlled Voltage Source (CCVS) .....................................363.1.5 CCVS to VCVS .................................................................................363.1.6 CCCS to VCCS..................................................................................363.1.7 Four Rules that Must be Observed....................................................37

3.2 Floating VCVS...............................................................................................383.3 Circuits with M > 1 .......................................................................................413.4 First-Order MOSFET Model .........................................................................443.5 VCVS and CCCS Example ...........................................................................463.6 Two Inputs, Three Outputs ............................................................................50

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3.7 Third-Order Opamp Model............................................................................543.8 A Subcircuit Scheme .....................................................................................563.9 Subcircuit Opamp Model...............................................................................583.10 Fifth-Order Active Filter ................................................................................593.11 State Variable Filter........................................................................................603.12 Seventh-Order Elliptical Low-Pass Filter......................................................63

3.12.1 Stepping One Resistor Value .............................................................683.12.2 Stepping All Seven Capacitor Values ................................................71

3.13 Square Root of Frequency (+10 dB/decade) Circuit ....................................743.14 HV (200 V) Shunt MOSFET Regulator........................................................763.15 LTC 1562 Band-Pass Filter IC in a Quad IC................................................783.16 LTC 1562 Quad Band Filter IC.....................................................................793.17 BJT Constant Current Source A Simple Linear Model Using the

NDS Method ..................................................................................................873.18 uA733 Video Amplifier..................................................................................89References................................................................................................................95

Chapter 4 Leverriers Algorithm

......................................................................97

4.1 Numerical Transfer Function [1] ...................................................................974.2 Transfer Function Using Leverriers Algorithm for Twin-T

RC Network ..................................................................................................100References..............................................................................................................101

Chapter 5 Stability Analysis

............................................................................103

5.1 Unity Gain Differential Amplifiers..............................................................1035.2 Stability of LM158 Opamp Model..............................................................1065.3 High-Voltage Shunt Regulator Stability Analysis..................................109

Chapter 6 Transient Analysis

..........................................................................115

6.1 Introduction ..................................................................................................1156.2 Switched Transient Analysis........................................................................1186.3 N = 2 Switched Circuit Transient Response ...............................................1206.4 Comparator 100-Hz Oscillator.....................................................................1236.5 Transient Analysis of Pulse Transformer ....................................................1276.6 Passive RCL Circuit Transient Analysis......................................................1316.7 Mathcads Differential Equation Solvers.....................................................1336.8 A Mathematical Pulse Width Modulator (PWM) .......................................1356.9 Switching Power Supply Output Stage Buck Regulator .......................1376.10 State Space Averaging..................................................................................1406.11 Simple Triangular Waveform Generator......................................................1436.12 Quadrature Oscillator ...................................................................................1456.13 Wein Bridge Oscillator ................................................................................148References..............................................................................................................149

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Chapter 7 DC Circuit Analysis

.......................................................................151

7.1 Resistance Temperature Detector (RTD) Circuit ........................................1517.2 An Undergraduate EE Textbook Problem...................................................152

7.2.1 Matrix Solution To Demonstrate the Utility of the NDS Method ....................................................................................153

7.3 DC Test Circuit ............................................................................................1547.4 Stacking VCVSs and Paralleling VCCSs..................................................1587.5 DC Voltage Sweep (RTD Circuit) ...............................................................1597.6 RTD Circuit Step Resistor Value............................................................1617.7 Floating 5-V Input Source ...........................................................................164

Chapter 8 Three-Phase Circuits

.....................................................................167

8.1 Convert

Floating Voltage Inputs to Single-Ended Y Inputs ....................1678.2 Three-Phase NDS Solution..........................................................................170

8.2.1 Unbalanced Delta Load Single-Ended Inputs on A and B ............................................................................................170

8.2.2 Unbalanced Delta Load Single-Ended Inputs on A and C ............................................................................................172

8.3 Three-Phase Y Unbalanced Load ...........................................................1748.4 Three-Phase Y-Connected Unbalanced Load Floating

Delta Input....................................................................................................1778.5 Balanced Y- Load.........................................................................................181References..............................................................................................................186

Appendix I

............................................................................................................187Background Theory of NDS Method....................................................................187A-I.1 Theory of NDS Method...............................................................................196

A-I.1.1 An AC Floating VCVS ..................................................................199A-I.1.2 VCVS and CCCS...........................................................................203

PART II

Tolerance Analysis

Chapter 9 Introduction

....................................................................................211

9.1 Introduction ..................................................................................................2119.1.1 Tolerance Analysis of Circuits with Discrete Components ............2119.1.2 Analysis Methods.............................................................................212

9.2 Some Facts about Tolerance Analysis .........................................................2129.2.1 DC Analysis .....................................................................................212

9.2.1.1 Monte Carlo Analysis .......................................................2139.2.2 AC Analysis .....................................................................................2139.2.3 Transient Analysis ............................................................................217

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9.2.4 Asymmetric Tolerances....................................................................217References..............................................................................................................217

Chapter 10 DC Circuits

.....................................................................................219

10.1 Resistance Temperature Detector (RTD) Circuit......................................21910.2 A Note on Asymmetric Tolerances...........................................................22110.3 Centered Difference Approximation Sensitivities ...............................22210.4 RTD Circuit Monte Carlo Analysis (MCA) .............................................22410.5 RTD MCA with R4 Tolerance = 10%......................................................22610.6 RTD Circuit Fast Monte Carlo Analysis (FMCA)...................................22710.7 A CASE FMCA Greater than EVA......................................................... 22810.8 Tolerancing Inputs.....................................................................................23110.9 Beta Distributions [46]............................................................................23210.10 RTD MCA Beta (Skewed) Distribution ..............................................23410.11 MCA of RTD Circuit using Bimodal (Gapped)

Distribution Inputs.....................................................................................236References..............................................................................................................239

Chapter 11 AC Circuits

.....................................................................................241

11.1 Circuit Output vs. Component Value........................................................24111.2 Exact Values of C1 Sensitivity .................................................................24711.3 Multiple-Output EVA................................................................................24811.4 Butterworth Low-Pass Filter Circuit.........................................................25011.5 Butterworth Low-Pass Filter MCA...........................................................25111.6 Butterworth Low-Pass Filter EVA ............................................................25311.7 Butterworth Low-Pass Filter FMCA ........................................................25411.8 Multiple-Feedback Band-Pass Filter (BPF) Circuit ................................25511.9 Multiple-Feedback BPF MCA..................................................................25611.10 Multiple-Feedback BPF EVA ...................................................................25711.11 Multiple-Feedback BPF FMCA................................................................25911.12 Switching Power Supply Compensation Circuit .....................................26011.13 Switching Power Supply Compensation MCA ........................................26111.14 Switching Power Supply Compensation EVA..........................................26211.15 Switching Power Supply Compensation FMCA......................................26411.16 Sallen and Key Band-Pass Filter (BPF) Circuit .......................................26511.17 Sallen and Key BPF MCA........................................................................266

11.17.1 Sallen and Key BPF MCA with both Common and Precision Tolerances ...................................................................267

11.18 Sallen and Key BPF EVA.........................................................................26811.19 Sallen and Key BPF FMCA .....................................................................27011.20 State Variable Filter Circuit .....................................................................27111.21 State Variable Filter MCA ........................................................................272

7028_C000.fm Page xiv Thursday, January 19, 2006 11:05 AM

11.22 State Variable Filter EVA..........................................................................27311.23 State Variable Filter FMCA and MCA Combined...................................27511.24 High-Q Hum Notch Filter Circuit ...........................................................27611.25 High-Q Hum Notch Filter MCA ..............................................................27811.26 High-Q Hum Notch Filter EVA................................................................27911.27 High-Q Hum Notch Filter FMCA ............................................................28011.28 LTC 1562 MCA ........................................................................................28111.29 LTC 1562 EVA..........................................................................................282References..............................................................................................................284

Chapter 12 Transient Tolerance Analysis

........................................................285

12.1 Transient MCA Twin-T RC Network ...................................................28512.2 Transient MCA Multiple Feedback BPF ...............................................28612.3 AC and Transient MCA Bessel HPF .....................................................28812.4 Transient MCA State Variable Filter......................................................291

Chapter 13 Three-Phase Circuits

....................................................................295

13.1 Three-Phase Y-Connected Unbalanced Load MCA....................................29513.2 Three-Phase Y-Connected Unbalanced Load EVA .....................................29713.3 Three-Phase Y-Connected Unbalanced Load FMCA..................................300

Chapter 14 Miscellaneous Topics

......................................................................303

14.1 Components Nominally Zero.......................................................................30314.2 Tolerance Analysis of Opamp Offsets .........................................................30514.3 Best-Fit Resistor Ratios ...............................................................................30914.4 Truncated Gaussian Distribution .................................................................31114.5 LTC1060 Switched Capacitor Filter ............................................................313

14.5.1 Design Procedure from the Data Sheet ...........................................313

Appendix II

...........................................................................................................319Summary of Tolerance Analysis Methods ............................................................319

DC ................................................................................................................319AC.................................................................................................................319Transient .......................................................................................................319

Table of Subprograms............................................................................................320Part I Nominal Analysis Subprograms .......................................................320Part II Tolerance Analysis Subprograms (Used with Part I

Subprograms) ..................................................................................320In Case of Difficulty..............................................................................................320Abbreviations .........................................................................................................321

Index

......................................................................................................................323

7028_C000.fm Page xv Thursday, January 19, 2006 11:05 AM

TO MY WIFE LINDA

Forever and Always

7028_C000.fm Page xvii Thursday, January 19, 2006 11:05 AM

Part I

Nominal Analysis

7028_S001.fm Page 1 Thursday, January 12, 2006 9:16 AM

3

1

Introduction

1.1 NOMINAL ANALYSIS

The features of this analysis are:

Loop or nodal analysis math is not required. It uses SPICE-like node lists. All four types of controlled (dependent) sources can be used. It has DC and AC multiple-input-multiple-output (MIMO) capability.

Maximum number of inputs: 10 Maximum number of outputs: No limit (all circuit nodes)

Transient (time-domain) analysis. Three-phase circuit analysis. DC, AC, three-phase, and transient tolerance analysis methods (discussed

in Part II).

1.1.1 I

NTRODUCTION

Using state space methods, the circuit DC, AC, and transient response can all beobtained from the same initial analysis. Hence, there is an economy of effort thatmakes it worthwhile to learn state space techniques. However, conventional statespace methods require an inordinate amount of circuit analysis algebra. This bookshows a SPICE-like method for creating state space arrays with minimal effort. Thenumerical transfer function can also be a part of the solution using Leverriersalgorithm.

Hence, this method eliminates the algebra required for conventional circuitanalysis techniques as taught in some undergraduate electrical engineering curricu-lums. The simple procedure entails creating node lists directly from the schematic,very much similar to early commercial versions of SPICE. This original method iscalled

node

list DC superposition

(NDS).The purpose of presenting this material in Part I is to provide easy SPICE-like

analysis methods for the working engineer if SPICE is not available owing to networkdowntime, network queuing (owing to limited site licenses), or, as sometimes hap-pens in smaller companies, simply has not been purchased.

Circuits of at least medium complexity can be simulated. (See Section 3.15 fora circuit with a component count of 68.)

The primary goal, however, is to demonstrate correct tolerance analysis methods(Part II). The prerequisite nominal circuit analysis NDS method along with numerousexamples is covered in Part I.

7028_C001.fm Page 3 Thursday, January 12, 2006 9:17 AM

4

Node List Tolerance Analysis: Enhancing SPICE Capabilities with Mathcad

1.1.2 T

HE

NDS M

ETHOD

OF

N

OMINAL

C

IRCUIT

A

NALYSIS

It is assumed that electrical engineers are somewhat familiar with matrix analysisand state space methods; hence, the introductory material is not extensive. Familiaritywith these subjects and Mathcad is necessary.

As previously stated, a big advantage of state space analysis is that the DCoutput, AC frequency response, transient response, and circuit transfer function(using Leverriers algorithm) can all be obtained from one initial analysis.

Another advantage is that state space matrices or arrays are real, not complex.Complex matrices obtained from loop or nodal analysis require a real array twice thesize of a complex array to obtain a solution. Hence, state space methods decreaseexecution time for large arrays and increase solution accuracy. This becomes apparentwhen it is recalled that the number of arithmetic operations required to find a deter-minant is directly proportional to N!, where N is the dimension of the square array.

The matrix equations used in state space analysis are

where A, B, D, E, and G are arrays; x, a column vector of the state variables; u, acolumn vector of inputs; and y, the output. In most analyses, array G is a null (zero)array. (For an example using the G array, see Section 12.3.) Taking the Laplacetransform of the first equation and substituting in the second gives the followingwith G = 0:

y = D(sI A)

1

Bu + Eu

where I is an identity matrix. In the NDS method, the input u is included

in B andE so that

y = D(sI A)

1

B + E

The state variables are the capacitor voltages and inductor currents. Using Nas the order of the circuit (number of Ls and/or Cs), M as the number of inputs,and K as the number of outputs, the arrays have the following dimensions (in {rowcolumn} format):

Array Rows Columns

A N NB N MD K NE K MG K Nx N 1u M 1I N N

dxdt

Ax Bu y Dx Eu G dxdt

= + = + +,


Introduction

5

Using dimensional notation, {row col}, y is {K N}{N N}{N M} + {K M} ={K M}. Then, y is a transfer matrix with the dimensions {K M} or {output input}

Note that in multiplying matrices, the inner dimensions in {row col} order mustbe the same. That is, if A is {N N} and B is {N M}, they cannot be multiplied asBA because {N M}{N N}, the inner dimensions, do not match. But they can bemultiplied as AB = {N N}{N M}. The dimension of the product is the outsidedimensions of both, i.e., {N M}. Hence, the dimension of the product {K N}{NN}{N M} is {K M}, which can be added to E = {K M} (The two arrays are thensaid to be conformable for multiplication if the inner dimensions are the same,and they are conformable for addition if the dimensions are equal.)

1.1.3 G

ENERAL

G

UIDELINES

The SPICE node list text format is

Ref Desig

From node To nodeComponent value

. An example would be

R3 6 9 10K

. The node lists usedin the NDS method are arrays of the form

[From node To node Ref Desig]

,

the component value having been specified prior to node list creation.Node numbering must start with 1 and be in numerical sequence up to 89. Nodes

99, 98, , 91, 90 are reserved for inputs, and node 0 is for ground. There is norequirement for the resistor node list as to node sequence. That is,

[4 5 R1]

and

[5 4 R1]

are both accepted. For the capacitor node list and the inductor nodelist, however, the sequence must correspond to Kirchoffs current law (KCL): currentflow from left to right and from top to bottom. Hence,

[3 6 C1]

will work, but

[6 3 C1]

may give the wrong phase angle output and incorrect output polarityin DC and transient analyses.

The open loop gain of opamps is set at 10

6

V/V or 120 dab. In the majority ofcircuit examples, no opamp frequency rolloff is used. However an example is givenon how to create an opamp with rolloff using voltage-controlled voltage sources(VCVSs) (see Section 3.7 and Section 3.8). The Mathcad file in Section 3.18demonstrates how to embed the opamp rolloff models into circuits, much likesubcircuits in SPICE.

Component values should generally be kept within the bounds of 1E+12 and1E12. Numbers outside this range run the risk of excessively increasing the Amatrix condition number. This will cause solution accuracy to diminish. A guidelinethat can be used is the number of decimal places of accuracy, which is 15 log10

(condition number). If a solution appears incorrect or unreasonable, the conditionnumber of matrix A

should be checked using the Mathcad statement

floor(15-log(conde(A)))

.

The reference paths for the subprogram files are localized for the authorscomputer. In creating new files, the user must click on

Insert

, then on

Reference

,

and then enter the correct local path or go to

Browse

.

Two of the most important Mathcad subprogram files are named as follows:

For DC:

dccomm42.mcd

(creates A1 and B2 arrays)For AC:

comm42.mcd

(creates A, B, D, and E arrays)


6


All of the necessary Mathcad subprograms are contained in the included CD.There is no error trapping. Users must ensure that the node lists correctly representthe circuit being analyzed and that all required input arrays are included.

The version of the software used is Mathcad 11.0. (Note that due to internalbugs in Mathcad 8.0, some files will not run on that version. Intermediate versionshave not been tested.)

Some mathematical ability will be helpful for some advanced subjects such asthe theory of the NDS method (Appendix I), stability analysis, Leverriers algorithm,and transient analysis.

1.2 INTRODUCTION TO NODE LIST CIRCUIT ANALYSIS

The passive RCL circuit used to demonstrate the procedure is shown in the followingfigure:

1.2.1 R

ULES

AND

D

EFINITIONS

Calculated using the Mathcad subprogram file comm42.mcd:Ncap = number of capacitorsNind = number of inductorsN = Ncap + NindM = number of independent inputs (= 1 here, but can be up to 10)K = number of outputs (= 1, but can be up to U)

User input:U = number of unknown nodes (= 3 here).Y = output node (can be any or all of the three nodes V1, V2, or V3).Number nodes sequentially from 1 to U (V1, V2, V3,); 0 is ground.

Maximum value of U = 89.

Independent voltage input nodes are numbered from 99, 98, , 90. (Note thatif only one input source is present, use 99 as the node number; if two inputs, use99, 98; if three inputs, use 99, 98, 97, etc.)

Component reference designator sequence is optional. It can be R1, L2, Ra, Cx,R301, etc. A sequential numbering has been used for convenience.

R1

R4

R2

R3

L3

L4

C1

C2

V2 V3V1Ein


Introduction

7

For AC analysis, log frequency sweep:BF = Beginning log frequency = 10

BF

HzND = Number of decades from BFPD = Points per decadeTotal number of frequency points NP = NDPD + 1

Linear frequency sweepBF = Beginning frequency in HzLF = Last frequency in HzDF = Frequency increment

Total number of frequency points

Using the RCL circuit, creating the node lists is just as easy as in early versionsof SPICE. For the resistors, we create the array RR:

The first column is one of the two nodes that the resistor is connected to, whereasthe second column is the other node. The last column is the reference designatorfor the resistor, the value of which has been given previously.

For the capacitors, we create the array CC:

For the inductors, we similarly create the array LL:

The inputs are listed in the array Ein as Ein = (99 1). The first number indicatesthe node and the second, the amplitude in volts, which is usually set to 1. Allindependent inputs are referenced to ground.

Because this circuit is passive with no controlled sources, this must be shownfor VCVSs as EE = 0. No Voltage-Controlled-Current (VCCS) is shown as GG = 0.

NP LF BFDF

= +1

RR

RRRR

=

99 1 11 2 42 3 23 0 3

CCCC

=

1 2 13 0 2

LLLL

=

1 2 33 0 4


8


REFERENCES

1. Seminal information for the method was obtained from DeRusso, P.M., Roy, R.J.,and Close, C.M.,

State Variables for Engineers

, John Wiley, NY, 1965.


9

2

Passive Circuits

2.1 INTRODUCTION TO NODE LIST CIRCUIT ANALYSIS (PART ONE)

Analysis with output plots.Unit suffixes:

K := 10

3

u := 10

6

m := 10

3

Component values:

R1 := 10 R2 := 100 R3 := 50K R4 := 10KC1 := 0.1u C2 := C1 f1 := 10K f2 := 100K

f1 and f2 are resonant frequencies for the values of L3 and L4.Calculate L3 and L4:

The eight inputs required for the subprogram

comm42.mcd

are: U, Y, EE, GG,RR, CC, LL, and Ein (see previous definitions).

U := 3 Three unknown nodes.Y := 3 Take the output from node 3, V3.

R1

R4

R2

R3

L3

L4

C1

C2

V2 V3 V1 Ein

Lf C

Lf C

3 12 1 1

4 12 2 22 2

: := ( ) = ( )


10


Set up node list arrays: Ein := (99 1) (Ein = 1 V at node 99)

EE := 0 (No VCVSs) GG := 0 (No VCCSs)

Insert reference for subprogram file comm42 to get state space arrays A, B, D,and E:

Reference:C:\mcadckts\CaNL11\comm42.mcd

Display arrays:

DC Analysis

In = Ax + B, the DC value is obtained by setting = 0. Then AX =

B and

X =

A

1

B where the uppercase X is used for DC. Mathcads lsolve functionprovides the solution. When B has more than one column, the explicit solution formX =

A

1

B must be used.

That is, I

L3

= I

L4

= 9.091 mA. The capacitors are short-circuited by the inductor.

RR

RRRR

CCC

: :=

=

99 1 11 2 42 3 23 0 3

1 2 13 0 CC

LLLL2

1 2 33 0 4

=

:

A =

91909 09 90909 09 1 10 090909 09 91109

7. .

. .009 0 1 10394 78 0 0 0

0 39478 42 0 0

7

..

B ==

= ( )=

90909 0990909 09

00

0 1 0 0

0

.

.

D

E (( )

dxdt

dxdt

X solve A B

V V I I

X

C C L L

T

: ( , )

. .

=

= (

1

0 0 9 091 9 091

1 2 3 4

))m


Passive Circuits

11

DC output voltage at node Y: Y = 3 Vodc := DX + E Vodc = (0)DC node voltages (inductors open-circuited) Vdc := 1solve(A11, A14)Vdc

T

= (1 0.833 0.832)

Confirming the last entry in vector Vdc:

AC Analysis

BF := 3 ND := 3 PD := 40 NP := NDPD + 1 i := 1..NP

L

i

:= BF + s := 2

10

L

cv

i

:= D(s

i

I A)

1

B + E

Vo

i

:= db(cv

i

) Va

i

:= arg(cv

i

)Note the two resonant frequency cusps at f1 and f2.

Ein RR R R R

1 2 31 2 3 4

0 832, .+ + +

=

iPD 1

1

180

3 3.5 4 4.5 5 5.5 680

40

20

0Y = 3

Output magnitude at node Y

Log freq(Hz)

60

dBV Voi

Li

3 3.5 4 4.5 5 5.5 6906030

0306090

120150180

Phase angle at node Y

Log freq(Hz)

Degr

ees

(Vai)1

Li


12


Now take the output from both nodes 2 (V2) and 3 (V3):

Call the subprogram comm42 again to get the new D and E arrays.


Note that only D and E have changed.Sample of cv (complex value) for one output: cv

10

= (0.001 + 0.002i)Dimension = {K M} = {1 1}Get the new AC outputs and plot: cv

i

= D(s

i

I A)

1

B + E

Sample of cv for two outputs:

Dimension = {K M} = {2 1}Plot both:

Y :=

23

A =

91909 091 90909 091 1 10 090909 091 911

7. .

. 009 091 0 1 10394 784 0 0 0

0 39478 418 0 0

7.

.

.

=

=

B

D

90909 09190909 091

00

.

.

00 909 0 091 0 00 1 0 0

0 9090

. .

.

=

E

cvii10

0 855 0 2130 001 0 002

=

+

. .

. .

Vo db cv

Vo db cv

i i

i i

2

3

1

2

:

:

= ( ) = ( )


Passive Circuits

13

We can plot the ratio of V3 to V2 as follows:

3 3.5 4 4.5 5 5.5 6

Y = ( )

60

80

40

20

0

V2V3

Output magnitude at node Y

Log freq(Hz)

dBV Vo2i

Vo3i

Li

23

Vo dbcv

cvVai

i

ii32 32

18021

: : ar=( )( )

= gg

cv

cv

i

i

( )( )

2

1

3 3.5 4 4.5 5 5.5 680

60

40

20

0Magnitude of V3/V2

Log freq(Hz)

dBV Vo32i

Li

3 3.5 4 4.5 5 5.5 6180

120

60

0

60

120

180Phase of V3/V2

Log freq(Hz)

Deg Va32i

Li


14


Introduction to NDS Method

SPICE Verification

VEin 99 0 AC 1

R1 99 1 10

R4 1 2 10K

R2 2 3 100

R3 3 0 50K

*

C1 1 2 0.1u

C2 3 0 0.1u

*

L3 1 2 2.533m

L4 3 0 25.33u

*

.PRINT AC V(2) V(3) VP(3) V(3,2) VP(3,2)

.AC DEC 50 1E3 1E6

.OPTIONS NOMOD NOECHO NOPAGE

.END

Extracting the data from the SPICE *.out file and plotting:Fnom := READPRN(c:\SPICEapps\datfiles\intro3.txt) N := rows(Fnom)N = 151 k := 1..N

3 3.5 4 4.5 5 5.5 680

60

40

20

0

V2V3

Spice verication - magnitude

dBV db(Fnomk,2)

db(Fnomk,3)

log(Fnomk,1)Log freq(Hz)


Passive Circuits

15

For further verification, we compare the accuracy of the A and B arrays obtainedfrom the NDS method to that obtained from the algebraic solution in Section 2.2.Ax and Bx, shown in the following, are from that section.

3 3.5 4 4.5 5 5.5 6906030

0306090

120150180

Spice verication - phase angle

Deg Fnomk,4


Ax

C R R R C R R C

:=

++

+( )

11

14

11 2

11 1 2

11

0

112 1 2

12

11 2

13

0 12

13

0 0

C R R C R R R C

L

+( )

++

00

0 14

0 0L

Ax =

91909 09 90909 09 1 10 090909 09 91109

7. .

. ..

.

.

09 0 1 10394 78 0 0 0

0 39478 42 0 0

7

AA Ax =

0 0 0 00 0 0 00 0 0 00 0 0 0


16


2.2 INTRODUCTION TO NODE LIST CIRCUIT ANALYSIS (PART TWO)

K := 10

3

u := 10

6

The algebraic solution of a sample RCL circuit is given to show the amount oflabor saved using the NDS method. For those less mathematically inclined, the nextthree pages can be skipped. The advantages of the NDS method can be seen just byglancing at the amount of circuit analysis algebra given in the following:

R1 := 10 R2 := 100 R3 := 50KR4 := 10K C1 := 0.1u C2 := C1fl := 10K f2 := 100K

Format goal:

e

L

and i

C

on LH side; Ein, i

L

, and v

C

on RH side. Must only useterms involving these unknowns. We thus need N = Ncap + Nind = 4 equations inthe following format including constant coefficients.

f(e

L

, i

C

) = g(i

L

, v

C

, Ein) in whichWe first see that

e

L3

= v

C1

e

L4

= v

C2

(1)

Bx

C R R

C R R:=

+( ) +( )

11 1 2

12 1 2

00

=

=Bx B Bx

90909 0990909 09

00

0.. 00

00

R1

R4

R2

R3

L3

L4

C1

C2

V2 V3 V1 Ein

Lf C

Lf C

3 12 1 1

4 12 2 22 2

: := ( ) = ( )

e L didt

i C dvdtL

LC

C= =


Passive Circuits

17

which are in the correct format. Two more equations are needed.

KCL at node V1:

(2)

Substituting:

(3)

Not done yet; need to eliminate V1.

KCL at node V2:

We see that: V3 = v

C2

Substituting and rearranging:

(4)

Solving Equation 4 for V2:

(5)

V1 = v

C1

+ V2 From Equation 2 (6)

Substituting Equation 5 into Equation 6

Collecting terms:

(7)

Substituting Equation 7 into Equation 3:

Ein VR

i i V VR

V V vL C C

= + +

=

11

1 24

1 23 1 1

Ein VR

i i vR

i EinR

i vR

VL C

CC L

C= + + =

11 4 1 43 1

11 3

1 111R

i i vR

V VRL C

C3 1

1

42 3

2+ + =

VR

v

Rv

Ri iC C C L

22 2 4

02 1 1 3 =

V i R v v RR

i RL C C C2 22

423 2 1 1= + +

+

V v i R v v RR

i RC L C C C1 22

421 3 2 1 1= + + +

+

V v RR

v i R i RC C L C1 124

2 21 2 3 1= +

+ + +


18


Collecting terms:

(8)

From Equation 2: V2 = V1

v

C1

Repeating Equation 5:

KCL at node V3:

Substituting V3 = v

C2

Multiplying by 1:

Substituting Equation 5:

Rearranging to the correct format:

or finally

i EinR

i vR

v

RRR

v

RC LC C C

1 31 1 2

1 4 11 2

4= +

11

21

21

3 1

i RR

i RR

L C

i RR

EinR

i RR

vC L

C1 3

21 21 1

1 21

+

= +

RR v R R

RR RC1

11

14

21 41

+ +

V i R v v RR

i RL C C C2 22

423 2 1 1= + +

+

V VR

VR

iC iL2 32

33

2 4 = + +

+ +

+ + =

VR

vR R

i iC C L2

212

13

02 2 4

VR

vR R

i iC C L22

12

13

02 2 4 +

=

i vR

v

Ri v

R Ri iL C C C C C3 2 1 1 2 22 4

12

13

+ + + +

LL4 0=

i i i vR

v

Rv

R RC C LC C

C1 2 32 1

22 412

13

= + +

+ iiL4


Passive Circuits

19

(9)

Create two {N N} arrays W and Q from Equation 1, Equation 8, and Equation9. Fill in the coefficients from the LH sides for W, and for the RH sides for Q perthe column headings:

S is created from the only Ein term in the third equation: P is an {N N} diagonalarray in the same C and L order as W and Q.

Now form A and B as follows: C:= (WP)

1

A := CQ B := CS

i i i vR

v

RiC C L C C L1 2 3 2 1 42 4

= + +

i i e e

W RR

C C L L1 2 3 4

0 0 1 00 0 0 1

1 21

0 0 0

1 1 0 0

:=+

v v i i

QR R

RR R

C C L L1 2 3 4

1 0 0 00 1 0 0

11

14

21 4

:= + +

+

11

1 21

0

14

13

1 1

RRR

R R

SR

P

CC

L: :=

=

0011

0

1 0 0 00 2 0 00 0 3 00 0 00 4L

A =

91909 091 90909 091 1 10 090909 091 911

7. .

. 009 091 3 492 10 1 10394 784 0 0 0

0 39478 41

10 7. .

.

.

88 0 0

90909 09190909 091

00

=

B.

.


20


Because the output is v

C2

, we place a 1 in the second column of the {K N} array

Because there are no input terms Ein in the output: E := 0Prior to this shortcut method [*], the algebra would have to continue as follows.

Isolating iC1 in Equation 8:

(10)

Because , we get

(11)

From Equation 9:

(12)

Substituting Equation 10 into Equation 12:

Again, because

(13)

From Equation 1 above, repeated here: e

L3

= v

C1

e

L4

= v

C2

v v i i

D

C C L L1 2 3 4

0 1 0 0:= ( )

i EinR R

i vR R

vR R RC L

CC1 3

211 2 1 2

14

11 2

=

+

+ +

+

i C dvdtC

C1

11=

dvdt

v

C R R Rv

C R RC C C1 1 2

114

11 2 1 1 2

=

++

+( )) + +( )

iC

EinC R R

L3

1 1 1 2

i i i vR

v

RiC L L C C C2 3 4 1 2 14 3

= + +

i i i vR

v

Ri v

R Rv

RC L LC C

LC

C2 3 41 2

32

14 3 1 21

= + +

441

1 2 1 2+

+

+ +R R

EinR R

i vR R

vR R R

i EinRC

CC L2

12 41 2

11 2

13

=

+

++

+

11 2+ R

i C dvdtC

C2

22=

dvdt

v

C R Rv

C R R RC C C2 1 2

2 1 2 21

1 213

=

+( ) + +

+ +( )

iC

EinC R R

L4

2 2 1 2


Passive Circuits 21

(14)

Similarly:

(15)

Using Equation 11, Equation13, Equation14, and Equation15, the general form

matrix equation = Ax + Bu becomes

2.3 ALL-CAPACITIVE CIRCUIT

u := 106

e L didt

didt

v

LLL L C

33 3 13

3= =,

didt

v

LL C4 2

4=

dxdt

dvdt

dvdt

didt

didt

C

C

L

L

1

2

3

4

=

++

+( )1

114

11 2

11 1 2

11

0C R R R C R R C

+( )

++

12 1 2

12

11 2

13

0 12

13

0

C R R C R R R C

L00 0

0 14

0 0

1

2

3

L

v

v

i

C

C

L

ii

C R R

C R R

L4

11 1 2

12 1 2

00

+

+( ) +( )

Ein

3

2 1

R2

R1

R3

C1

C2

Ein


22 Node List Tolerance Analysis: Enhancing SPICE Capabilities with Mathcad

R1 := 10 R2 := 100 R3 := 50 C1 := 0.1u C2 := 0.5uU := 3 Y := 2 Ein := (99 1) Input 1 V at node 99.

LL := 0 (No induc-

tors)EE := 0 GG := 0 (No controlled sources.)

Get A, B, D, and E arrays from subprogram comm42.mcd:


DC voltages at all U nodes in the order given by Vdc. If inductors are present,they are open-circuited:

Vdc := lsolve(A11, A14) VdcT = (1 1 0)

X := lsolve(A,B)

Vodc := DX + E Vodc = (1) DC output voltage at node Y given by Vodc.Y = 2

AC Analysis

BF := 3 ND := 3 PD := 40

i := 1..NDPD + 1 Li := BF + s := 210L

cvi := D(siI A)1B + E Voli := db(cvi)

Vai := arg(cvi)1(Phase angle) Y = 2

RRRRR

:=

99 1 11 2 33 0 2

CCCC

:=

1 2 12 3 2

A

B

=

=

290909 1 90909 118181 8 18181 8

. .

. .

990909 118181 8

0 909 0 091

0 909

.

.

. .

.

= ( )=

D

E (( )

X =

01

iPD 1

1

180


Passive Circuits 23

2.4 ALL-INDUCTIVE CIRCUIT

u := 106 mA := 103

R1 := 10 R2 := 100 R3 := 50 L1 := 220u L2 := 330uU := 3 Y := 2 Ein := (99 1)

CC := 0 (No capacitors)EE := 0 GG := 0 (No controlled sources.)


3 4 5 64

3

2

1

0Magnitude at node Y

Log freq (Hz)

dBV Vo1i

Li3 4 5 6

Log freq (Hz)Li

20

10

0

10Phase at node Y

Degr

ees

Vai

3

2 1

R2

R1

R3

L1

L2

Ein

RRRRR

:=

99 1 13 0 21 2 3

LLLL

:=

1 2 12 3 2



Vdc := lsolve(A11, A14) VdcT = (1 1 0) X := lsolve(A, B)

Vodc := DX + E Vodc = (0.909)

AC Analysis

BF := 3 ND := 3 PD := 50

NP := NDPD + 1 i := 1..NP Li := BF +

s := 210L cvi := D(siI A)1B + E Voli := db(cvi)

Vai := arg(cvi)1 Y = 2

2.5 TWIN-T RC NETWORK

60-Hz Notch Filter K :=103 u := 106 Meg := 106 m := 103

A =

2287272 7 227272 7151515 2 484848 5

. .

. .

BB

D

E

=

= ( )= ( )

03030 3

50 60

1

.

XmA

iLiL

=

9 0919 091

1

2

.

.

iPD 1

1180

3 4 5 63

2

1

0Amplitude at node Y

Log freq (Hz)

dBV Vo1i

Li3 4 5 6

Log freq (Hz)Li

10

5

0

5

10Phase at node Y

Degr

ees

Vai


Passive Circuits 25

R1 := 267K R2 := 267K R3 := 133K R5 := 10MegR4 := 0.01 C1 := 0.02u C2 := 0.01u C3 := 0.01uU := 4 Y :=3 Ein := (99 1)

Resistor R4 is the output impedance of the external voltage source.


DC Analysis

X := lsolve(A, B) Vodc := DX + E

Vodc = (0.949)

(Checks; same as Vodc.)DC node voltages: Vdc := lsolve(A11, A14)

Note: The reader is encouraged to reverse 3 1 C3 to 1 3 C3 in the CC array andnote the polarity change of VC3 above. Sign changes in the D array cancel the VC3sign change and the output Vodc polarity remains the same. In SPICE the statevariables X and the A, B, D, E arrays are not accessible. As will be seen later, accessto these arrays can be useful.

R4 R1

R5

R2

R3

C2

C1

C3

V2 V3 V4

V1

Ein

RR

RRRRR

:=

4 2 12 3 23 0 51 0 399 4 4

CCCCC

GGLLEE

:

:

:

:

=

=

=

=

2 0 14 1 23 1 3

000

XVVV

C

C

C

=

0 9751

0 949

1

2

3

.

.

Ein RR R R R

1 2 54 1 2 5

0 949, .+ + +

=

V V V V

VdcT1 2 3 4

0 0 975 0 049 1= ( ). .



AC Analysis

BF := 0 LF := 100 NP := 100 (Linear frequency sweep)

i := 1..NP + 1 Fi := BF + DF(i 1)

DF = 1 s := 2F cvi := D(siI A)1B + E

Voli := db(cvi) Vai := arg(cvi)Note: Most math software and scientific calculators limit phase angles of com-

plex numbers to +/ 180 deg, or + to . SPICE phase angle outputs can be from0 to + 360 (2 ) or 360 deg. For example, +300 deg is equivalent to 60 deg; 200deg is equivalent to +160. Both are correct.

Output plots

Y = 3

DF LF BFNP

:=

1180

0 10 20 30 40 50 60 70 80 90 10060

40

20


Freq(Hz)

dBV Voi

Fi

0 10 20 30 40 50 60 70 80 90 100100

50

0

50

100Phase at node Y

Freq(Hz)

Deg (Vai)1

Fi


Passive Circuits 27

2.6 BROADBAND PULSE TRANSFORMER MODEL

K := 103 p := 1012 u := 106 n := 109 m := 103

R1 := 10 R2 := 1.5 R3 := 20K R4 := 1.5 R5 := 1KR6 := 0.5 C1 := 20p C2 := 5p C3 := 20p L1 := 1uL2 := 2m L3 := 1u R7 := 1

U := 7 Y := 5 Ein := (99 10) 10 Vac input.

L1 and L3 represent leakage inductance; L2 is the magnetizing inductance.

Insert subprogram file:


R1 R2 R4

R6

2 1 3 4 5

R5 R7 R3

L3 L1

L2 7

6

C1 C3

C2

Ein

RR

RRRRRRR

:=

99 1 11 2 23 0 33 4 45 0 51 6 63 7 7

=

=

CCCCC

LL

:

:

1 0 16 5 25 0 3

22 3 17 0 24 5 3

0

0

LLL

EE

GG

=

=

:

:



DC Analysis

X := lsolve(A,B)

Vodc := DX + E Vodc = (0.798)

Note that this DC analysis is certainly easier than deriving the following alge-braic solution:

DC node voltages (inductors open-circuited):

Vdc := lsolve(A11, A14) VdcT = (10 10 0 0 0 10 0)

AC Analysis

BF := 2 ND := 6 PD := 30

i := 1..NDPD +1 Li := BF + s := 210L

cvi := D(siI A)1B + E rd := Voi := db(cvi) Vai := rdarg(cvi)Note flat response from about 1 KHz to 10 MHz.

X V V V I I I

X

C C C L L L

T

Format: 1 2 3 1 2 3

1 999 1 201 0= . , .7798 0 8 0 799 7 98 10 4. . . ( )

Vdc Ein R

R RR R R R

R R R

5 5

1 1 24 5 3 7

3 7 4

1 2:

,

=

++

+( ) + ++( ) +( )

+( )

=

R R R

R R

Vdc

5 3 7

4 5

5 0 79. 88

iPD 1

1

180

2 3 4 5 6 7 840

20

0

20

40Output amplitude at node Y

Log freq(Hz)

dBV Voi

Li


Passive Circuits 29

Broadband Pulse Transformer SPICE Verification

*File: c:\SPICEapps\Cirtext\xformer.cir

VEin 99 0 AC 10

R1 99 1 10

R2 1 2 1.5

R3 3 0 20K

R4 3 4 1.5

R5 5 0 1K

R6 1 6 0.5

R7 3 7 1

*

C1 1 0 20p

C2 6 5 5p

C3 5 0 20p

*

L1 2 3 1u

L2 7 0 2m

L3 4 5 1u

*

.AC DEC 20 100 1E8

.PRINT AC V(5) VP(5)

2 3 4 5 6 7 8200150100

500

50100150200

Phase at node Y

Log freq(Hz)

Degr

ees

(Vai)1

Li



.OPTIONS NOMOD NOPAGE NOECHO

.END

Extracting the data from the SPICE *.out file:Fnom := READPRN(c:\SPICEapps\datfiles\xformer.txt)N := rows(Fnom) N = 121 k := 1..N

2.7 ALL-CAPACITIVE LOOPS (ACL)

In a physical circuit, two or more capacitors in parallel can occur, such as in powersupply decoupling circuits. However, in converting capacitors to ideal independentvoltage sources (which is done using this method of analysis), we end up with aviolation of Kirchoffs laws. For example, in the circuit that follows:

2 3 4 5 6 7 840

20

0

20

40Output amplitude at node Y

dBV db(Fnomk,2)


2 3 4 5 6 7 8200150100

500

50100150200

Phase at node Y

Degr

ees

Fnomk,3


C1 C2 C3 E1

+

+

+ E2 E3


Passive Circuits 31

If we assign arbitrary values to E1, E2, and E3, Kirchoffs Voltage Law (KVL)is violated around any of the three possible loops. If we assign the value of +1 Vto all three, because the resistance is zero, infinite current will flow around the loopsunless all assigned values of 1.0 have an infinite number of zeros after the decimalpoint, e.g., if E1 E2 = 109000 V divided by zero resistance is infinite current.

Another example of an ACL is:

When converted to ideal voltage sources, KVL is again violated. For example,if the arbitrary values were C1 = E1 = 10 V, C2 = E2 = 7 V, and C3 = E3 = 20 V,KVL yields 10 + 7 + 20 = +17 V 0.

Every real-world capacitor has a small amount of series resistance, termedequivalent series resistance (ESR). The cure in state space analysis of circuits withACLs is to place a small ESR resistor ( 0.01 ) in series with all (or all but one)of the capacitors.

2.8 ALL-INDUCTIVE CUTSETS (ICS)

A similar problem occurs with circuits having two or more inductors connected tothe same node. In this analysis method, the inductors become ideal current sourcesconnected to the same node, and we end up with a violation of Kirchoff's CurrentLaw (KCL), as shown in the following:

Kirchoffs Current Law at node V1 is I1 + I2 = I3. This law is violated regardlessof the values of I1, I2, and I3. The term cut set comes from circuit topology. If wewere to place a small cookie cutter at node V1, it would cut the wires of all threeinductors. Thus, we are cutting a set of inductor wires.

C3

C2

C1

E1

+

+

+ E2 E3

R1 R3

The c

ure

R2

L1

L2 L3

I1

I2 I3V1 V1

+

+ +



The cure is to place de-Qing resistors in parallel with at least one of theinductors as shown in the following. The values to be used will depend on theremainder of the circuit and the desired L/R time constants.

In defense of the NDS method, it should be stated that ACLs and/or ICSs willcause any state space analysis method to fail if additional corrective steps are nottaken. See, for example, Intermediate Network Analysis, Shlomo Karni, Allyn &Bacon, 1971.

2.9 ALL-CAPACITIVE LOOP EXAMPLE

K := 103 u := 106 m := 103 KHz := 103

R1 := 1K R2 := 0.1 R3 := 100C1 := 1u C2 := C1 C3 := C1 L3 := 25.33mU := 3 Y := 3 Ein := (99 1)GG := 0 EE := 0 LL := (3 0 L3)

R3The cure

R1

R2 V

I2 I3

I1+

+ +

L3

C2

C3 V1 V2

V3

R1

R3 Ein

C1

RRRR

CCCCC

:

:

=

=

99 1 12 3 3

1 0 11 2 32 0 2


Passive Circuits 33

Call reference subprogram:


A, B, D, and E are not returned. Due to the ACL, A is singular, i.e., thedeterminant of A is zero, and the inverse of A is undefined.

Insert R2 to break ACL.

U := 4 Y := 4 LL := (4 0 L3)

Reinsert subprogram for new node lists.


AC Analysis

BF := 2 ND := 2 PD := 50

i := 1..NDPD + 1 Li := BF + s := 210L

cvi := D(siI A)1B + E Voi := db(cvi)

L4

C2

C3 V1V2

V3

V4

R1 R2

R3Ein

C1

RRRRR

CCCCC

:

:

=

=

99 1 11 2 23 4 3

1 0 12 3 33 0 2

iPD 1

1



Y = 4

REFERENCES

1. R. Boyd, State Space Averaging with a Pocket Calculator, High Frequency PowerConversion Conference Proceedings, Santa Clara, CA, 1990, p. 283.

2 2.5 3 3.5 450

40

30

20Output at node Y

Log freq(Hz)

dBV Voi

Li


35

3

Controlled Sources

3.1 CONTROLLED (DEPENDENT) SOURCES

3.1.1 V

OLTAGE

-C

ONTROLLED

C

URRENT

S

OURCE

(VCCS)

SPICE convention:

Gname Vp Vn Vcp Vcn Transconductance

The units of transconductance are amperes/volts = 1/ohms = siemens (or mhos,for you old-timers).

Vp and Vn are the node connections of the current source in the circuit. Currentflows away from node Vp (into the + terminal of the source) and towards node Vn,going out of the source. Vcp and Vcn are the + and controlling voltage nodes.

This convention is chosen because virtually all models of transistors and MOS-FETs depict the current as flowing down and internally away from the collector ordrain terminal of the device.

Example: MOSFET drain current: Id = gmVgs = gm(Vg Vs)Here Vg and Vs are Vcp and Vcn, respectively. Because Id is dependent by

definition, it is unknown, as usually are Vg and Vs.In MathCAD,

GG = (Vp Vn Vcp Vcn Gain)

For a MOSFET,

GG = (Vp Vn Vg Vs gm)

3.1.2 C

URRENT

-C

ONTROLLED

C

URRENT

S

OURCE

(CCCS)

SPICE convention:

Fname Vp Vn Controlling Current Gain

In the NDS analysis method, the controlling current is specified as I = f(V/R)

Example:

3.1.3 V

OLTAGE

-C

ONTROLLED

V

OLTAGE

S

OURCE

(VCVS)

SPICE convention:

Ename Vp Vn Vcp Vcn Gain

As in VCCS, Vp and Vn are the + and connections of the source in the circuit,and Vcp and Vcn are the + and controlling nodes.

Example: V1 V2 = k(V3 V4), or in SPICE

Ename V1 V2 V3 V4 k

In MathCAD,

EE = (Vp Vn Vcp Vcn Gain) = (V1 V2 V3 V4 k)

For an opamp, which is usually a single-ended output, Vo = Ao(Vcp Vcn),where typically Ao = 10

6

V/V.For an inverter, Vcp = 0. For a voltage follower, Vo is connected to Vcn and

Ic B lb B Ein VR

= =

11


36


and in

MathCAD as

EE = (Vo 0 Vcp Vcn Ao) = (Vo 0 Vcp Vo Ao)

3.1.4 C

URRENT

-C

ONTROLLED

V

OLTAGE

S

OURCE

(CCVS)

SPICE convention:

Hname +V V Controlling CurrentTransresistance

The units of transresistance are volts/amperes = ohms.Only two types are used in NDS method, the VCVS and the VCCS. Conversions

from the remaining two are easily accomplished as shown in the following subsec-tions.

3.1.5 CCVS

TO

VCVS

To convert a CCVS to a VCVS, divide the controlling current nodes by the resistancein the controlling current branch. (This resistance could be that of a printed circuitboard trace or wire, or a small current-sensing resistor.) Example: Assume thecontrolling current Ic is through a resistor or resistance R2, which is connected tonodes V2 and V1. Then

The gain is thereby converted from a transresistance in dimensions of ohms,to a dimensionless gain.

MathCAD format:

EE = (Vp Vn Vcp Vcn Gain) = (Vh 0 V2 V1Rc/R2),

which is very similar to the SPICE format.

3.1.6 CCCS

TO

VCCS

To convert a CCCS to a VCCS, divide the (dimensionless) gain by the resistance ofthe controlling current. Example:

The controlling voltage is now Ein V1, and the gain, with dimension 1/ohmsor transconductance, is B/R1.

In MathCAD format,

GG = (Vp Vn Vcp Vcn Gain) = (Vp Vn EinV1 B/R1).

Vo AoVcp AoVo Vo Ao AoVcp

Vo AoVcpAo

+ = +( ) =

=+

=

0 1

1

,

VVcp, since Ao1+Ao

1

Vh Rc Ic Rc V VR

RcR

V V Gain Rc= = = ( ) =

2 12 2

2 1 // R2

Ic B lb B Ein VR

BR

Ein V= = = ( )

11 1

1


Controlled Sources

37

To repeat, the first input Ein is given the node number 99. For a second input,Ein2 = 98, Ein3 = 97, etc., down to 90. For example, if Vp = 2, Vn = 1, Vcp = 99,Vcn = 1, then

GG = (2 1 99 1 B/R1)

.

3.1.7 F

OUR

R

ULES

T

HAT

M

UST

B

E

O

BSERVED

1. The output of a controlled source cannot be connected directly to an

independent

input source.That is,

EE = (99 0 2 1 gain)

is not allowed. Input voltagesources are specified, for example, as

Ein = (99 5)

, the inputconnected from node 99 to ground, with an amplitude of +5 V.However,

EE = (2 0 99 1 gain)

, one input being a controllingnode, Vcp or Vcn, is allowed. Here and as earlier, 99 represents any ofthe nodes 99, 98, 97, , etc., down to 90.An independent source can be created by having Vcp = 99, 98, etc., andVcn = 0. For example, assume

Ein = (99 5)

, and it is desired toconnect an independent 15-mA current source at an internal node V2 tonode V7. Then

GG = (2 7 99 0 0.015/5)

For an independent 15 V source at the same nodes:

EE = (2 7 99 0 15/5)

2. Vp in a VCVS is not allowed to be zero. That is, the output nodes of a VCVS must always be (Vp 0) or (Vp Vn).For example,

EE = (0 2 3 0 gain)

is not allowed. If a negativeoutput is desired, use

EE = (2 0 3 0 gain)

or

EE = (2 00 3 gain)

.

3. If a capacitor C or inductor L in the circuit being analyzed is connecteddirectly to an ideal input source, it must have an equivalent series resis-tance (ESR) resistor in series between it and the source. That is

CC =(99 1 C1)

or

LL = (98 2 L1)

are not allowed.This will be a minor inconvenience as every real-world capacitor andinductor has an ESR. Also, every real-world voltage source has some finiteinternal source impedance which includes resistance. Hence, the simula-tion will be more realistic with ESR included. If in doubt about whatvalue of ESR to use, use 0.01

for capacitors and 0.05

for inductors.4. The nodes Vp or Vn of two or more VCVSs (EE) must not be common.

That is

is not allowed. In the NDS method, this results in node contention, andthe solution will not be correct.

As in SPICE, every circuit must have at least one ground node (node 0).

EE =

2 1 12 4 42 0 3 4 2


38


3.2 FLOATING VCVS

K := 10

3

uF := 10

6

m := 10

3

R1 := 1K R2 := 3K R3 := 4K R4 := 2KC1 := 0.01uF C2 := 0.05uF U := 3 Y := 3

u := 20 Gain of VCVS. rd :=

LL := 0 Ein := (99 2) GG := 0

VCVS equation: uV1 = V2 V1 or V2 = V1(1 + u)

Format: EE = (Vp Vn Vcp Vcn gain), then: EE := (2 1 1 0 u)


D = (0 1) E = (0)

DC Analysis

X := lsolve(A, B) X

T

= (0.174 1.217) Vodc := DX + EVodc = (1.217)

DC node voltages:

Vdc := lsolve(A11, A14) Vdc

T

= (0.174 3.652 1.217)

R1 R3V2uV1

V3V1

R4R2C1 C2Ein

+

180

RR

RRRR

CCC

: :=

=

99 1 12 0 22 3 33 0 4

1 0 13 0 CC2

A B=

=

1 325 10 25000105000 15000

2000006.00


Controlled Sources

39

Check VCVS equation:

Vdc

2

Vdc

1

= 3.478 uVdc

1

= 3.478 Checks.

AC Analysis

BF := 2 ND := 5 PD := 20 Lit := NDPD + 1 i :=1..Lit

Li := BF + s := 2

10

L

db(x) := 20log(|x|)cv

i

:= D(s

i

I A)

1

B + E Vo

i

:= db(cv

i

) Va

i

:= rdarg(cv

i

)

Plot marker: M1

:=

db(Vodc) Y = 3

iPD1 1

2 3 4 5 6 780

60

40

20

0


Log freq(Hz)

dBV Voi

M1

Li

2 3 4 5 6 7180

135

90

45

0Phase at node Y

Log freq(Hz)

Deg (Vai)1

Li



SPICE Verification Floating VCVS

*File: c:\Spicapps\Cirtext\vcvs1c.cirVEin 99 0 AC 2R1 99 1 1KC1 1 0 0.01uR2 2 0 3KR3 2 3 4KC2 3 0 0.05uR4 3 0 2K*

EE 2 1 1 0 20; VCVS.AC DEC 20 100 1E7.PRINT AC V(3) VP(3).OPTIONS NOPAGE NOMOD NOECHO

.END

Fnom := READPRN(c:\SPICEapps\datfiles\vcvs1c.txt)N := rows(Fnom) N = 101 k := 1..N

2 3 4 5 6 780

60

40

20

0

20Spice V3 magnitude

Log freq(Hz)

dBV db(Fnomk,2)

log(Fnomk,1)


Controlled Sources 41

3.3 CIRCUITS WITH M > 1

The subprogram that constructs the A, B, D, and E arrays from the node lists alsocounts the number of rows in the Ein array and assigns this value to M. In mostcases, the user is interested in the node voltages with all inputs active. In some cases,however, the separate superposed contribution of each independent input may bedesired. Hence, there are two different subprograms to call, depending on the typeof output desired.

For DC, call dccomm42.mcd if the user wants all inputs active simultaneously.(Most frequently used.)

Call dccomm42m.mcd if the separate contribution of each independent input,M > 1, one at a time, is desired.

For AC, call comm42.mcd for all inputs active, and comm42m.mcd to separatethe node voltages due to the M > 1 inputs.

For a simple example, we use one circuit with M = 3 inputs and U = 3 unknownnodes:

2 3 4 5 6 7180

135

90

45

0Spice V3 phase angle

Log freq(Hz)

Deg Fnomk,3

log(Fnomk,1)

Ein Ein Ein

A

1 2 3

30 1 0 01 00 01 0 2 0 020 0 0

:

. .

. . .

.

=

22 0 3

31 0 00 2 00 0 3

1

.

:

=

B

Ein Eiin Ein

V A B V

2 3

3 3 3 310 05 1 01 0 10 51 10 121:

. . .

. .= = 11 010 03 0 67 10 07

123

.

. . .

VVV



The aforementioned is what is returned if dccomm42m.mcd is called. Theseparate contributions of each column (independent input) in B3 is given.

When this is not desired, calling dccomm42.mcd gives

We could get the same answer by adding the columns of V3, but this requiresadditional statements in the worksheet.

For circuits in which M = 1, i.e., Ein array has one row, it does not matter whichsubprogram is called. This applies only to those circuits with more than one input,where Ein has more than one row and M > 1.

Example DC circuit with M = 2:

K := 103

A30 1 0 01 00 01 0 2 0 020 0 02 0 3

:

. .

. . .

. .

=

=

= =

B

V A B V

1123

1 3 1 111 1611 61

:

:

.

. 4410 78

123.

VVV

i

V V V V V

V

i i i i i

: ..

:

.

, , , ,

=

= + + +

=

1 3

1 3 3 3 3

111 16

1 2 2 3

111 6410 78

.

.

R1V99 V1 V2 V3 V98R3 R4

R7

R8

R2 R5 R6

Ein1 Ein2



GG := 0 EE := 0 U := 3Inputs separate. (M = 2) Reference:C:\mcadckts\CaNL11\dccomm42.mcd

In SPICE, one of two inputs would have to be zeroed, which requires two runsto get the same information as given earlier.

If M = 3, SPICE would require three runs, and so forth.Inputs added. (M = 1) Reference:C:\mcadckts\CaNL11\dccomm42.mcd

Ein

RR

KKK

:

:

=

=

99 1598 5

99 1 11 0 11 2 12 3 1 KK

KKK

K

2 0 103 0 11 3 1 53 98 1

.

RRRRRRRR

12345678

Va A B

Ein Ein

Va

:

. .

.

=

=

1 2

1 2

5 3936 0 64403 4884 1

1

..

. .

16281 9320 1 7979

123

VVV

Vb A B

Vb

V

:

.

.

.

=

=

1 2

4 74962 32560 1342

1

aa Va1 1 1 2 4 7496, , .+ = etc.



3.4 FIRST-ORDER MOSFET MODEL

K := 103 u := 106 n := 109 p := 1012 mA := 103

R1 := 4.99K R2 := 1K R3 := 10K R4 := 4.99KR5 := 1.96K C1 := 0.1u C3 := 4.7n

From MOSFET data sheet:

gm := 0.001 Edd := 200 Eg := 20Nodes: V1 Gate; V3 Source; V4 Drain

Model using VCCS:

C2 := 400p

C2 represents the internal gate-source capacitance.(Nonlinear in higher-order models.)

C3

C1V2

V3

R5V4 V5

R4

R1

Eg

R2

R3

V1 M1

Edd

R1

R2 R5 V5V4

g1+ C3

R4

Edd

C1V2

V3

C2

R3

V1Eg



(VCCS g1 is drain current Id)VCCS: gl = gmVgs = gm(V1 V3)

VCCS format:

GG = (Vp Vn Vcp Vcn gain)GG := (4 3 1 3 gm)Eg = 20 Edd = 200


DC AnalysisVC1 VC2 VC3 DC voltages across C1, C2, and C3

X := A1B XT := (1.82 1.82 190.93)

DC output:

Vodc := DX + E Vodc = (190.93)

DC voltage at all nodes:

Vdc := A111A14 VdcT = (20 20 18.128 190.93 1.82 103)Drain current Id:

Vgs := Vdc1 Vdc3 Vgs = 1.818 Id := gmVgs Id = 1.82mA

RR

RRRRR

C

:=

99 1 11 2 23 0 3

98 4 44 5 5

CCCCC

EinEgEdd

:

:

=

=

2 3 11 3 25 0 3

9998

=

=

=

LL

U

Y

:

:

:

0

5

4



Id := Vdc6 Id = 1.82mA V4 := Edd IdR4 V4 = 190.93= Vodc. Checks.

AC Analysis

BF := 2 ND := 4 PD := 25 Lit := NDPD + 1 i := 1..Lit

Li := BF + s := 210L cvi := D(siI A)1B + E Voi := |cvi|

3.5 VCVS AND CCCS EXAMPLE

K := 103 u := 106 m := 103 mA := 103 n := 109

Hybrid-pi model of the Bipolar Junction Transistor (BJT).

iPD1 1

2 3 4 5

Y = 4

60

50

100

150

200Drain voltage V4

Log freq(Hz)

Volts Voi

Li

R4R2

V2

V3+

+

R5

g1 C2

R1 R3

C1l1

V1 V4Ein



R1 := 100 R2 := 10 R3 := 40K R4 := 2KR5 := 10 C1 := 80n C2 := 5n

Controlled source gains:

hre := 0.004 hie := 100 rd :=

VCVS:

V2 V3 = hre(V1 V4)

Format for EE:

EE = (Vc Vn Vcp Vcn gain)

then

EE := (2 3 1 4 hre)

Convert g1 CCCS to a VCCS.

180

RR

RRRRR

CC

:=

99 1 11 2 21 4 34 0 43 0 5

::

:

: .

:

:

=

=

= ( )=

=

1 4 14 0 2

0

99 0 1

4

4

CC

LL

Ein

U

Y

g hie I I Ein VR

g hieR

Ein V1 1 1 11

11

1= = = ( )




DC Analysis

X := lsolve(A,B) XT = (24.226 24.138) Vodc := DX + EVodc = (24.14) Vdc := lsolve(A11,A14)VdcT = (0.09 0.09 4.79 103 24.14 0.01)Igl := Vdc5 Igl = 12.67mA (Igl = current thru souce gl)

AC Analysis

BF := 1 ND := 7 PD := 20 i := 1..NDPD + 1

Li : = BF + F := 10L s := 2F

Voi := D(siI A)1B + E Vai := rdarg(Voi)

NDS results and SPICE verification:Fnom := READPRN(c:\SPICEapps\datfiles\vcvs_cccs4.txt)N := rows(Fnom) N = 141 k := 1..NHybrid-pi BJT Model

*File: vcvs_cccs4.cirVEin 99 0 AC 0.1R1 1 99 100R2 1 2 10R3 1 4 40KR4 4 0 2KR5 3 0 10

GG Vp Vn Vcp Vcn gain

GG hieR

GG

= ( )

=

=

4 0 99 11

4 0 999 1 1( )

A

B

=

=

747812 5 75000188040000 187900000

.

11250019800000

0 1

0

= ( )= ( )

D

E

iPD1 1



*

C1 1 4 80nC2 4 0 5n*

EE 2 3 1 4 0.004* B = 100; Gain B/R1 = 1.0 in GG GG 4 0 99 1 1.AC DEC 20 10 1E8.PRINT AC V(4) VP(4).OPTIONS NOECHO NOPAGE NOMOD

.END

Y = 4Traces are separated to show congruency.

1 2 3 4 5 6 7 830

20

10

0

10

20

30

SpiceNDS

Magnitude at node Y

Log freq(Hz)

dBV db(Fnomk,2)

db(Voi) 4

log(Fnomk,1), Li

1 2 3 4 5 6 7 8200160120

8040

04080

SpiceNDS

Phase angle at node Y

Log freq(Hz)

Deg Fnomk,3

(Vai)1 10

log(Fnomk,1), Li



3.6 TWO INPUTS, THREE OUTPUTS

K := 103 n := 109 mA := 103

R1 := 1K R2 := 2K R3 := 1K R4 := 2K R5 := 2.2KR6 := 2.2K R7 := 1K R8 := 1K C1 := 20n C2 := 4nC3 := 6nU := 7 Y := (1 3 5)T

Three outputs.

Gains:

gm := 10 a := 5

R1 R2 R3 R4 R5 R6

R7 R8

C1 C2 C3

V1 V2 V3 V4

V7V6

GG EE

V5

Ein1 Ein2

+

+

Ein :=

99 10098 50

RR

RRRRRRRR

:=

99 1 11 2 22 3 33 4 44 5 55 98 66 0 77 0 8

=

CC

CCC

:

1 0 13 0 25 0 3

=LL : 0



For VCVS EE:

V4 V7 = a(Ein2 V2) EE := (4 7 98 2 a) a = 5

For VCCS GG:

gl = gm(V3 Ein1) GG := (2 6 3 99 gm) gm = 10


DC Analysis

Igl := Vn8 Igl = 311.92mA

AC Analysis

BF := 3 ND := 3 PD := 40 i := 1..NDPD + 1

Li := BF + s := 210L cvi := D(siI A)1B + E

Sample of the three (complex) outputs:

X A B

Vdc D X E

Vdc

:

:

.

.

.

= = +

=

1

22 03100 03308 96

=

Y135

Vn solve A A

V V V V V V V Ig

VnT

: ,

.

= ( )

=

1 11 14

1 2 3 4 5 6 7 1

22 003 133 92 100 03 567 93 308 96 311 92 351 66 0 . . . . . . .331( )

iPD1 1

cv

ii

i5

21 37 6 19100 03 0

308 92 1 14=

+

. .

.

. .

=

Y135



SPICE Listing Two In Three Out

*File: c:\SPICEapps\Cirtext\wizard.cir

VEin1 99 0 AC 100

VEin2 98 0 AC 50

*

R1 99 1 1K

R2 1 2 2K

R3 2 3 1K

R4 3 4 2K

R5 4 5 2.2K

R6 5 98 2.2K

R7 6 0 1K

R8 7 0 1K

*

C1 1 0 20n

C2 3 0 4n

C3 5 0 6n

*

GG 2 6 3 99 10

EE 4 7 98 2 5

.AC DEC 50 1E3 1E6

.OPTIONS NOMOD NOECHO NOPAGE

.PRINT AC V(1) V(3) V(5)

.OPTIONS NUMDGT 8

.END

Fnom := READPRN(c:\SPICEapps\datfiles\wizard.txt)N := rows(Fnom) N = 151 k := 1..N

Vo db cv Vo db cv Vo db cvi i i i i1 2 31 2= ( ) = ( ) = ii( ) 3



NDS and SPICE plots:

3 3.5 4 4.5 5 5.5 626

28

30


Log freq(Hz)

dBV db(Fnomk,2)

log(Fnomk,1)

3 3.5 4 4.5 5 5.5 626

28

30

32NDS V1 magnitude

Log freq(Hz)

dBV Vo1i

Li

3 3.5 4 4.5 5 5.5 640.0016

40.0020

40.0024

40.0028Spice V3 magnitude

Log freq(Hz)

dBV db(Fnomk,3)

log(Fnomk,1)



3.7 THIRD-ORDER OPAMP MODEL

This model has two poles and one zero.

K := 103 uF := 106 pF := 1012 MHz := 106 KHz := 103

3 3.5 4 4.5 5 5.5 640.0016

40.0020

40.0024

40.0028NDS V3 magnitude

Log freq(Hz)

dBV Vo2i

Li

3 3.5 4 4.5 5 5.5 648.8

49.2

49.6


Log freq(Hz)

dBV db(Fnomk,4)

log(Fnomk,1)

3 3

node list tolerance analysis

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