JOURNAL DE PHYSIQUE Colloque C4, supplement au n09, Tome 49, septembre 1988

NONSELECTIVE W/WSi,-CVD TECHNOLOGY FOR LOW RESISTANCE VIA PLUGS ON ALUMINUM

E. BERTAGNOLLI, C. WIECZOREK, B. HOFFMANN and H. SCHABER

Siemens AG, Corporate Research and Development, Otto-Hahn-Ring 6, 0-8000 Miinchen 83, F.R.G.

Abstract: By reducing the thermal budget of a nonselective W/WSi,- CVD technology, a via filling process completely compatible with a conventional aluminum track scheme has been obtained. A specific via resistance in the range of a few 10-8 Ocm2 was realized. Hillock formation was suppressed significantly. No fluorine pile-up was found at the WSi,-/AlSiTi-interface so the formation of an A1F3-interlayer has been avoided successfully.

Introduction

In multilevel metallization the formation of reliable and planar interlevel contacts is a key issue. Sputtered metals for via contacting fail due to self-shadowing problems as via dimensions are continuously shrunk. Blanket CVD-tungsten offers unique conformal step coverage. Therefore it is well suited for via filling purposes. Tungsten plugs in vias allow for the use of headless metal runners in a conventional aluminum track scheme. They fulfill the option of stackability of interlevel contacts. Tungsten on aluminum, however, suffers from a high interface resistance and an unfavourable thermal budget /I/.

The formation of a highly resistive A1F3-layer is an inherent problem as long as tungsten fluorine (WFs) is used for the deposition of tungsten and tungsten compounds / 2 / . A high deposition temperature prevents the formation of such compounds with low volatility, which influence the interfacial resistance. High temperature, however, enhances hillock formation. Also the reliability of an optional diffusion barrier at the aluminum-/silicon- interface in the contact area may be endangered. An important goal in every multilevel metallization scheme is the repeated application of the via filling process. This aggravates the problem of contact resistances in connection with low deposition temperature.

This paper describes a tungsten via plug process aiming at the minimization of via resistance and at hillock suppression. The main emphasis is put on optimization of the integrability in a multilevel wiring scheme based on AlSiTi-metallization.

In order to clarify the importance of interfacial phenomena and geometrical effects the measured resistances are compared with 2-D simulations. Calculations were done using the program VLSICAP / 3 / , which is based on a 2- D finite element method.

Experimental

A first metal layer of sputtered and patterned AlSiTi-alloy was planarized by an etch back of a plasma oxide/polyimide double layer /4/. 1000 nm plasma

Article published online by EDP Sciences and available at http://dx.doi.org/10.1051/jphyscol:1988436

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oxide were deposited as intermetal dielectric. The different-sized viaholes were opened in i1 dry plasma etch process using CHF3/02. The native oxide on the AlSiTi-surface in the vias was removed by a dip etch in dilute HF just before deposition of tungsten in a cold wall reactor.

Blanket CVD-tungsten was deposited using WFs/SiH4/H2 as reactive gases. In order to avoid peel-off of tungsten due to bad adhesion on silicon oxide a 100 nm WSi,-layer (x= 2 . 4 ) was deposited first. Then 500 nm of tungsten were grown on top of this interlayer. This double layer deposition was performed at various temperatures (TD = 400, 425 and 450°C) .

Vias with both lateral dimensions larger than 1 Hm are not completely filled by this process; the inner part of such a via remains empty. A sacrificial layer of 300 nm polyimide was spun onto the wafers. This layer was etched prior to the tungsten etch back process, thus leaving protective polyimide plugs in the grooves between the vertical tungsten layers covering the sidewalls of the vias. Then the W/WSi, on top of the dielectric was removed by an etch back process using a SFs/Oz-plasma (etch-rate: 400 nm tungsten/min, un.iformity: +/- 5 % ) /5/. Finally the polyimide plugs were removed with a resist stripping process. Thus the planar oxide surface was re-established.

A second metal layer of AlSiTi-alloy was sputtered and patterned. Finally the wafers were annealed for 15 minutes at 450°C in forming gas atmosphere.

Via resistances were measured using two level via chains with vias ranging down to an edge length of 1 . 0 pm. The via hole filling was controlled by SEM as well as by metallographic cross-sections. The composition of the layers was tested by e-Lectron microprobe mass analysis. Auger depth profiling was used to monitor the interface composition.

Results

Sheet resistance of the WSi,-and W-layers are only weakly dependent on deposition temperature in the range investigated. Strong hillock suppression is, however, achieved by decreasing TD to 400°C (fig. 1). Even for this low deposition temperature, the goal of via resistances in the 10-eQcm2 regime has been achieved. Wereas the high temperature (TD = 4 5 0 ° C ) via resistance is predicted quite well by the simulation based on measured sheet resistances of fig. 1 , the rise of R,L, with decreasing TD is underestimated by the calculations. This discrepancy points at the existence of a resistive interfacial layer at low TD.

iV-Deposition Temperature T ~ [ ' c ]

Fig.1: W- and WSi, (x=:2.4) sheet resistances vs. deposition temperature T, and hillock density on AlSiTi

Deposition Temperature ( O C )

2.0

- C - 1.5

a, 0 c m ... m 1.0 .- ln a, a m 5 0.5

0.0

Fig.2: Resistance of a 1.0 x 1.0 pma via vs.

WSiJW deposition temperature. Simulations based on experimental sheet resistivities show only little increase of via resistance with decreasing deposition temperature

Via \

% ( 1 . 0 ~ l.0)prn2 - \ \ \

X. --*- -

- ---- Experirn.

- 2 D Sirnul.

I I I

400 425 450 500

Vias ranging down to a nominal edge length of 1 pm have been sufficiently filled (fig.3a-c).

a) 1.0 x 1.0 pm' b) 1.1 x 1.1 pmz c) 1.2 x 1.2 &m2

Fig.3a-3c: SEM micrographs of via chains with CM-tungsten filled vias o f different size CT,=4WOC) after AISiTi-&patterning

A comparison of the measured via resistances for different via sizes with simulated values is given in fig. 4. The simulation was based on measured sheet resistances (fig. 1). Results are in good agreement with experimental data for TD = 450°C. As the changes in sheet resistivity for various deposition temperatures are small (fig. 1 , only a slight increase of via resistance with decreasing deposition temperature is predicted by simulation. A disadvantage of the lower deposition temperature is the slightly reduced deposition rate (fig. 5). Below 400°C only insufficient growth rate could be obtained.

Via Resistance

- --- Experlm.

- 2 D Sirnul.

0.0 I I I I I 0.5 1 .O 1.5 2.0 2.5

Via Size (pm)

Fig.4: Via resistance vs. via size for T, =450QC

400 425 450

W-Deposition Temperature T~ ["c ]

Fig.5: Dependence of deposition rate on deposition temperature

The investigation of the WSi,-AlSiTi interface by AES-profiling did not show any pile up of fluorine (fig. 6). Fig. 7 shows a TEM-micrograph of this interface.

The formation of AIFs during the tungsten deposition process probably is prevented by the presence of silane. SiH4 seems to enhance the formation of volatile fluorine compounds thus blocking the formation of AlF3.

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0 20 4 0 6 0 80 100

Sputter Time Cminl

Fig.6: AES depth profile of WIWSiJAISiTi-system aflcr 400°C anneal. No indication of an interfacial layer (AIF,) between AlSiTi and WSL can be seen

WSi, I

I

100 nrn

Fig.? TEM micrograph of a crossdection of the W/WSix/AISiTi-interlace

Conclusions

With a low temperature W/WSi,-CVD technology for via-filling a fully stackable multilayer interconnect system using conventional aluminum tracks comes into reach. In particular the well known trade-off between via resistances and hillock formation could be greatly alleviated.

Acknowledgement

The authors would like to thank M. Stolz for preparing the metallographic cross-sections, E. Renner for SEM analysis, A. Mitwalsky for TEM analysis, W. Pamler for AES profiling and I. Maier for electrical characterization.

References

/1/ R.S. Blewctr, Solid State Technol., Nov. 1986, pp. 117

/2/ T. Moriya, S. Shinia, U. Hazuki, M. Chiba and J.M Kashiwagi, IEEE Techn. Dig. IEDM, N.Y. 1983, pp. 553

/3/ F. Strake]:, "VLSICAP", Thesis, Techn. Univ. Vienna 1985

/4/ V. Grewal, A Gschwandtner and G. Higelin, V-MIC 1986 Conf. Proc. IEEE, pp. 107

/5/ G. Higelin, C. Wieczorek, V. Grewal, V-MIC 1986 Conf. Proc. IEEE, pp. 443