norhayati soin 05 keee 4425 week 6/2 8/19/2005 lecture : keee 4425 week 6/2 design rules,layout and...

Norhayati Soin 05 KEEE 4425 WEEK 6/2 8/19/2005

LECTURE : KEEE 4425

WEEK 6/2

DESIGN RULES,LAYOUT AND STICK DIAGRAM


SYSTEM

GATE

CIRCUIT

VoutVin

CIRCUIT

VoutVin

MODULE

+

DEVICE

n+S D

n+

G

Review: Design Abstraction Levels


Summary of VLSI Components


CMOS Mask Layers

P substrate

wafer

n well

• Determine placement of layout objects

• Color coding specifies layers

• Layout objects:

– Rectangles

– Polygons

– Arbitrary shapes

• Grid types

– Absolute (“micron”)

– Scaleable (“lambda”)


Mask Generation

• Mask Design using Layout Editor

– user specifies layout objects on different layers

– output: layout file

• Pattern Generator

– Reads layout file

– Generates enlarged master image of each mask layer

– Image printed on glass

• Step & repeat camera

– Reduces & copies image onto mask

– One copy for each die on wafer

– Note importance of mask alignment


Symbolic Mask Layers

• Key idea: – Reduce layers to those that describe design– Generate physical layers as needed

• Magic Layout Editor: "Abstract Layers”– metal1 (blue) - 1st layer metal (equiv. to physical layer)– Poly (red) - polysilicon (equivalent to physical layer)– ndiff (green) - n diffusion (combination of active, nselect)– ntranistor (green/red crosshatch) - combined poly, ndiff– pdiff (brown) - p diffusion (combination of active, pselect)– ptransistor (brown/red crosshatch) - combined poly, pdiff– contacts: combine layers, cut mask


About Magic

• Scalable Grid for Scalable Design Rules– Grid distance: lambda)– Value is process-dependent:

= 0.5 X minimum transistor length

• Painting metaphor– Paint squares on grid for each mask layer– Layers to interact to form components (e.g.

transistors)


Mask Layers in Magic

• Poly (red)

• N Diffusion (green)

• P Diffusion (brown)

• Metal (blue)

• Metal 2 (purple)

• Well (cross-hatching)

• Contacts (X)


Magic User-Interface

Cursor

Box

Paint(poly)

Paint(pdiff)

Paint(ntransistor)

• Graphic Display Window– Cursor

– Box - specifies area to paint

• Command window (not shown)– accepts text commands:paint poly:paint red:paint ndiff:paint green:write

– prints error & status messages


Layer Interaction in Magic

• Transistors - where poly, diffusion cross

– poly crosses ndiffusion - ntransistor

– poly crosses pdiffusion – ptransistor

• Vias - where layers connect

– Metal 1 connecting to Poly - polycontact

– Metal 1 connecting to P-Diffusion (normal) - pdc

– Metal 1 connecting to P-Diffusion (substrate contact) - psc

– Metal 1 connecting to N-Diffusion (normal) - ndc

– Metal 1 connecting to N-Diffusion (substrate contact) - nsc

– Metal 1 connecting to Metal 2 - via


Magic Layers – Example

nwell

nsc

psc

p-transistor

ntransistor

metal1

metal1

metal1

poly

poly

ndc ndc

polycontact

polycontact

pdc


Why we need design rules

• Masks are tooling for manufacturing.

• Manufacturing processes have inherent limitations in accuracy.

• Design rules specify geometry of masks which will provide reasonable yields.

• Design rules are determined by experience.


Manufacturing problems

• Photoresist shrinkage, tearing.

• Variations in material deposition.

• Variations in temperature.

• Variations in oxide thickness.

• Impurities.

• Variations between lots.

• Variations across a wafer.


Transistor problems

• Variations in threshold voltage:– oxide thickness;– ion implantation;– poly variations.

• Changes in source/drain diffusion overlap.

• Variations in substrate.


Wiring problems

• Diffusion: changes in doping -> variations in resistance, capacitance.

• Poly, metal: variations in height, width -> variations in resistance, capacitance.

• Shorts and opens:


Oxide problems

• Variations in height.• Lack of planarity -> step coverage.

metal 1metal 2

metal 2


Via problems

• Via may not be cut all the way through.• Undesize via has too much resistance.• Via may be too large and create short.


MOSIS CMOS design rules

• Designed to scale across a wide range of technologies.

• Designed to support multiple vendors.• Designed for educational use.• Ergo, fairly conservative.


and design rules

is the size of a minimum feature.• Specifying particularizes the scalable rules. • Parasitics are generally not specified in units


Design Rules

• Typical rules:

– Minumum size

– Minimum spacing

– Alignment / overlap

– Composition

– Negative features


Types of Design Rules

• Scalable Design Rules Based on scalable “coarse grid” - (lambda)

– Idea: reduce value for each new process, but keep rules the same

• Key advantage: portable layout

• Key disadvantage: not everything scales the same

– Not used in “real life”

• Absolute Design Rules

– Based on absolute distances (e.g. 0.75µm)

– Tuned to a specific process (details usually proprietary)

– Complex, especially for deep submicron

– Layouts not portable


CMOS Design Rule Summary• Contacts (Vias)

– Cut size: exactly 2l X 2l

– Cut separation: minimum 2l

– Overlap: min 1l in all directions

– Magic approach: Symbolic contact layer min. size 4l X 4l

– Contacts cannot stack (i.e., metal2/metal1/poly)

• Other rules

– cut to poly must be 3l from other poly

– cut to diff must be 3l from other diff

– metal2/metal1 contact cannot be directly over poly

– negative features must be at least 2l in size

– CMP Density rules (AMI/HP subm): 15% Poly, 30% Metal


Design Rule Checking in Magic

• Design violations displayed as error paint

• Find which rule is violated with ":drc why” Poly must overhang transistor by at least 2 (MOSIS rule #3.3)


Aside - About MOSIS

• MOSIS - MOS Implementation Service

• Rapid-prototyping for small chips

– Multi-project chip idea - several designs on the same wafer

– Reduced mask costs per design

– Accepts layout designs via email

– Brokers fabrication by foundries (e.g. AMI, Agilent, IBM, TSMC)

– Packages chips & ships back to designers

• Our designs will use AMI 1.5µm process (more about this later)


Aside - About MOSIS• Some Typical MOSIS Prices (from www.mosis.org)

– AMI 1.5µm “Tiny Chip” (2.2mm X 2.2mm) $1,080

– AMI 1.5µm 9.4mm X 9.7mm $17,980

– AMI 0.5µm 0-5mm2 $5,900

– TSMC 0.25µm 0-10mm2 $15,550

– TSMC 0.18µm 0-7mm2 $24,500

– TSMC 100-159mm2 $63,250 + $900 X size

• MOSIS Educational Program (what we use)

– AMI 1.5µm “Tiny Chip” (2.2mm X 2.2mm) FREE*

– AMI 0.5mm “Tiny Chip” (1.5mm X 1.5mm) FREE*


Wires

6

3

3

3

metal 3

metal 2

metal 1

pdiff/ndiff

poly2


Transistors

2

3

1

3 2

5


Vias

4

1

4

2

• Types of via: metal1/diff, metal1/poly, metal1/metal2.


Metal 3 via

• Type: metal3/metal2.

• Rules:– cut: 3 x 3– overlap by metal2: 1– minimum spacing: 3– minimum spacing to via1: 2


Spacings

• Diffusion/diffusion: 3

• Poly/poly: 2

• Poly/diffusion: 1

• Via/via: 2

• Metal1/metal1: 3




Stick diagrams

• A stick diagram is a cartoon of a layout.

• Does show all components/vias (except possibly tub ties), relative placement.

• Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.


Stick Diagrams

• Key idea: "Stick figure cartoon" of a layout

• Useful for planning layout– relative placement of transistors– assignment of signals to layers – connections between cells– cell hierarchy


Stick Diagrams

Metal (BLUE)

Polysilicion (RED )

N-Diffusion (Green)

P-Diffusion (Brown)

Contact / Via

poly

n-diff

p-diff

metal

poly n-diff p-diff metal

S N P NC

S X NC

S NC

S

Connection RulesLayers


Example - Stick Diagrams

A B

A

B

Circuit Diagram. Pull-Down Network(The easy part!)

Alternatives - Pull-up Network

Complete Stick Diagram


Example - Stick Diagrams

Inverter

Vdd

In

Gnd

Out

NAND Gate

Vdd

AOut

Gnd

B


Dynamic latch stick diagram

VDD

in

VSSphiphi’

out


Stick Diagram XOR Gate Examples

Exclusive OR Gate

Vdd

A

Out

GndB

A’ B’

A’

B’

BA’

Out

A A’

B B’

A

B’

A

B

A’

B’

A’

B


Hierarchical Stick Diagrams

VddA

Out

Gnd

B

Vdd

Gnd

VddA

Out

Gnd

B

Vdd

Gnd

NAND

NAND CellStick Diagram

NAND CellOutline

• Define cells by outlines & use in a hierarchy to build more complex cells


Cell Connection Schemes

• External connection - wire cells together

• Abutment - design cells to connect when adjacent

• Reflection, mirroring - use to make abutment possible


Example: 2-input multiplexer

• First cut: Vdd

A

Out

NAND

A

B

Gnd

Vdd

Gnd

Vdd

Out

NAND

A

B

Gnd

Vdd

Gnd

Vdd

Out

NAND

A

B

Gnd

Vdd

Gnd

Vdd

Out

S

B

S’

Gnd

A

S

B

S’

OUT

OUT = A*S + B*S’


Sticks design of multiplexer

• Start with NAND gate:


NAND sticks

VDD

a

VSS

out

b


Refined one-bit Mux Design

• Use NAND cell as black box

• Arrange easy power connections

• Vertical connections for allow multiple bits

NAND

A

B

Gnd

Vdd

Gnd

Vdd

OutNAND

A

B

Gnd

Vdd

Gnd

Vdd

Out

select’ select

NAND

A

B

Gnd

Vdd

Gnd

Vdd

Out

VddAB

Gnd

Out


Multiple-Bit Mux

select’ select

NAND

A

BGnd

Vdd

Gnd

Vdd

OutNAND

A

BGnd

Vdd

Gnd

Vdd

OutNAND

A

BGnd

Vdd

Gnd

Vdd

Out

VddA0A0

Gnd

Out0

NAND

A

BGnd

Vdd

Gnd

Vdd

OutNAND

A

BGnd

Vdd

Gnd

Vdd

OutNAND

A

BGnd

Vdd

Gnd

Vdd

Out

VddA1B1

Gnd

Out1


Cell Mirroring, Overlap

• Use mirroring, overlap to save area

VddA0B0

Gnd

NAND

A

B

Gnd

Vdd

Gnd

Vdd

OutNAND

A

B

Gnd

Vdd

Gnd

Vdd

OutNAND

A

B

Gnd

Vdd

Gnd

Vdd

Out

B1A1

Vdd


Example: Layout / Stick Diagram

• Create a layout for a NAND gate given constraints:

– Use minimum-size transistors

– Assume power supply lines “pass through” cell from left to right at top and bottom of cell

– Assume inputs are on left side of cell

– Assume output is on right side of cell

– Optimize cell to minimize width

– Optimize cell to minimize overall area


Layout Example

A B

A

B

A

B

OUT

Vdd!Vdd!

Gnd! Gnd!

Circuit Diagram. Exterior of Cell


Example - Magic Layout

• Overall Layout: 52 X 16


Review - VLSI Levels of Abstraction

Specification(what the chip does, inputs/outputs)

Architecturemajor resources, connections

Register-Transferlogic blocks, FSMs, connections

Circuittransistors, parasitics, connections

Layoutmask layers, polygons

Logicgates, flip-flops, latches, connections

You are Here


Levels of Abstraction - Perspective

• Right now, we’re focusing on the “low level”:– Circuit level - transistors, wires, parasitics– Layout level - mask objects

• We’ll work upward to higher levels:– Logic level - individual gates, latches, flip-flops– Register- transfer level - Verilog HDL– Behavior level - Specifications


The Challenge of Design

• Start: higher level (spec)

• Finish: lower level (implementation)

• Must meet design criteria and constraints

– Design time - how long did it take to ship a product?

– Performance - how fast is the clock?

– Cost - NRE + unit cost

• CAD tools - essential in modern design


CAD Tool Survey: Layout Design

• Layout Editors• Design Rule Checkers (DRC)• Circuit Extractors• Layout vs. Schematic (LVS)

Comparators• Automatic Layout Tools

– Layout Generators– ASIC: Place/Route for Standard Cells, Gate

Arrays


Automatic layout

• Cell generators (macrocell generators) create optimized layouts for ALUs, etc.

• Standard cell/sea-of-gates layout creates layout from predesigned cells + custom routing.– Sea-of-gates allows routing over the cell.

norhayati soin 05 keee 4425 week 6/2 8/19/2005 lecture : keee 4425 week 6/2 design rules,layout and...

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