novel fast peak detector for single- or three-phase unsymmetrical

Journal of Electrical Engineering & Technology Vol. 6, No. 5, pp. 658~665, 2011 http://dx.doi.org/10.5370/JEET.2011.6.5.658

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Novel Fast Peak Detector for Single- or Three-phase Unsymmetrical Voltage Sags

Sanghoey Lee* and Hanju Cha†

Abstract – In the present paper, a novel fast peak detector for single- or three-phase unsymmetrical voltage sags is proposed. The proposed detector is modified from a single-phase digital phase-locked loop based on a d-q transformation using an all-pass filter (APF). APF generates a virtual phase with 90° phase delay. However, this virtual phase cannot reflect a sudden change of the grid voltage in the moment of voltage sag, which causes a peak value to be significantly distorted and to settle down slowly. Specifically, the settling time of the peak value is too long when voltage sag occurs around a zero crossing, such as phase 0° and 180°. This paper describes the operating principle of the APF problem and proposes a modified all-pass filter (MAPF) to mitigate the inherent APF problem. In addition, a new fast peak detector using MAPF is proposed. The proposed detector is able to calculate a peak value within 0.5 ms, even when voltage sag occurs around zero crossing. The proposed fast peak detector is compared with the conventional detector using APF. Results show that the proposed detector has faster detection time in the whole phase range. Furthermore, the proposed fast peak detector can be effectively applied to unsymmetrical three-phase voltage sags. Simulation and experimental results verify the advantages of the proposed detector and MAPF.

Keywords: Fast peak detector, All-pass filter, Modified all-pass filter

1. Introduction

Power quality issues have been studied substantially in recent years because of the considerable penetration of renewal energy systems and growing interests for smart grids. Voltage sags are a decrease in root mean square (RMS) voltage below 0.9 pu of nominal voltage at the power frequency for durations from 0.5 cycle to 1 min, thereby causing expensive downtime [1]. The sag phenomenon is caused by atmospheric discharges, transformer energizing, short circuits, turning on of motors, and high power loads such as from soldering machines and arc furnaces. Some of the consequences of these perturbations are the interruption of industrial processes that lead to high economical losses, erroneous functioning or tripping of equipment, bad quality or damaged products, long restart times, and permanent damage to equipment [2].

Many studies in recent years have focused on the performance evaluation of mitigation devices [3], [4]. Generally, the RMS method is used to detect the sag before the mitigation is initiated. The disadvantage of this method is that a window of historical data has to be obtained and processed before a mitigation signal can be sent to the hardware. Limitations associated with the RMS method are discussed in [5], [6]. Due to the use of a low-pass filter and

instantaneous reactive power theory to extract the sag, this method is too complex for implementation in a digital signal processor. A method for determining the start and end time of a sag using wavelets is presented in [7]. This is performed to verify a proper breaker operation after the sag occurs. In addition, mitigation devices using the above methods, such as sag/swell compensators and dynamic voltage restorer (DVR), in which the basic principle is to inject a voltage in series with the supply when a fault is detected, have been proposed [8]–[11].

The present paper proposes a fast peak value calculation method for rapid voltage sag detection using a modified all-pass filter (MAPF). The proposed fast peak detector using MAPF can quickly calculate peak value, even when voltage sag occurs around zero crossing. To confirm the effectiveness of the proposed fast peak detector, a simulation and an experiment are carried out using PSIM and DSP controller, respectively.

2. Proposed Fast Peak Detection Algorithm

2.1 Conventional peak detector with all-pass filter In general, the traditional hardware-based peak voltage

detector with diodes, a capacitor, and a resistor is used as a voltage sensing circuit. When its input voltage is decreased, the capacitor voltage is discharged through the resistor. In contrast, when input voltage is increased, the capacitor

† Corresponding Author: Department of Electrical Engineering, Chungnam National University, Daejeon, Korea. ([email protected])

* Wind Turbine Development and Engineering Team, Doosan Heavy Industries and Construction, Daejeon, Korea. ([email protected])

Received: February 17, 2011; Accepted: June 7, 2011

Sanghoey Lee and Hanju Cha

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voltage is charged directly. Therefore, the charging speed is faster than the discharging speed. Reducing the resistance increases the discharge speed. However, the ripple voltage of the detected signal is increased, making the signal difficult to use. In contrast, the software-based peak voltage detector has demonstrated growing hardware performance. Since the introduction of the RMS method in [12], similar peak detectors have been released for power systems [1], [2], [8], [10]. For example, the compensation devices of voltage sag requires a peak detector and must respond in less than a quarter of cycle, or as fast as possible, which is difficult to accomplish. In some cases, a technique to detect the start of perturbations is also needed. A number of methods for these purposes have been reported; however, in most cases, these methods are not sufficiently fast. Therefore, a new fast peak detector development is needed.

Recently, the digital phase-locked loop (DPLL) has been widely used because it is simple and is able to detect not only phase, but also peak voltage. Fig. 1 shows the block diagram of conventional DPLL that uses d-q transformation with an all-pass filter (APF). APF generates a virtual phase, which is has a 90° phase lag from the measured grid voltage [13], [14].

Fig. 1. Block diagram of conventional digital PLL

The virtual phase Vqs can be obtained from the measure

grid voltage Vds = Vgrid using APF in discrete-time domain:

)1()()1()( −++−−= kVkcVkcVkV dsdsqsqs (1)

where

22

+−

=ωTωTc

c

c (2)

)cos(*)()sin(*)()( θkVθkVkVV qsdsqepeak +−== (3)

Therefore, Vqe(k) is equal to Vpeak calculated from Eq. (3)

in the conventional DPLL. As shown in Fig. 2, APF generates proper virtual phase when sag occurs during 45°–90° and 180°–270°. However, APF generates increased virtual phase in the opposite direction from the

decreased grid voltage when sag occurs during 90°–180° and 270°–360°, as shown in Fig. 3. This APF output variation in the opposite direction is reflected into DPLL operation. Thus, the phase-tracking and peak-voltage detection time slow down because of the unexpected disturbance to the DPLL operation.

Both original input and virtual waveforms using APF are shown in Fig. 2, where Vds can be considered as sin(θ) and Vqs as cos(θ) at the fundamental phase angle. When sag occurs around 150° and 320° in Fig. 3, the original voltage falls; however, the virtual voltage rises. This means that the peak detector in the conventional DPLL delivers a wrong result during a relatively long transient interval. Therefore, MAPF is proposed to avoid the mentioned problem.

Fig. 2. Normal operation of APF

Fig. 3. Abnormal operation of APF

2.2 Proposed MAPF

As described in the previous section, the transient

interval caused by APF results in a longer phase-detection time; thus, more time is needed to stabilize and lock the phase of grid voltage.

MAPF is proposed for a faster detection of peak voltage and grid voltage phase compared with APF. MAPF is a very simple technique because it only checks the grid voltage variation.

Fig. 4 shows the phasor diagram of grid voltage in reference frames, where Vds is the d-axis component with the same magnitude and phase as the grid voltage; Vqs is the virtual q-axis component, which is generated using APF from the grid voltage; and Vde and Vqe are voltage components in synchronous frame.

MAPF is different from the APF-based method. The virtual q-axis voltage component is generated from the difference between the current and previous value of the d-


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axis voltage component in stationary reference frame, as shown in Eqs. (4) and (5):

)sin()1()(Δ θkkVkVV qsqsqs =−−= (4)

)cos()1()(Δ θkkVkVV dsdsds =−−= (5)

Fig. 4. Reference vector of single grid voltage

where Vds(k) is the grid voltage and Vds(k-1) is the grid voltage at one step ahead.

Here, ΔVds is equal to kcos(θ), and the magnitude is smaller than the actual grid voltage.

The RMS value ΔVRMS, which is an RMS value of the grid voltage at the normal condition and is updated every hour, is defined as follows:

22 ΔΔΔ dsqsRMS VVV += (6)

The value Δ Vds is compared with Δ VRMS. If Δ Vds(k) >

+Δ VRMS or Δ Vds < -Δ VRMS, which indicates that sag occurs, the sag can be detected, as shown in Fig. 5. At the moment of detection, DPLL uses MAPF, rather than APF.

When sag is recognized, the implementation of MAPF in discrete-time domain is as follows:

)1()1()1()( −+−+−−= kVkcVkcVkV dsdsqsqs (7)

Using MAPF, inversely varying virtual voltage can be avoided. In such a case, the Vde value has a smaller step change than in APF. This technique is very simple; however, it has better performance when detecting peak voltage and phase tracking based on DPLL.

Fig. 5. Block diagram of MAPF

2.3 Proposed fast peak detector The proposed fast peak detector is a very simple

algorithm and inherently works well under sag generation in any phase. Most of conventional peak detector methods have time delays, including the RMS method (2–9 ms) [12], the hybrid KF-RMS method (0.5–4 ms) [2], and DVR (2 ms) [11]. Other methods report a delay of 1–4 ms [1], with the maximum delay being generated around 0° or 180° for all methods. The proposed fast peak detector decreases average detection delay within 0.5 ms in any phase; a three- to five-cycle sampling time is needed.

In order for ΔVds to have the same value as the grid voltage, Vgrid as a ratio of Vqe(k-1) to ΔVRMS [Eq. (8)] can be used:

RMSqegain VkVV Δ/)1( −= (8)

where Vqe(k-1) is the one-step-ahead value of Vqe(k) using synchronous reference frame, and ΔVRMS is from Eq. (6).

gaindsdsqs VkVkVkV *))1()(()( −−= (9)

Here, Vqs(k) is similar to the original APF value; however, Vqs(k) does not cause inverse value problem when sag occurs. Therefore, Vqs(k) can be used to replace the Vqs(k) generated by the original APF.

The detection technique uses a simple trigonometric equation:

1)(sin)(cos 22 =+ θθ (10)

The value of Vpeak using the proposed fast peak detector

of the grid voltage is derived from Eq. (11).

)sin(*)()cos(*)( θkVθkVV dsqspeak += (11) Fig. 6 shows the block diagram of the new fast peak

detector where cos(θ) and sin(θ) are generated from DPLL. In the simulation, the low-pass filter is not used because it has no impact on the hardware. This block diagram is designed for experimental test. In the experiment, the low-pass filter is embedded in the DSP microcontroller for

Fig. 6. Block diagram of the proposed fast peak detector


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detecting peak voltage. Fig. 7 shows the overall block diagram of the proposed fast peak detector.

Fig. 7. Overall block diagram of the proposed fast peak

detector

2.4 Extension to three-phase peak detector The sag/swell compensator and DVR need to detect

peak voltage for compensating voltage sag. However, voltage sag per phase in the three-phase system is difficult to detect. This section shows the adoption of the proposed method into the three-phase system. The proposed detection algorithm cannot be applied to all three phases of the system because it cannot detect all of the phase voltages simultaneously. In other words, if one phase peak voltage can be obtained using this algorithm, the peak voltages of other two phases have a different voltage values because of the following relationship in balanced voltage case (12):

0=++ tsr VVV (12)

The proposed algorithm cannot be adopted into three-

phase, three-wire systems; however, it can be adopted into the three-phase, four-wire system because of ground. In the current paper, both the simulation and the experimental test use three-phase, four-wire, grid-connected system; thus, the peak voltage can be detected per phase.

3. Simulation A simulation was performed to verify the proposed

algorithm under unbalanced grid voltage condition. The sampling frequency used was 10 kHz and the parameters of the PI controller were as follows: Kp = 28.6, τ = 2.2 ms. All simulation tests used the same PI controller parameters. The simulation results of the single phase with 220 V/60 Hz grid voltage, 30% sag generation, and interruption by fault are shown in Figs. 8-11.

The simulation was used to evaluate the new fast peak detector and check the detection time in any phase angle.

Furthermore, the proposed algorithm was also compared by a conventional method using d-q transformation.

Fig. 8 shows the grid voltage in non detecting angle around 180° when sagged by 30%. Fig. 8(a) shows Vds from grid voltage and 90° phase lagged virtual waveform Vqs generated by MAPF.

When Vds sags at 180°, at that time Vqs sags in 0° at the same time; however, Vqs cannot be reflected by every voltage sag because of APF. Only Vqs is reflected in its original waveform voltage sag value, as shown in Fig. 8(a). Fig. 8(b) shows Vde from synchronous d-q transformation waveform by DPLL, which causes phase in grid. In contrast, Vqe is a conventional method of peak voltage detector, which shows that the time delay for detecting the peak voltage is within 4 ms. Fig. 8(c) shows the exact detected peak voltage Vpeak within 300 μs in 180°.

Fig. 8. 30% sagged grid voltage in non detecting phase around 180°: (a) stationery reference frame Vds and Vqs; (b) synchronous reference frame Vde and Vqe; (c) detected peak voltage Vpeak

Fig. 9 shows the best detection phase at 90° using the

conventional method for quick detection of Vqe. However, when using APF, the peak value cannot be detected quickly because of the inversed voltage value. Fig. 9(a) shows Vds and Vqs. Fig. 9(b) shows Vde and Vqe. Fig. 9(c) is the detected peak voltage Vpeak within 0.3 ms.

Fig. 9. 30% sagged grid voltage around 90°: (a) stationery

reference frame Vds and Vqs; (b) synchronous reference frame Vde and Vqe; (c) detected peak voltage Vpeak


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Fig. 10 shows the sag generation angle at around 135° with 30% sagged. In Fig. 10(a), when APF is used, a longer time delay results because of the inverse value. Because MAPF is used, Fig. 10(a) shows Vqs without inverse voltage. Fig. 10(b) shows Vde and Vqe using synchronous reference frame. Fig. 10(c) shows the detected peak voltage Vpeak.

Fig. 10. 30% sagged grid voltage around 135°: (a)

stationery reference frame Vds and Vqs; (b) synchronous reference frame Vde and Vqe; (c) detected peak voltage Vpeak

Fig. 11. Interruption around 0°: (a) stationery reference

frame Vds and Vqs; (b) synchronous reference frame Vde and Vqe; (c) detected peak voltage Vpeak

Fig. 12. 30% sagged three-phase grid voltage: (a) three-

grid voltage Vr, Vs, and Vt; (b) Vr_peak; (c) Vs_peak; (d) Vt_peak

Fig. 11 shows the interruption at around 0° generated within three circles; the comparison between the conventional and new detection method is also shown.

The conventional method shows that with bigger voltage dip magnitude, longer detection time is obtained. Fig. 11(a) shows Vds and Vqs during interruption, where Vqs retains APF data. This means that the peak voltage slows down. Fig. 11(b) shows the simulation results in the case of conventional method, where Vde has a deep sag and a long interruption transient time. Fig. 11(c) shows the peak voltage detection within 0.5 ms

The three-phase simulation results with 127 V/60 Hz and 30% sag in each phase angle by phase-to-phase fault are shown in Fig. 12. Because Vgain is used in Eq. (8), spikes are present in the waveform, as shown in Fig. 12. This problem can be avoided by adopting certain technical methods, such as simple average method, allowing the peak voltage to be detected without any spikes.

4. Experimental results To confirm the simulation result, several experimental

comparisons with the conventional method using APF in a synchronous reference frame were conducted. Two power source types were used to generate unbalanced grid voltage: (1) a single-phase programmable AC power supply (Model: ES2000S, NF in Japan) that generates voltage sag of 30% and interruption in 220 V/60 Hz during the three cycles as IEC 6100-4-11 voltage dip and short interruption, and (2) a three-phase programmable AC power supply (Model: 61703, Chroma in Taiwan) that also generates voltage sag of 30% in 90 V/60 Hz during the three cycles.

The experimental prototype used a DSP TMS320F28335 as a core of control system board. The sampling time used was 100 μs, and PI controller parameters were the same as in the simulation. Sag and interruption were usually generated as ground or line-to-line fault.

In the experimental results, the conventional method used the negative peak voltage. However, the positive peak voltage of the proposed fast peak detector was used because of different axis d-q transformation. Fig. 13 shows the grid voltage in non detecting phase at around 180° when 30% sagged. Fig. 13(a) shows a grid voltage Vgrid. Fig. 13(b) shows Vde using synchronous reference frame and phase tracking characteristic. Fig. 13(c) shows the peak voltage Vqe using conventional method. Fig. 13(d) is the detected peak voltage Vpeak within 0.5 ms, where the time delay is checked by curser function in oscilloscope. Even if the Vpeak includes ripple from analog digital conversion, this ripple can be reduced using a low-pass filter or simple averaging method. Both methods were adopted in the experimental implementation; however, the latter is recommended because of a better detection time


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Fig. 13. 30% sagged grid voltage in non detecting phase

around 180°: (a) grid voltage Vgrid; (b) synchronous reference frame Vde; (c) conventional method of peak voltage Vqe; (d) detected peak voltage Vpeak using the new fast peak detector

Fig. 14(a) shows the fastest detection time with

conventional method at around 45° when 30% voltage sagged. Fig. 14(b) shows Vde using synchronous reference frame. Fig. 14(c) shows the detected peak voltage Vqe using the conventional method with a 4 ms time delay. Fig. 14(d) shows the detected peak voltage Vpeak using the new fast peak detector with a 500 μs time delay. The detection time of the proposed method is the same as that of the conventional method in the fastest case.

Fig. 14. 30% sagged grid voltage around 45°: (a) grid

voltage Vgrid; (b) synchronous reference frame Vde; (c) peak voltage Vqe using the conventional method; (d) detected peak voltage Vpeak using the new fast peak detector

Fig. 15 shows the grid voltage when sagged 30% at

around 110°. Fig. 15(a) shows the grid voltage Vgrid when using APF. The APF causes an inverse value around 110°. Fig. 15(b) shows Vde in synchronous reference frame. Fig. 15(c) shows the peak voltage Vqe using the conventional method. Fig. 15(d) shows the detected peak voltage Vpeak using the new fast detector. Unlike APF, MAPF does not cause any delay time for detecting the peak voltage.

Fig. 16 shows the interruption of the single-phase grid voltage when generating interruption for three circles by ground fault at around 0°. Fig. 16(a) shows the grid voltage Vgrid. Fig. 16(b) shows the Vde in the synchronous reference

frame. Fig. 16(c) shows the peak voltage Vqe using the conventional method. Figs. 16(b) and 16(c) demonstrate that, when using the conventional method, the magnitude of the voltage dip is larger and the detection time is longer (approximately 5 ms). Fig. 16(d) shows the peak voltage detection with the new peak detector where the detection time is approximately 0.3 ms.

Fig. 15. 30% sagged grid voltage around 110°: (a) grid

voltage Vgrid; (b) synchronous reference frame Vde; (c) peak voltage Vqe using the conventional method; (d) detected peak voltage Vpeak using the new fast peak detector

Fig. 16. Interruption around 0°: (a) grid voltage Vgrid; (b)

synchronous reference frame Vde; (c) peak voltage Vqe using the conventional method; (d) detected peak voltage Vpeak using the new fast peak detector

Fig. 17 shows the three-phase grid voltage with 30%

sagged by ground fault on r-phase. Fig. 17(a) shows the r-phase Vr of grid voltage 30% sagged. Fig. 17(b) shows the s-phase Vs of grid voltage in the normal state. Figs. 17(c) and 17(d) show the detected peak voltages Vr peak and Vs peak in r-phase and s-phase, respectively, using the new fast peak detector. The new peak detector can be applied into the three-phase system with a short detection time (within 0.5 ms).

Fig. 18 shows the comparative performance of sag detection times using APF and MAPF in both simulation and experiment, with 30% sagged. “APF” represents conventional method with APF. “MAPF” represents the conventional method with MAPF. “NSIM” is a simulation using the new fast peak detector with MAPF. Finally,


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“NEXP” is an experimental test using the new fast peak detector with MAPF. The conventional and proposed methods are able to detect the peak voltage at any phase position; however, the peak detection time using the conventional method is slower than that in the proposed method. This means that the system can achieve better performance and control response when applying the proposed method. Another advantage of the new peak detector is its ability to detect peak voltage without any PLL performance effects. As the experimental results show, even if PLL causes phase tracking delays in Vde, the proposed peak detector is able to detect the sag/swell voltage perfectly.

Fig. 17. 30% sagged in three-phase grid voltage: one-phase

Vr (a) and Vs (b) of three-grid voltage; (c) detected peak voltage Vr_peak; (d) Vs_peak in three-phase grid voltage using the new fast peak detector

Fig. 18. Comparison of sag detection time

5. Conclusion In the present paper, a new fast peak detector for single-

or three-phase unsymmetrical voltage sags has been proposed. The proposed detector has been modified from a single-phase DPLL based on a d-q transformation using APF. APF generates a virtual phase with 90° phase delay; however, the virtual phase cannot reflect a sudden change of the grid voltage in the moment of voltage sag, which

causes a peak value to be significantly distorted and to settle down slowly. Specifically, settling time of the peak value is too long when voltage sag occurs around zero crossing, such as phase 0° and 180°. This paper has described the operating principle of the APF problem and has proposed a MAPF solution to mitigate the inherent APF problem. In addition, a new fast peak detector using MAPF has been proposed that is able to calculate peak value within 0.5 ms, even when voltage sag occurs around zero crossing. The proposed fast peak detector has been compared with the conventional detector using APF, and shows faster detection time in the whole phase range. Furthermore, the proposed fast peak detector has been effectively applied to single-phase and unsymmetrical three-phase voltage sags. The advantages of the proposed detector and MAPF have been verified through simulation and experiment.

Acknowledgement This work was supported by the Human Resources

Development of the Korea Institute of Energy Technology Evaluation and Planning (KETEP) grant funded by the Korea government Ministry of Knowledge Economy (No. 20104010100600)

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Sanghoey Lee received his B.S. degree in Instrumentation Control Engineering from Konyang University, Korea, in 2002, and his M.S. and Ph.D. degrees in Electrical Engineering from Chungnam National University, Korea, in 2005 and 2011, respectively. From 2005 to 2007, he worked in the

Institute for Advanced Engineering, Yong-in, Korea. He is currently part of the Wind Turbine Development and Engineering Team in Doosan Heavy Industries and Construction, Daejeon, Korea. His research interests include power quality, advanced converter, and control for renewable energy system and microgrids.

Hanju Cha received his B.S. degree in Electrical Engineering from Seoul National University, Korea, in 1988; his M.S. degree from Pohang Institute of Science and Technology, Korea, in 1990; and his Ph.D. degree from Texas A&M University, College Station, TX, USA, in 2004. From 1990 to 2001, he

was with LG Industrial Systems, Anyang, Korea, where he was engaged in the development of power electronics and adjustable speed drives. In 2005, he joined the Department of Electrical Engineering, Chungnam National University, Daejeon, Korea. In 2009, he was a visiting professor in United Technology Research Center, Hartford, CT, USA. His research interests include high power dc-dc converter; ac/dc, dc/ac, and ac/ac converter topologies; power quality and utility interface issues for distributed energy system; and microgrids.

novel fast peak detector for single- or three-phase unsymmetrical

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