november 2006 spaceops 2010 conference, huntsville, alabama by josé feiteirinha, nuno sebastião...
TRANSCRIPT
![Page 1: November 2006 SpaceOps 2010 Conference, Huntsville, Alabama By José Feiteirinha, Nuno Sebastião Date: 25-30 April 2010 Emulation Using the CellBE Processor](https://reader035.vdocuments.net/reader035/viewer/2022062518/56649ec85503460f94bd5e5b/html5/thumbnails/1.jpg)
November 2006
SpaceOps 2010 Conference, Huntsville, Alabama
By José Feiteirinha, Nuno Sebastião
Date: 25-30 April 2010
Emulation Using the CellBE Processor
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Purpose
Introduction
History and Motivation
Emulation Techniques
– Interpretation– Dynamic Translation
The CellBE Processor
– Architecture µLeon
– Implementation Details– Performance Evaluation
Conclusions
Agenda
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PurposePurpose
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Emulation of Onboard Software
is in the Critical Path for SpaceCraft Simulators
Heavily explored area
Optimization techniques have been here for years now
CellBE provides a new processor architecture design
It’s performance as an emulator host should be considered
Purpose
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History and Motivation
Performance of the new Leon2 processor is 3x to 5x higher than what traditional emulation techniques provide
Previous studies have shown that modern emulation technologies can provide enough performance to emulate future space capable processors [PMarques 2006]
Computer industry is providing more and more cores per CPU without many gains in the performance of individual cores
Operation multi domain missions still require one computer per spacecraft simulator (i.e. increasing costs)
Determinism and lateral application behavior are enemies
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Emulation Emulation TechniquesTechniques
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Emulation Techniques - Interpretation
Interpretation is the most common (and simple) emulation technique
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Emulation Techniques - Interpretation
Interpretation is also the slowest way to emulate
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Emulation Techniques – Dynamic Translation
Dynamic translation improves by blocking and writing into the host memory translated code in the host’s own instruction set
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The Cell The Cell ProcessorProcessor
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The CellBE Processor - Architecture
One “Main” core – PPE – Power Processing Element
Multiple “Side” cores – SPEs – Synergetic Processing Elements
Operating
System
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µLeon µLeon
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µLeon, a sub-set of the Leon2 processor
Module Leon2 µLeon
Integer Unit SPARC Compliant
Equivalent to 30% of the SPARC ISA
Floating Point Co-Processor Built-in as part of the ISA
Registers Windows 8 windows of 32 registers
Single register window
UARTS Two UARTS Single state UART
Timers Two timers and one watchdog.
n/a
Imaginary processor composed of the critical requirements for evaluating the emulation of the real Leon2 processor
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Performance Results
Performance is lower than cutting edge processors
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Performance Results
Near deterministic behaviour
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Conclusions Conclusions
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Conclusion
CellBE provides lower throughput for emulation when compared to modern x86 based computers
Commonly used architectures have high variance in performance and require the use of thresholds to ensure performance consistency
CellBE provides a near deterministic platform for emulation
Future processors with similar achitectures should be considered
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Questions and Answers
?
THANK YOUPaulo Marques: [email protected]
Damiano Guerrucci: [email protected]
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Extra Slide 1