nuevas soluciones power architecture para desarrollo … · tm freescale, the freescale logo,...

TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions Logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SmartMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2010.

AUTOSAR

March, 2010

MCALs and OS implementation

Francisco RamirezField Applications Engineer

TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions Logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SmartMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2010.

AUTOSAR

Designing with Freescale

March, 2010

MCALs and OS implementation


TMFreescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions Logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SmartMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2010.

►AUTOSAR Overview

• MCAL & OS layers

►CONFIGURATION METHODOLOGY

►TOOLS

►AUTOSAR/OS Design Process

• Flow Chart

►EXAMPLE

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions Logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SmartMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2010. 4

Microcontroller

AUTOSAR Runtime Environment (RTE)

Com

ple

x D

river

Ba

sic

Soft

wa

re

Application Layer

CommunicationServices

MemoryServices

SystemServices

Onboard DeviceAbstraction

Memory HardwareAbstraction

Communication HardwareAbstraction

Microcontroller Drivers Memory Drivers Communication Drivers I/O Drivers

I/O HardwareAbstraction

Opera

tin

g S

yste

m

Application

Software

Component

Application

Software

Component

Application

Software

Component

Application

Software

Component

AUTomotive Operative System ARchitecture

AUTOSAR Software “Packages” from Freescale


AUTOSAR partnership objectives

►(AUTomotive Open System ARchitecture)

►Manage increasing E/E complexity associated with growth in

functional scope

►Improve flexibility for product modification, upgrade and update

►Improve scalability of solutions within and across product lines

►Improve quality and reliability of E/E systems

►Enable detection of errors in early design phases.


Worldwide, OEMs and Suppliers Participate in AUTOSAR

Core Partners

Premium Members

Semi-

conductors

Tier 1 Standard

Software

Tools

AssociateMembers

CapeWare

OEM

Source: , actual status at http://www.AUTOSAR.org


AUTOSAR – An Industry Standard

2H 2005 1H 2006

2005 2006

2H 2006

Release 2.1

Improvements R2.1Specification R2.0

Phase I (2004 – 2006) Basic Software & RTE

Release 2.0

1H 2007 2H 2007 1H 2008 2H 2008 1H 2009

2007 2008 2009

2H 2009

Release 4.0

Improvements R4.0Specification R4.0

Specification R3.0

Concepts R4.0

Release 3.0

Phase II (2007 – 2009) Basic Software & RTE

Release 3.1


Microcontroller

Microcontroller Abstraction Layer

AUTOSAR Runtime Environment

ECU Abstraction Layer

AUTOSAR BSW Architecture—Basic Layers

Services Layer

Co

mp

lex

Dri

ve

r

Bas

ic S

oft

ware

Application LayerApplication

Software

Component

Application

Software

Component

Application

Software

Component

Application

Software

Component


Microcontroller


AUTOSAR BSW Architecture—Sub-Layers

Co

mp

lex D

river

Bas

ic S

oft

ware

Application Layer


MemoryServices

SystemServices





I/O HardwareAbstraction

Op

era

tin

g S

yste

m

Application

Software

Component

Application

Software

Component

Application

Software

Component

Application

Software

Component


Freescale‘s offering is based on AUTOSAR Basic Software

Microcontroller


Co

mp

lex D

river

Bas

ic S

oft

ware

Application Layer


MemoryServices

SystemServices





I/O Hardware

Abstraction

Op

era

tin

g S

yste

m

Application

Software

Component

Application

Software

Component

Application

Software

Component

Application

Software

Component

► AUTOSAR software „product“ packages from Freescale

• MCAL

• Operating System


AUTOSAR MCAL Product

Microcontroller

Hardware AD

C

DIO

Tim

er

I/O Drivers

PO

RT

Driver

AD

C D

river

DIO

Driver

PW

M D

river

ICU

Driver

PW

M

LIN

/ S

CI

CA

N

SP

I

Fla

sh

WD

T

GP

T

Microcontroller Drivers Communication DriversMemory Drivers

CA

N D

river

Inte

rnal F

lash D

river

Watc

hdog D

river

LIN

Driver

MC

U D

river

Fle

xRa

y™

Driver

GP

T D

river

SP

I D

river

MC

U

Pow

er

&

Clo

ck U

nit

PO

RT

S

Fle

xRa

y

Memory Hardware

Abstraction

Flash EEPROM Emulation

► MCAL drivers + Flash EEPROM Emulation, compliant to Autosar 2.1 or 3.0► Autosar 2.1/3.0 MCAL releases do not contain RAM Test module► All components configurable in any AUTOSAR-compliant configuration tool► Including plugins for EB tresos StudioTM


OS & System Services

Microcontroller


Co

mp

lex D

riv

er

Basic

So

ftw

are

(B

SW

)

Application Layer

Communication

Services

Memory

Services

System

Services





I/O Hardware

Abstraction

Op

era

tin

g S

ys

tem

Application

SoftwareComponent

Application

SoftwareComponent

Application

SoftwareComponent

Application

SoftwareComponent

System Services

• Provide functionality to be used by all other modules, e.g.,

diagnostic event manager (DEM), diagnostic error tracer (DET), operating system (OS)

• OS is a system service that is MCU dependent, i.e., has to be optimized for each MCU

• Other modules can be application and/or hardware dependent (e.g., ECU state manager)

AUTOSAR OS is OSEK/VDX™ OS plus:

• New core features

•Software and hardware counters

•Schedule tables with time synchronisation

•Stack monitoring

• Protection features

•Timing protection, memory protection and service protection

•OS applications, trusted and non-trusted code

•Protection hook

System Services

Co

mm

un

ica

tio

nM

an

ag

er

EC

U S

tate

Ma

na

ge

r

Fu

nction

Inh

ibitio

nM

an

ag

er

Watc

hd

og

Ma

na

ge

r

Dia

gno

stic E

ve

nt

Ma

na

ge

r

Dia

gno

stic E

rro

rT

race

r

Opera

ting S

yste

m

CRC Library


OSEK OS (all conformance classes)

Counter Interface

Schedule Tables

Stack Monitoring

Protection Hook

Timing Protection

Global Time/Synchronization Support

Memory Protection

OS Applications

Service Protection

CallTrustedFunction

Sca

lab

ility

Cla

ss 1

Sca

lab

ility

Cla

ss 2

Sca

lab

ility

Cla

ss 3

Sca

lab

ility

Cla

ss 4

� � � �

� � � �

� � � �

� � � �

� � �

� �

� �

� �

� �

� �

� �

AUTOSAR OS Scalability Classes 1–4


ElektroBit (EB) Tresos Studio

14

� EB tresos Studio is a easy-to-use tool for ECU standard software configuration, validation and code generation

� Full support for the AUTOSAR standard

� Full support for the Freescale AUTOSAR software and the EB tresos AutoCore

► Integrated, graphical user interface

► Based upon Eclipse and open standards

► Online-help and parameter-specific help


Parameter Description Files – EPD/EPC

Source: Elektrobit

EPD

EB tresos Studio

Configurator write

read

BSW

ModuleDescription

EB tresos Studio

Generator

c, hwrite

read

c, htemplates

read

BSW Module Configuration

GeneratedCode

Code

Templates

AUTOSAR Files

Elektrobit Files

Generated Files

Legend

read

EPC


Parameter Description Files – XDM

Source: Elektrobit

XDM

EB tresos Studio

Configurator write

read

BSW

ModuleDescription

EB tresos Studio

Generator

c, hwrite

read

c, htemplates

read


GeneratedCode

Code

Templates

AUTOSAR Files

Elektrobit Files

Generated Files

Legend

read

EPD

convert

XDM

EPC

import/export


Main Window

Node Outline

Error & ProblemMessages

ParameterInformation

EditorProject Browser

Source: Elektrobit


EPD

Parameter Description Files – XDM

Source: Elektrobit

EB tresos Studio

Config Editor write

read

BSW

ModuleDescription

EB tresos Studio

Generator

c, hwrite

read

c, htemplates

read


GeneratedCode

Code

Templates

AUTOSAR Files

Elektrobit Files

Generated Files

Legend

read

EPC

XDM

XDM

XDM is a proprietary format (EB)

providing enhanced usability

features during configuration with

EB tresos Studio.


EPD

Parameter Description Files – EPD/EPC

write

read

BSW

ModuleDescription

EB tresos Studio

Generator

c, hwrite

read

c, htemplates

read


GeneratedCode

Code

Templates

AUTOSAR Files

Elektrobit Files

Generated Files

Legend

read

EPC

EPD

EPC

Any otherAUTOSAR-compliant

EPD is the standard AUTOSAR

format. This allows the Freescale

Autosar software to be used with

any other Autosar GCE tool.

Config Editor


New Power Architecture

March, 2010

Solutions for Automotive Body Electronics



New Power Architecture: MPC560X

March, 2010

MPC560XB – Bolero for Body Electronics


► Power Architecture™: e200 Core• Key Characteristics

• Programming Model

• Auxiliary Processing Unit: Signal Processing Engine

• Memory Management Unit

• Cache

► Common Microcontroller System Features• Direct Memory Access

• Crossbar

• Memory Protection Unit

• Phase Lock Loop

• Power Control and Peripheral Clock Generation

• Boot Assist Module

• Memories

• Pad Configuration

• Interrupts

► Peripheral Example Overviews• Timed I/O: Timers

• Analog I/O: eQADC, ADC

• Serial I/O: LIN, CAN, FlexRAY

► Bolero Unique Features• ADC diagram block/functionality

• Lightning PWM Channels

• Bolero Roadmaps


Enabling More Integration

Benefits:

• Less modules, less cables

• Reduced weight, fuel efficiency

• Reduced manufacturing costs

• Better quality

• Lower total cost of ownership

CAN Gateway

Body Controller

(interior features +

lighting)

RF Receiver

(key, tires)Central Body

Domain

ControllerFuses Box

Replacement


32-bit Body Electronics MCU RoadmapA

pplic

ation P

erf

orm

ance / Inte

gra

tion

MPC5515S768KB Flash, 48 KB RAM5 CAN, 6 eSCI

MPC5516x1M Flash, 64KB RAMUp to 6 CAN, FlexRay, MLB

MPC5517x1.5M Flash, 80 KB RAMUp to 6 CAN, FlexRay, MLB

MPC5604B/C512KB Flash, 64KB Data flash3/6 CAN, 32/48KB RAM

MPC5606B (w/ eDMA)

1M Flash, 64KB Data Flash6 CAN, 80KB RAM

MPC5601D

128K Flash, 64KB Data Flash1 CAN, 16KB RAM

MPC5510

e200z1, eDMA

e200z0 optional48-66-80MHz

144/176LQFP208MAPBGA

130nm

MPC5514E/G512KB Flash

32K/64K RAM

e200z032, 48, 64MHz

64/100/144/176LQFP

90nm

MPC560xB/C

MPC5603B/C384KB Flash, 64KB Data flash3/6 CAN, 28-40KB RAM

MPC5605B (w/ eDMA)768KB Flash, 64KB Data Flash6 CAN, 64KB RAM

MPC5668G2MB Flash, 592KB RAMFlexRay, Ethernet, MediaLB

90nm

MPC5668G/EHigh performance gateways

Dual-core 200z6+z0, 116MHz @105C208MAPBGA

MPC5668E2MB Flash, 128KB RAM, 6 CAN, 12LIN

MPC5607B (w/ eDMA)1.5M Flash, 64KB Data Flash6 CAN, 96KB RAM

e200z4 or e200z4+z080-120MHz

MPC564xB/CMPC5646B/C

3MB Flash, up to 256K RAM,6 CAN, Flexray, Ethernet option

90nm

NOW 2010 2011

MPC5602D256K Flash, 64KB Data Flash

1 CAN, 20KB RAM


Available

Planned

Proposed

In Design

MPC5645B/C 2MB Flash, up to 256K RAM

6 CAN, Flexray, Ethernet option

MPC5644B/C1.5MB Flash, up to 192K RAM, 6 CAN, Flexray, Ethernet option


MPC5604B (Bolero 512K)

CROSSBAR SWITCH

32K SRAM

PowerPCTM

e200z0Core

VReg

Communications I/O System

Crossbar Slaves

Interrupt Controller

Crossbar Masters

Nexus 2+

JTAG

Debug

512KFlash

BootAssist

Module (BAM)

Oscillator

Memory Protection Unit (MPU)

System Integration

I/OBridge

3 FlexCAN

4LINFlex

1I2C

3 DSPI

FMPLL

CORE

• PowerPC e200z0 core running 48-64MHz

• VLE ISA instruction set for superior code density

• Vectored interrupt controller

• Memory Protection Unit with 8 regions, 32byte granularity

MEMORY

• 512Kbyte embedded program Flash, 64KByte data flash

• 64Kbyte embedded data Flash (for EE Emulation)

• Up to 64MHz non-sequential access with 2WS

• ECC-enabled array with error detect/correct

• 32Kbyte SRAM (single cycle access, ECC-enabled)

COMMUNICATIONS

• 3x enhanced FlexCAN

• 64 Message Buffers each, full CAN 2.0 spec

• 4x LINFlex

• 3x DSPI, 8-16 bits wide & chip selects

• 1x I²C

ANALOG

• 5V ADC 10-bit resolution

TIMED I/O

• 16-bit eMIOS module

OTHER

•CTU (Cross Triggering Unit) to sync ADC with PWM Channels

• Debug: Nexus 2+

• I/O: 5V I/O, high flexibility with selecting GPIO functionality

• Packages: 100LQFP, 144LQFP, 208MAPBGA (Development only)

• Boot Assist Module for production and bench programming

PIT 4ch 32b

MCM

Power Mgt

Standby RAM

64K Data

Flash

36 chADC10bit

eMIOSLite6ch IC/OC50ch PWM

CTU


MPC5607 (Bolero 1.5M)

CROSSBAR SWITCH

96K SRAM

PowerPCTM

e200z0Core

VReg


Crossbar Slaves


Crossbar Masters

Nexus 2+

JTAG

Debug

1.5MFlash

BootAssist

Module (BAM)

Oscillator


System Integration

I/OBridge

6 FlexCAN

10LINFlex

1I2C

6 DSPI

FMPLL

CORE

• PowerPC e200z0 core running at up to 64MHz

• VLE ISA instruction set for superior code density

• Vectored interrupt controller

• Memory Protection Unit with 16 regions, 32byte granularity

•MEMORY

• 1.5M byte embedded program Flash

• 64Kbyte embedded data Flash (for EE Emulation)

• Up to 64MHz non-sequential access with 2WS

• ECC-enabled array with error detect/correct

• 96Kbyte SRAM (single cycle access, ECC-enabled)

COMMUNICATIONS

• 6x enhanced FlexCAN

• 64 Message Buffers each, full CAN 2.0 spec

• 10 x LINFlex

• 6 x DSPI, 8-16 bits wide & chip selects

• 1 x I²C

ANALOG

• Up to 52 ch 5V ADC (16x12-bit, 36x10-bit) resolution, CTU (Cross Triggering Unit) to sync with PWM Channels

TIMED I/O

• 16-bit eMIOS module, 64ch.

•Counter / OPWM / IC/OC– 10ch

•O(I)PWM / OPWFMCB / IC/OC–7ch

•O(I)PWM / IC/OC - 19 ch

•OPWM / ICOC – 28 ch

OTHER

• 32 Channel DMA Controller

• Debug: Nexus 2+

• I/O: 5V I/O, high flexibility with selecting GPIO functionality

• Packages: 100LQFP, 144LQFP, 176LQFP, 208MAPBGA (TBD)

• Boot Assist Module for production and bench programming

PIT 4ch 32b

MCM

Power Mgt

Standby RAM

64K Data

Flash

DMAC

TUUp to 52 ch

ADC16x12bit, 36x10 Bit

eMIOS64ch, 16 bit


Power Architecture: e200 Core


Power Architecture e200 Core Family Key Characteristics

►Synthesizable Power Architecture™ cores with Power ISA 2.03

►Additional supported instructions

• SPE – Signal Processing Engine: DSP, SIMD and vector floating point

• VLE – Variable Length Encoding: for improved code footprint

►Standard interfaces:

• AMBA bus, which has a large following in the licensable-IP community

• Nexus debug interface (ISTO 5001)

►Leverages Power Architecture tools and software ecosystem

• Hardware and software development tools are available.

• Development support is available from leading tools vendors providing

compilers, debuggers and simulation development environments.


e200 Power Core Platform

Increased Integration / Advanced Process Technology

Perf

orm

an

ce

Z0/Z1•First embedded

PowerPC processor

•Separate products for

embedded and computing markets

Z3/Vector•32 bit PowerPC Book

Single-issue, 4-stage

•32-Bit AMBA AHB bus

•SPE and SPFP APUs•16-entry unified MMU

•Optional Harvard cache

(4 KB – 16K)

Z4•32 bit PowerPC Book

Single-issue, 5-stage•32-Bit AMBA AHB bus

•SPE and SPFP APUs

•16-entry unified MMU

•Optional Harvard cache

(4 KB – 16K)

Z6•32 bit PowerPC Book E

•Single-issue, 7-stage

•64 bit AMBA AHB Bus•EFP and SPE APUs

•Unified 32KB Cache

•8-way set-associative

•32-entry unified MMU

Z7 preliminary•32 bit PowerPC Book E

•Dual-issue, 10 stage

•64/128-Bit bus•Single Precision FP and

SPE SIMD APUs

•Harvard L1 caches and

optional L2

•Large MMU

Future

Versions•Next Generation

•64 bit, 3+ GHz

86XX

Software Compatib

le Architecture

*

(Power Archite

cture driven High Perfo

rmance Applic

ations)

Original Slide by J. Shockey

► Highly modular core • add DSP & FP, cache,

• pre-fetch buffers

• packaging, module library, peripherals

• single and dual core options

► Cost reduction through maximum re-use• same tools, drivers, application code

• cross-application platform with 1 core

• 60MHz – 2 x 300MHz, 256K – 8MB


e200z Core Roadmap

2004 2005 2006 2007

Perf

orm

ance /

Featu

res

Powertrain

&

Chassis

Body

Electronicse200z380MHz

SIMD

4-stage pipeline

FPU

VLE

e200z6200MHz

SIMD

7-stage pipeline

FPU

VLE

e200z6144MHz

SIMD

Up to 32k cache

FPU

e200z180MHz

4-stage pipeline

VLE

7-stage pipeline

Up to 32k cache

e200z7266MHz

SIMD

10-stage pipeline

FPU

Dual Issue /VLE

Up to 32k cache

e200z080MHz

4-stage pipeline

VLE Only

This document contains forward-looking statements based on current expectations, forecast and assumptions of Freescale that involves risk and uncertainties. Forward looking statements are subject to risk and uncertainties associated with Freescale business that could cause actual results to vary materially from those stated or implied by such forward-looking statements.

e200z4120MHz

SIMD

5-stage pipeline

FPU

Dual Issue / VLE

Up to 16k cache


Core DMIPS/MHz

e200 z4d 2.79

e200 z7 2.42

e500 v2 2.40

SH-2A 2.40

QCOM Scorpion 2.10

Cortex A8 2.00

Cortex A9 2.00

IBM 464 2.00

e300 1.99

MIPS 74k 1.80

Cortex R4 1.60

e200 z1 & z3 1.60

MIPS 4K 1.50

Tri-Core 1.50

SH-2 1.3

Cortex M3 1.25

Dhrystone Comparative Performance


Variable Length Encoding (VLE)

► VLE is an extension to the existing 32bit Power™ Book E instruction set.

► VLE instruction set includes16-bit and 32-bit VLE instructions

► VLE and Power™ codecan be mixed in the application by using separate MMU pages

► The e200z0 core only uses VLE instructions

0

0.2

0.4

0.6

0.8

1

1.2

Code Size Performance

Power ISA

VLE


Auxiliary Processing Unit: Signal Processing Engine (SPE)

►SPE is an Auxillary Processing Unit (APU) that provides signal processing capabilities

• Aimed specifically at DSP operations, such as filters and FFTs

►Key SPE Features:

• Single Instruction Multiple Data (SIMD) functionality

• Includes Embedded Floating Point APU

• Support for the following data types:

• 32-bit fractional

• 32-bit integer

• Single precision floating point

• 16-bit fractional

• 16-bit integer


rA

rB

rDop op

0 31 32 63

evfs*

r3

r4

0 31 32 63

85 46

13 21

77 34

Register File

rA

rB

rD

op op

0 31 32 63

evfs*

r3

r4

r5

add

0 31 32 63

85 46

13 21

77 67

add r5, r3, r4

Classic PowerPC: add r5, r3, r4

rA

rB

rD

op op

0 31 32 63

evfs*

r3

r4

r5

add

0 31 32 63

85 46

13 21

98 67

evadd r5, r3, r4

add

SPE: evadd r5, r3, r4

r5

Single Instruction Multiple Data (SIMD)

SPE extends the

ordinary Book E 32

bit registers to be 64

bits in size

Ordinary PowerPC

instructions operate

as usual just on the

bottom 32 bits,

leaving the top 32 bits

untouched

SPE instructions do the

specified operation on

the bottom 32 bits and,

in parallel, on the top

32 bits. So two

independent operations

are executed by the one

instruction


TLBTLB Entry 0TLB Entry 1TLB Entry 2TLB Entry 3

…TLB Entry 31

Effective virtual Address(32-bits)

Real Address(32-bits)

Page0

Page3

Page2

Page1

PhysicalMemoryYellow: Flash

Green: Peripherals

Blue: SRAM

MMU

Core

…

…

…

cal_var

Memory Management Unit (MMU)

►Memory must be defined in the MMU for Core access

►MMU does not control accesses from EBI, eDMA, or NEXUS

• Nexus may read MMU & change the settings on the fly (in some devices)

►Memory space is divided into up to 32 pages, each having:

• Defined size (1k, 2k, 4K, 8k,16K, 64K, 256K, 1M …)

• Address base, Effective Page Number (EPN), which is translated to a different base,

Real Page Number (RPN)

• Permission control

• Memory and cache attributes

►Each page is created by an entry in the Translation Lookaside Buffer (TLB)

►ECU calibration does not require any change in the software

• As required by OEMs same build is used for ECU calibration

►e200 MMU is Autosar compatible.

Memory Management Unit


Calibration Example Using The MMU

► Use the MMU to switch between any number of calibration banks.

► MMU solution requires a very small amount of core intervention when switching banks.

Internal FLASH

Calibration #1

External SRAM

Calibration #3

MMU selects which of

many calibrations the

software sees at a fixed

address

External Memory

Emulator

Calibrations #5&6

External SRAM

Calibration #4

Calibration

Effective Address

Physical Address

Internal FLASH

Calibration #2MMU


Common Microcontroller System Features


•The crossbar switch allows two bus masters to simultaneously connect to different bus slaves

• In addition, e200z1 has a private connection to flash module for instructions

•The eDMA offloads the processor tasks for data movement, especially for communications

•Optional second processor, e200z0

•Smart peripherals

Architecture Performance Support

Flash

e200z1 eDMAController

SRAMIP Bus i/f to peripherals

and I/Os

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. ARM is the registered trademark of ARM Limited. ARM7 is the trademark of ARM Limited.© Freescale Semiconductor, Inc. 2004

e200z0

CP

U 1

In

str

uc

tio

ns

Crossbar

Example snapshot


Crossbar Switch► Simultaneous transfers between

independent master and slave ports

► Programmable master priorities on a per-slave port basis

• Fixed and Round-Robin arbitration priorities

► Parking on slave ports• Explicit, park on last master to access

that slave and none (low power parking)

► 32-bit internal address, 32 or 64-bit internal data paths

► Master Ports• Core complex Load/Store port• Core complex Instruction port• DMAs• FlexRay• EBI

► Slave Ports• Flash• SRAM• Peripheral Bridge (AIPS)

AHB


Memory Protection Unit (MPU)Memory Protection Unit Overview

►Unlike MMU, provides access control for DMA,

EBI, and FlexRAY, in addition to core accesses

►Full compliance with Autosar Class 4

►Protects slaves against erroneous master accesses

►Supports concurrent accesses between masters

►Splits the memory space into regions

• 8 or 16 regions

• with a granularity of up minimal 32 bytes

►Assigns access rights for each region• For supervisor (read, write, execute)

• For user mode (read, write, execute)

• Flexray: read and write attributes only

►Regions can be assigned per task or group of tasks• Patented scheme allowing static MPU configuration in

safety systems

►2 supported MPU schemes

• MPU entries reload on task change

• Fully static configuration

MPU

Cro

ssbar

Transfer Error

Master#

(optional PID)

Maste

rs

Sla

ves


eDMA Features• Up to 64 DMA channels implemented

• Each channel source is selected by

• Software - Sources are NOT pre-assigned to peripherals

• Hardware - Sources are not pre-assigned to peripherals

• One DMA engine services all channels

• Devices may have multiple DMA engines

• DMA requests can come from:

• Peripheral (e.g., eQADC)

• Software command

• Programmable Interrupt Timer (PIT)

• Transfer Control Descriptors define each channel’s transfer

• Optional generation of interrupt request upon

• Reaching half of the transfer

• After completion of the transfer


Software Selection Of A DMA Source

DMAChannel

Mux

Source # 0

Source # 1

Source # 2

Source # n

PeripheralsDMA Channel #0

DMA Channel #1

DMA Channel # 15

.

.

..

.

.

.

.

.Always Enabled

# n+1

# 32 or 64

• Software selects which DMA sources connect to the 16 DMA channels

• DMA request for channels can be initiated by:

• A peripheral (example: ADC conversion result ready to be put into queue)• Software (example: set a bit to initiate a block move)• Periodic Interval Timer (example: enable periodic transmit of latest pending SPI data)

• Periodic Interval Timer available to 8 of the 16 channels (DMA channel 0 to 7)

Disabled


DMA Channel Mux Sources (shown for MPC5604P)

DMA MuxSource Input #

#sources

DMA Source

0 1 Channel Disabled

1 – 8 8 4 DSPIs: TX and RX

9 -13 5 CTU, CTU FIFO 1:5

14, 15 2 FlexPWM 0: WR, RD

16 - 19 4 eTimer 0 channels 0:1 and eTimer 1 channels 0:1

20 – 21 2 ADC 0:1

22 - 30 Always Enabled -With PIT to generate periodic DMA

- w/o PIT for continuous DMA transfer


FMPLL Block Diagram (MPC563xM)

► fsys = fref x (MFD + 4) ----------------------------

(PREDIV + 1) x 2 RFD

PRE

DIV

Filter

ICO

(Current

Controlled

Osc.)

RFD

MFD

fref(xtal)

feedbackclk

fsysPFD

(Phase

Freq.

Detector)

Charge

Pump

Lock

Detect

Loss of

Clock Detect

LOCK

Loss Of Clock

FM

Mod.

Control

fico

Default Fsys = 1.5 x Fextclk

unless PLLCFG2 = 1, then Fsys = 0.75 x Fextclk


Peripheral Clock Generation

► To conserve power, many peripherals do not have a

clock signal after reset.

• A bus error will occur when attempting to access

peripherals without clocks.

► Software must initialize in two ways:1. Peripheral clock gating on a mode basis.

� Based on ME_RUN_PCx, ME_LPx and various ME_PCTLx registers

2. Clock generation on a peripheral or peripheral set basis.


Peripheral Clock Generation Examples


Boot Assist Module (BAM) Overview

►The Boot Assist Module is a block of read-only memory which

assists the boot process.

►Typically it is executed after RESET

►Features:

• Locates and detects application boot code

� Searches for a BOOTID value in pre-assigned locations in flash

• Can allow serial download of code into internal SRAM for execution

� Uses FlexCAN or eSCI for MPC563xM

� Uses FlexCAN or LINFlex for MPC560xB / P / S

• Can allow boot from external flash (if external bus is implemented)

• If an MMU is implemented, MMU pages are configured processor resources

• Censorship protection for internal flash module


SIU Pad Configuration

► Each pad has its own 16-bit Pad Configuration Register (PCR)

• Registers SIU_PCR0 to SIU_PCR230

• Register number corresponds to GPIO number

• Not all pads have all bit fields

• BAM will alter defaults for some pads

► Software must configure pin assignments to be other than their common default GPIO assignment.

► MPC56xxB / P / S also includes registers to select which pin input is connected to which peripheral.

• Allows a single input to be routed to 2 peripherals

• Pad Selection For Multiplexed Inputs (SIU_PSMIx)


Pad Configuration Example: Assign EMIOS Channel 0

Primary Function: EMIOS chan. 0

Alternate Function: ETPU A chan. 0

[reserved]

GPIO: GPIO[179]

11

10

01

00

SIU_PCR179[PA]

(Pad Assignment – can be 1, 2 or 3 bits)

Pad

MPC5553/MPC5554 Microcontroller Reference Manual,

Table 2-1 MPC5553 Signal Properties:


SIU_PCR: Pad Configuration Registers

Bit Field Name Symbol Description

Pad Assignment PA Assigns pad as GPIO (common default),

alternate or primary function

Output Buffer Enable OBE If pad can be input or output, enables as output.

Input Buffer Enable IBE If pad can be input or output, enables as input.

Tip: If pad is configured as an output, the pad

state can be read when IBE is also enabled..

Drive Strength Control DSC** Output drive strength of 10, 20, 30 or 50 pf

Open Drain output Enable ODE Output has open drain

Input Hysteresis HYS Input has Hysteresis (for noise, but slower)

Slew Rate Control SRC** Output has minimum, medium or max. slew rate

Reset default is min. slew rate (slowest transition)

Weak Pull down/up Enable WPE* Enables selected pull down/up

Weak Pull down/up Select WPS* 0= pull down, 1 = pull up

*WPE and WPS override initial pullup/down configured at reset by WKCFG for eMIOS/eTPU.

** DSC applies to fast pad types (example: external bus), SRC applies to medium & slow

*


Interrupt Generation

► Interrupts are handled between:

• The Interrupt Controller (INTC)

• The Core

► The Interrupt controller provides a mechanism to service non core

based interrupts

• Software selects one of 16 priority levels for each interrupt

• Interrupts are serviced in one of 2 ways:

� Software vector mode (which conforms to Power Architecture technology)

� Hardware vector mode


Peripheral Example Overviews


PIT Timer Module

► Independent AutoSAR system timers

►Down counting with auto reload

►32 bits wide

►Most channels Clocked by system clock

►1 channel clocked by crystal clock

• Operates in stop mode

• Used to wake-up CPU

► Interrupt and trigger on each channel

• Ideal tick source for operating system

►Channel outputs can trigger eQADC queues


eMIOS Timer Module

• 24 Independent Channels• “Unified” – all have same output and input time function (mode) capability

• 24-bit wide counter buses• Global: Counter bus A – Driven by channel 23 or eTPUA or eTPUB

• Local: Counter buses B, C, D – Driven by channels 0, 8, 16 for channels 0-7, 8-15, 16-23

• Internal: Internal Counter – inside the channel.

• Output Pins can be disabled by input or output events on other eMIOS Channels• Any one of channels 8, 9, 10 or 11 disables any user selected eMIOS

• eMIOS Channels 8-11, 20-23 provide disable control to 8 groups of 8 channels on eTPUA, eTPUB

Chan 0

Bus B

Chan 7

Bus A

Chan 8 Chan 15 Chan 16 Chan 23

eTPUA

eTPUB

Chan

8-1

1

Output disable control

to eTPUA, eTPUB

Bus DBus C

Chan

20

-23


eMIOS Modes of OperationTimer Mode

Modulus Counter1,2 (does not use pin)

Input Channel Modes

Single Action Input Capture1

Input Pulse Width Measurement1

Input Period Measurement1

Pulse/Edge AccumulationPulse Edge Counting

Quadrature Decode

Windowed Programmable Time Accumulation Modulus Counter

Output Channel Modes

Single Action Output Compare1

Double Action Output Compare1

Output Pulse Width Modulation1,2

Output Pulse Width and Frequency Modulation2

Center Aligned Output Pulse Width Modulation with dead time insertion2

1 Mode supported on MPC5002 Buffered mode versions avaialble except for MPC5554 and MPC5552 input modes

Note: As a supplement to the reference

manual, see EB651: MPC5500 eMIOS –

Avoiding Unexpected Module Operation


eQADC Features

► Two independent on - chip ADC’s

• 12 bit resolution

• Single-ended signal range from 0 to 5V

• 4 pairs of differential analog input channels

• Sample times of 2 (default), 8, 64 or 128 ADC clock cycles

• Right- justified unsigned and signed result formats

• Provides time stamp information when requested

Target

Accuracy

Max. Rate

ADC_CLK

Conversion

Type

Min. # of

ADC_CLKs

Conversion

Rate

Conversion

Time

10 bit 6 MHz Differential 15 400 K /sec 2.5 usec

Single Ended 16 375 K / sec 2.67 usec

8 bit 12 MHz Differential 15 800 K /sec 1.25 usec

Single Ended 16 750 K /sec 1.33 usec


eQADC Command/Data Flow

Command Queue 0

OOO

Command Queue 1

Command Queue 5

Command FIFO 0

OOO

Command FIFO 1

Command FIFO 5

A/DBN 0

A/DBN 1

ResultFIFO 0

OOO

Result FIFO 1

ResultFIFO 5

ResultQueue 0

OOO

Result Queue 1

Result Queue 5

DMA

DMA

DMA

DMA

DMA

DMA

Trigger (0)

Trigger (1)

Trigger (5)

• Each CFIFO and RFIFO are hard-wired to individual DMA channels

• Each result can return through any RFIFO

Pu

sh

Re

g. 5

Pu

sh

Re

g. 1

Pu

sh

Re

g. 0

Po

p

Re

g. 0

Po

p

Re

g. 1

Po

p

Re

g. 5


LINFlex(LIN and UART)Features:

• Supports LIN protocol version 1.3, and 2.0

• UART mode

� 7/8-bit data, parity/no-parity, 1 or 2 stop bit

� MSB / LSB first

LIN Management

• Initialization, Normal and Sleep

• Maskable interrupts

• Wake-up event on dominant bit detection

• 8-bit counter for time-out management

• Software-efficient data buffer interface mapping at a unique address space

LIN Master Mode

• Autonomous message handling

• Once the software has triggered the header transmission, no further intervention needed:

� until the next header transmission request in transmission mode

� until the checksum reception in reception mode

LIN Slave Mode

• Software intervention needed only to:

� Trigger transmission or reception depending on the identifier,

� Fill the buffer (transmission) or get data from buffer (reception).

• If Filter mode is available for Slave mode (option), Software intervention needed only to:

� Fill the buffer in transmission,

� Get data from buffer in reception.

UART mode

• Full duplex; Character length 7 & 8 bits; opt parity, 1 or 2 stop bits

• 4 byte Tx and Rx buffers

• 3 interrupt sources : error, Rx, Tx MSB / LSB first

• Transmit/receive data inversion at pin level

SCI / LINSCI / LIN


FlexCAN: Architecture with MPC5510 FlexCAN

► Each buffer has it’s own receive ID mask (up to 3 diff IDs)

► Buffers 0-7 can be used to implement an 8 frame Rx FIFO

Rx ID Mask 63

Tx Shifter

Rx Shifter

Rx ID Mask 0

BUFFER 14

ID

DATA

TIME STAMP

DATA LENGTH

BUFFER 15

BUFFER 13

IRQs

SERIAL BUFFERSCANTx

64 Transmit/Receive

Message Buffers

Transparent to user

ID

DATA

TIME STAMP

DATA LENGTH

ID

DATA

TIME STAMP

DATA LENGTH

BUFFER 62

ID

DATA

TIME STAMP

DATA LENGTH

BUFFER 63

20

CANRx

29

29

CONTROL

.

.

.


Flexcan: Architecture - Combining FlexCAN Modules

Message Buffer 0

Message Buffer 1

.

.

.

Message Buffer 63

FlexCAN A

(Transmit

and Receive)

Message Buffer 0

Message Buffer 1

.

.

.

Message Buffer 63

FlexCAN B

(Receive only)

Transceiver

Vehicle

CAN

Bus

CNTXA

CNTXB

CNRXA

CNRXB• Benefit: More buffers available

for one CAN bus.

• CNTXB is not connected.

(Otherwise FlexCAN B would

acknowledge FlexCAN A

transmissions)

CANH

CANL


MPC560xB Family Unique Features


INJECTED conversionPITPeriod Interrupt

e200 z0h Power Architecture

CORE

NORMAL or SW INJ. conversion

INTCInterrupt Controller

CTUCross Triggering

Unit

eMIOSEnhanced Modular

IO System

48 49

CTU conversion

End of CONV.End of CHAINEnd of INJ. End of CTU WATCHDOG

e200 z0h Power Architecture

CORE

NORMAL or SW INJ. conversion

INTCInterrupt Controller

MPC5604B – Bolero 512K

ADC10-bit

64 channel

16 ANS(Standard)

TUE

+/-3 counts

ANP(Precise)

TUE

+/-2 counts

4 32

3

ANX(Muxed)

TUE

+/-3 counts

MU

X x

4

16


Lighting - PWM Channels

Ch 0

period n period n + 1

Ch 1

Ch 2

Ch 3

Ch n-1

Ch n

10

0H

z c

ha

nn

els

(n

+1

) 0% shift, 40% duty cycle

5% shift, 40% duty cycle


OFF



period n period n+1 period n+2

Ch 0

Ch 1

Ch 2

Ch 3

Ch n-1

Ch n

16

0H

z c

ha

nn

els

(n

+1

) 0% shift, 15% duty cycle



OFF




eMIOS - OPWMT Mode

Period: the period of the PWM is defined by a Modulus Counter channel.

A1 Value: define the leading edge (or shift) of the PWM channel. Buffering is not needed as the value of the shift must not changed on the fly.B1 Value: define the trailing edge (or duty cycle) of the PWM channelB2 Value: buffered value of trailing edgeB1 update: transfer from B2 to B1 takes place at A1 matchEDPOL: define the output polarityC1 Value: define the sampling point for the analog diagnostic. It can be configured anywhere within the PWM period.

Period

B1

C1

A1

Output Pin

Match A1

Match C1Match B1


32-bit Body Electronics MCU RoadmapA

pplic

ation P

erf

orm

ance / Inte

gra

tion

MPC5515S768KB Flash, 48 KB RAM5 CAN, 6 eSCI

MPC5516x1M Flash, 64KB RAMUp to 6 CAN, FlexRay, MLB

MPC5517x1.5M Flash, 80 KB RAMUp to 6 CAN, FlexRay, MLB

MPC5604B/C512KB Flash, 64KB Data flash3/6 CAN, 32/48KB RAM

MPC5606B (w/ eDMA)

1M Flash, 64KB Data Flash6 CAN, 80KB RAM

MPC5601D

128K Flash, 64KB Data Flash1 CAN, 16KB RAM

MPC5510

e200z1, eDMAe200z0 optional48-66-80MHz144/176LQFP208MAPBGA

130nm

MPC5514E/G512KB Flash

32K/64K RAMe200z0

32, 48, 64MHz64/100/144/176LQFP

90nm

MPC560xB/C


MPC5605B (w/ eDMA)768KB Flash, 64KB Data Flash6 CAN, 64KB RAM

MPC5668G2MB Flash, 592KB RAM

FlexRay, Ethernet, MediaLB

90nm

MPC5668G/EHigh performance gateways

Dual-core 200z6+z0, 116MHz @105C

208MAPBGAMPC5668E2MB Flash, 128KB RAM, 6 CAN, 12LIN

MPC5607B (w/ eDMA)1.5M Flash, 64KB Data Flash6 CAN, 96KB RAM

e200z4 or e200z4+z080-120MHz

MPC564xB

Bolero Gateway 2MB2Mb Flash, 192K RAM, 64K Dataflash6 CAN, 10 LIN, 6SPI. FR, Ethernet

Bolero Gateway 4MB

4Mb flash, 256K RAM, 64K Dataflash6 CAN, 12 LIN, 6SPI. FR, Ethernet

90nm

NOW 2010 2011

MPC5602D256K Flash, 64KB Data Flash1 CAN, 20KB RAM


Available

Planned

Proposed

In Design

Samples: Feb 2010

Qual:Q1-2011

Samples: May 2009

Qual: Q3-2010


Data Flash

Code Flash64Kb 64Kb 64Kb 64Kb 64Kb 64 Kb Technology

4Mb5647

Up to 256K

5647

Up to 256K

5647

Up to 256K90nm(TBC)

120 MHz

125oC Ta

3Mb5646

Up to 256K

5646

Up to 256K

5646

Up to 256K

2Mb5645

Up to 192K

5645

Up to 192K

5645

Up to 192K

1.5Mb5607

Up to 96K

5607

Up to 96K90nm

64 MHz

125oC Ta

1Mb5606

Up to 80K

5606

Up to 80K

768K5605

Up to 64K

5605

Up to 64K

5605

Up to 64K

512K5604

Up to 48K

5604

Up to 48K90nm

64 MHz

125oC Ta

384K5603

Up to 40K

5603

Up to 28K

256K5602B/C

Up to 32K

5602B/C

Up to 24K

256K5602D

Up to 20K

5602D

Up to 20K90nm

48 MHz

125oC Ta128K

5601D

Up to 16K

5601D

Up to 16K

Pin Out64 100 144 176 QFP

208 (*1) 256(*1) BGA

Device

Ram SizeCommitted Proposed

Bolero Family Line-up

*1= package subject to confirmation. All proposed parts features subject to change with out notice.


Cross Family Compatibility

CROSSBAR SWITCH

40K

SRAM

PowerPCTMe200z0

Core

VReg


Crossbar Slaves


Crossbar Masters

Nexus

JTAG

Debug

512KbFlash Boot

AssistModule

(BAM)

Oscillator

System Integration

DMARTC

I/O

Bridge

1or2

FlexCAN

1

eSCI

Mc T

imer

3DSPI

FMPLL

FlexRay

Mc T

ime

r

Mc T

ime

r

Mc P

WM ADC I/F

10 bit650 nsec

S&H S&H

mux mux

CROSSBAR SWITCH

40K

SRAM

PowerPCTMe200z0

Core

VReg


Crossbar Slaves


Crossbar Masters

Nexus

JTAG

Debug

512KbFlash Boot

AssistModule

(BAM)

Oscillator

System Integration

DMARTC

I/O

Bridge

1or2

FlexCAN

1

eSCI

Mc T

imer

3DSPI

FMPLL

FlexRay

Mc T

ime

r

Mc T

ime

r

Mc P

WM ADC I/F

10 bit650 nsec

S&H S&H

mux mux

CROSSBAR SWITCH

32KSRAM

PowerPCTM

e200z0

Core

VReg


Crossbar Slaves

Interrupt

Controller

Crossbar Masters

Nexus

JTAG

Debug

512KbFlash Boot

AssistModule

(BAM)

Oscillator


System Integration

DMA

ReadyRTC

I/O

Bridge

3

FlexCAN

4

LINFlex

32 ch

ATD12bit

eMIOSLite

8ch IO

36ch shiftPWM

3

DSPI

FMPLL

2

I2C

Power Sw

PIT 4ch 32b

MCM

CROSSBAR SWITCH

48K

SRAM

PowerPCTMe200z3

Core

SIMDMMU

VReg


Crossbar Slaves

Interrupt

Controller

Crossbar Masters

Nexus

JTAG

Debug

1Mb

Flash Boot

Assist

Module

(BAM)

Oscillator

System Integration

DMARTC

I/O

Bridge

2

FlexCAN

2

eSCI

32 ch

ATD

12bit

eMIOSLite

24ch

2

DSPI

FMPLL

eTPU

32 ch.

2.5K Code

RAM

12K Data

RAM

Ca

l B

us I

nte

rfa

ce

CROSSBAR SWITCH

48K

SRAM

PowerPCTMe200z3

Core

SIMDMMU

VReg


Crossbar Slaves

Interrupt

Controller

Crossbar Masters

Nexus

JTAG

Debug

1Mb

Flash Boot

Assist

Module

(BAM)

Oscillator

System Integration

DMARTC

I/O

Bridge

2

FlexCAN

2

eSCI

32 ch

ATD

12bit

eMIOSLite

24ch

2

DSPI

FMPLL

eTPU

32 ch.

2.5K Code

RAM

12K Data

RAM

Ca

l B

us I

nte

rfa

ce

CROSSBAR SWITCH

64KSRAM

PowerPCTM

e200z0

Core

External

Bus

(208MAPBGA)

VReg


Crossbar Slaves

Interrupt

Controller

Crossbar Masters

Nexus

JTAG

Debug

1MbFlash Boot

AssistModule

(BAM)

Oscillator


System Integration

DMA

DisplayInterface

UnitRTC

I/O

Bridge

2

CAN

2

LIN

Flex

16 ch

ATD10bit

6

gaugedrivers

eMIOSLite

24 ch.

2I2C

3

DSPI

so

un

d

40x4

LCD

FMPLL

Video

RAM

(tbd)

CROSSBAR SWITCH

64KSRAM

PowerPCTM

e200z0

Core

External

Bus

(208MAPBGA)

VReg


Crossbar Slaves

Interrupt

Controller

Crossbar Masters

Nexus

JTAG

Debug

1MbFlash Boot

AssistModule

(BAM)

Oscillator


System Integration

DMA

DisplayInterface

UnitRTC

I/O

Bridge

2

CAN

2

LIN

Flex

16 ch

ATD10bit

6

gaugedrivers

eMIOSLite

24 ch.

2I2C

3

DSPI

so

un

d

40x4

LCD

FMPLL

Video

RAM

(tbd)

Monaco(Powertrain)

Pictus/Tokay(Airbag/Steering)

Bolero(Body)

Spectrum(Instrument Cluster)

3232--bit standard architecture adopted across all product familiesbit standard architecture adopted across all product families

� Maximum IP reuse

� Faster time-to-market

� Reduced risk

� Leverage software and tools investments


Tools


RAppIDTime to Market Improvement for the MPC560xB/C Family

RAppID application, initialization, and documentation software

• Comprehensive Initialization of MPC560xB/C

• GUI based tool for easy and fast development of initialization code.

• Automatic report generation of Peripheral and Register settings.

• Efficient C and Assembly code generation for a multitude of compilers like CodeWarriorTM, Diab(WindRiver), and GreenHills.

• On-line documentation and built-in tool tips for ease of use

• Performs consistency checks to eliminate mistakes and inconsistencies.

• C code and Documentation templates customizable as a service.

• Supports multiple initialization strategy code generation.


Pin Allocation Wizard - Screenshot


Fully enabled

RAppID MPC5516

CodeWarrior


Development Tools – An Existing Ecosystem

Compilers Debuggers Simulators Eval Boards

Initialization

Tools

Modeling and

Code

�(v2.2) works w/ any

debugger�

� � �

� �

�

� �

� �

�

�

�

�

CodeWarrior

Green Hills

Wind River

GNU

dSpace

MathWorks

Lauterbach

iSystem

P&E Micro

RAppID Init


New Power Architecture

March, 2010

Solutions for Automotive Body Electronics



New Power Architecture: MPC560X

March, 2010

MPC560XS – Spectrum for Clusters


► Common Microcontroller System Features• Building Block Diagram

• DCU

► Quad SPI Interface

► Sound Generation

► Software Librarles

► Software / Tools

► Graphic Application Concept Design


DIS MCU Roadmap

Applic

ation P

erf

orm

ance / Inte

gra

tion

64K

128K

S12HZStepper Motor,

LCD drive

25MHz80,112 pin

(ROM 32K-256K

512K

256K

S12XHZStepper Motor,LCD drive

40MHz XGATE

112,144 pin

384K

256K

Stepper Motor, LCD drive

32MHz

100,64 pin

Production

Proposed

Committed

MPC560xS

512KB

Z0h CPU @ 64MHzDCU on 1MB & 768K

Up to 160KB GRAM


144 / 176 pin

1MB

768KB

256KB

MPC564xS

2MBZ4d CPU @ 120MHz

DCU (TFT Display Driver)

Graphics Accelerator

1MB of GRAMStepper Motor Drive

176 / 208 QFP, 324 BGA

MPC5121eE300 @ 400MHz

OpenGL ES1.1 Accelerator

Up to XGA displayExternal Flash & DRAM i/f

400 BGA

800 MIPs

i.MX35GARM1136JF-S CPU @ 400MHz

Open VG 1.1 2D Graphics AcceleratorIp to SVGA display

External Flash & DRAM i/f

400 BGA

400 MHz

i.MX511200 MIPS

Coretex A8 600MHzOpenVG1.1 & OpenGL2.0 Accel

Up to WXGA display


530 BGA

S12HY

32K

64K

48K

128K

256K

Stepper Motor,

LCD drive

32MHz112, 144 pin

0.18um

90nm

0.25um

0.25um

90nm

Sin

gle

chip

In

str

um

ent

clu

ste

rH

igh e

nd

Multim

ed

ia M

CU

’s

1MB


MPC5606S: Spectrum 1M (64MHz)

CROSSBAR SWITCH

48KSRAM

PowerTM

e200z0hCore

QuadSPI Serial Flash Controller

VReg


Crossbar Slaves


Crossbar Masters

Nexus

JTAG

Debug

1MbFlashBoot

AssistModule (BAM)

Oscillator


System

Integration

16chDMA

Display Control Unit

RTC/32kHz

I/OBridge

2 FlexCAN

2LINFlex

16 chATD10bit

6 Gauge Drivers

eMIOS24 ch

4I2C

3 SPI

Stall Detect

40x4 LCD

FMPLLx2

160KGraphicsSRAM

RGB / Control

Sound

Generation

Power Management

4x16k EEE

PDI

General Characteritics:• PPC e200z0h Core

• 1M FLASH with ECC• 4x16k EEPROM Emulation block with ECC• 48k SRAM with ECC• 16 channel DMA• Memory Protection Unit (12 regions)

• Voltage Regulator with external ballast transistor• Real Time Counter + 32kHz crystal oscillator• Watchdog, Periodic Interrupt Timer, System Timer

• 4-16MHz crystal oscillator

• Frequency Modulated PLL (x2)• Nexus 2+ / JTAG

Graphics Features:• 160k Grpahics SRAM (No ECC)• Display Controller Unit – 18/24bit RGB• Parallel Data Interface• QuadSPI Serial Flash controller

General Characteristics:• Up to 64MHz operation• Low power modes• -40 to +105C, 3.0V to 5.5V• 144 LQFP, 176 LQFP package options

Peripherals and Communications:• 6 Stepper Motor Drivers with Stall Detection• Sound generation using eMIOS• 40x4 LCD Segment Driver• 2xCAN, 2xDSPI, 4xI2C, 2xLIN, I2S• 24 channel eMIOS (PWM+Timer)

• 16 channel, 10bit ADC


i.MX511200 MIPS

Coretex A8 600MHz

OpenVG1.1 & OpenGL2.0 Accel

Up to WXGA displayExternal Flash & DRAM i/f

530 BGA

MPC5645S

1.5MB

3MB

2MBZ4d CPU @ 120MHz

DCU (TFT Display Driver)Graphics Accelerator

Stepper Motor Drive

176 / 208 pin

DRAM

Investment reuse/portability

Applic

ation P

erf

orm

ance / Inte

gra

tion

MPC5604S

512KB

Z0h CPU @ 64MHzStepper Motor, LCD drive

144 / 176 pin

256KB

MPC5645S

1.5MB

3MB

2MBZ4d CPU @ 120MHzDCU (TFT Display Driver)

Graphics Accelerator

Stepper Motor Drive

176 / 208 pin

MPC5121eE300 @ 400MHz

OpenGL ES1.1 Accelerator

Up to XGA display


400 BGA

800 MIPs

i.MX35GARM1136JF-S CPU @ 400MHz

Open VG 1.1 2D Graphics Accelerator

Ip to SVGA display


400 BGA

400 MHz

Conn

ectivity,

applic

ation,

tools

No TFT

WVGA

HVGA TFT

MPC5606SZ0h CPU @ 64MHz

DCU (TFT Display Driver)

Up to 160KB GRAM


144 / 176 pin

1MB

768KB

WXGA

MPC5604S+

MPC5604S+

DC

U

OpenV

G

OpenG

L


•• The display driver used in Spectrum family MCUThe display driver used in Spectrum family MCU’’s for instrument cluster s for instrument cluster

is a combined direct unis a combined direct un--buffered blit engine & display driver.buffered blit engine & display driver.

•• Main advantages are Main advantages are

•• Cost efficient Cost efficient

•• Low memory requirementLow memory requirement

•• Optimized for GUI and advanced OSDOptimized for GUI and advanced OSD

•• Safety feature to enable safety related display content Safety feature to enable safety related display content

DCU


Bliting concepts

OBJECT memory

Blit engine

CPU

FRAME buffer

Display driver

Visible buffer

Shadow buffer

Scratch pad

OBJECT memory

eDMA

CPU

FRAME buffer

Display driver

Fragmented

frame buffer

Bli

ter

Classic solution

• Flexible and typically slow

• Needs typically 3x full frame buffer RAM for 480x272 @24/18bpp RGB888 that is 1147kB.

• Typically needs external fast RAM.

• Needs min. 2 x resolution RAM for video input.

• Display frame rate asynchronous output composition

DCU “direct un-buffered blit engine”

• Fixed function and typically much faster

• Needs less frame buffer RAM. For 480x272 @24/18bpp RGB888 that is typically less than 160kB

• Suitable for single chip solutions with no external RAM.

• Blit functions optimized for GUI design.

• No RAM required for video input

• Display frame rate synchronous output composition


DCU features, (updated with rev2 enhancements)DCU features, (updated with rev2 enhancements)

•• 16 Layers16 Layers

•• 4 planes4 planes

•• Frame buffer limited by memory size (all memories, RAM, ROM INTFrame buffer limited by memory size (all memories, RAM, ROM INT, EXT), EXT)

•• Target size WVGA (Limited by memory bandwidth and pixel clock sTarget size WVGA (Limited by memory bandwidth and pixel clock speed)peed)

•• Support 16, 24, 32 bit color depth.Support 16, 24, 32 bit color depth.

•• Support 1, 2, 4, 8bpp indirect color modeSupport 1, 2, 4, 8bpp indirect color mode

•• Support TFT type LCD with 16, 18, 24bit wide digital RGB interfSupport TFT type LCD with 16, 18, 24bit wide digital RGB interfaceace

•• Alpha blend (per pixel and per layer in 4 planes)Alpha blend (per pixel and per layer in 4 planes)

•• Chroma key (range per RGB component in 4 planes)Chroma key (range per RGB component in 4 planes)

•• Combined alpha blend and chroma key modesCombined alpha blend and chroma key modes

•• Font mode blending (transparency mode/alpha map)Font mode blending (transparency mode/alpha map)

•• Highlight area mode. (luminance offset)Highlight area mode. (luminance offset)

•• Tile mode Tile mode

•• Digital video inputDigital video input

•• Safety mode supportSafety mode support

•• Hardware cursorHardware cursor


DCU layers & planes

• Layer priority is fixed.

• Layers arbitrate for 4 planes on per pixel basis.

• The active layer that has the highest priority loads in the foreground plane 1,

the next loads in foreground plane 2 etc….

• If no layer qualifies for the BG plane the BG color is loaded in the BG plane


MPC5606S, Layers and planes usage

• Green frame show Planes and HW cursor

• Red frames show Layers


DCU functions – Font mode (Transparency)

•Original image

•Coded in 4bpp transparency

• Run time color selection in hardware to any back/fore color.

*) Images are significantly enlarged for clarity.


Transparency Mode Blending examples


DCU layers

• 16 + 1 background color

• Layers are memory areas that can reside in any memory. Internal or external

FLASH or RAM.

• Size and position is configurable runtime in 1 pixel increments.

•The 2 highest priority layers support a special safety mode.

• Data in layers is coded in 1,2,4,8 bits per pixel or…

• Raw color 16, 24, 32 bpp or.. (RGB565, RGB888, ARGB8888, ARGB1555, ARGB4444) or…

• 4 or 8bpp transparency with foreground and background color or…

• 4 or 8bpp luminance offset.


DCU CLUT

• CLUT is a color look up table.

• Size is 2k 24bpp colors, CLUT is assigned on a per layer basis.

• Pallet size is dynamic and is shared by all layers.

• Color depth is fixed to 24bpp RGB888

• Layer control descriptor uses a color offset value to mark start position in the

CLUT.

• As an example the CLUT can hold 8 x 8bpp pallets with 24bit colors. Or any combination required for the other indexed modes i.e. 1, 2, 4bpp.

• Run time manipulation and assignment of CLUT to a layer is possible.

• CLUT is part of the DCU memory and does not load the system memory bus.


MPC5606S, DCU timing example

1 frame = 16,7ms @ 60Hz

AB

C

• A Layer CD’s are latched in shadow buffer and frame composition starts.

• B CPU writes CD registers to prepare the next frame. Typically less than 0,1ms. Needs to be done within the frame period.

• C eDMA performs a ROM to RAM scan synchronized BLIT of the next car and navigation object. (Direct un-buffered frame synchronized blit)

• D eDMA performs vertical blanking period blit of CLUT, objects, HWC etc..

* C & D ie. the DMA activation is performed in ISR.

* B The main frame loop is assumed to be a pre-emptive low priority task. Very relaxed latency requirement. Typically need <5% CPU as an average measured over 16ms.

D


PDI video input, use case example

MCU

Camera ITU-R BT.656 (progressive RGB) Digital RGB

FPGA

De-interlacing

Scaling

muxing

Digital RGB Digital RGB

CCIR 656Digital RGBProprietary

LVDS

PDI 9 pin

MCU

PDI 10 pin

MCUCamera or

Navigation or

DVD decoder or

TV tuner or…16/18 bit RGB

Digital RGB

PDI 20/22 pin

• PDI has 5 modes. 8bitcolor, 8bit mono, 16bit, 18bit digital RGB and ITU-R BT.656 (progressive RGB)

• Input video must be equal clock data must match used display. Example: if

display is 480x272 9MHz input video must be 480x272 9MHZ


QuadSPI / Serial Flash


Serial Flash Bandwidth Expectations

• Serial Interface Bandwidth:

• Peak bandwidth = [Serial clock * 4(quad)] / [8bits/byte]

• For 48MHz flash = 24MByte/sec

• For 80MHz flash = 40MByte/sec

• Small overhead incurred to launch Serial Flash read commands reduces

achievable b/w – Impact depends on data size transferred

• As a frame buffer for Spectrum Display Control Unit (DCU):

• QVGA @ 5MHz pixel clock

• 16bpp layer = 10MByte/sec



• 480x272 @ 9MHz pixel clock





QuadSPI Integration – Spectrum1M

• AMBA AHB Slave:• Memory-mapped Serial Flash

looks like On-Platform memory

• Accessible by all crossbar

masters

• Direct access by DCU for pre-

rendered layers.

• IPS:• Connected as an IPS peripheral

• Useable as regular SPI

• Clocking• Serial Interface runs up to full

48MHz platform speed

• Auxiliary PLL available as

optional clock source.

CROSSBAR SWITCH

48KSRAM

PowerTM

e200z0hCore

QuadSPI Serial Flash Controller

VReg


Crossbar Slaves


Crossbar Masters

Nexus

JTAG

Debug

1MbFlashBoot

AssistModule (BAM)

Oscillator


System Integration

16chDMA

Display Control Unit

RTC

I/OBridge

2 FlexCAN

2LINFlex

16 chATD10bit

6 Gauge Drivers

eMIOS24 ch

4I2C

2 DSPI

Stall Detect

40x4 LCD

2xFMPLL

160KGraphicsSRAM

RGB / Control

Sound

Generation

Power

Management

4x16k EEE

PDI


0x87FF_FFFC

0x803F_FFFC

QuadSPI Memory Map

• AHB Mapping• 4 x 128MByte ‘Slots’ reserved for external serial flash in memory map (future expansion)

• AHB RX Data Buffer (QSPI_ARDB) for Serial-Flash-0 is mapped at 0x87FF_FFFC

0x8000_0000

0x8000_0004

0x8000_0008

0x8000_000C

MCU Memory Map

0x00_0000

0x00_0004

0x00_0008

0x00_000C

Serial Flash Memory Map

0x3F_FFFC

QSPI_ARDB

128k

QuadSPI

Slot-0

32Mbit

Serial Flash

(4MByte)


Sound Generation


MPC560xS : Simple Audio Implementation

Features:

• Used for simple „beeps“ / „alarms“

• Uses dual-PWM outputs• 1 x PWM channel to control Amplitude • 1 x PWM channel to control Frequency

• Logical ‚AND‘ of any 2 eMIOS PWM channels to generate audio output

• Simple external R-C Low pass filter on mixed PWM output

LPF

Frequency

Amplitude

Freq . Amplitude

Filtered


MPC560xS: Advanced Audio Implementation

Features:

• Playback of Sample-Based waveforms• Polyphonic sound synthesis• DMA reads sound files from internal (or external) Flash• Up to 8KHz analog bandwidth• Variation of duty cycle reconstructs the analog signal

• Speed of duty cycle variation proportional to frequency• Width of duty cycle variation proportional to amplitude

• Analog signal AC centered around 50% duty cycle• Low pass filter / amplifier on PWM I/O pin• Software tools to support sound generation

LPF

50% Duty

Low Duty

High Duty


Software Libraries


Introduction

MPC56xxS Software Graphics Libraries

The MPC56xxS Software Graphics Libraries is a set of drivers that allow the designers to develop fast and clean software animations. The libraries explodes most of the HW features of the Display Control Unit along with other peripherals such the DMA.

Current Main Features

• Animations (Position, Transparency, Color, Scrolling, and Downscaling) HW accelerated

• Transformations (Rotations, Mirroring, Blitting) DMA accelerated

• RLE Decoding Hybrid CPU/DMA

• Color Look up table dynamic update. DMA accelerated

• Dynamic Memory Allocation for graphics. DMA accelerated

• UNICODE Text Rendering. CPU or DMA Accelerated

• PC Toolset to manipulate graphic


Software Architecture

• Drivers were made to work together in an abstract way

• Architecture allow correct interaction between software layers

• Users will focus in movie clips and functionality leaving alone lower layers

HARDWARE ABSTRACTION LAYER (HAL)Graphic Memory Allocation, DCU and DMA

HARDWARE INDEPENDENT LAYER (HIL)Font library, Graphics Library, Animation Library and

Display driver.

SERVICES

DMA Handler,Animation

Handler,Interrupts,

Others

APPLICATION LAYERMovie Clips, Stimuli, Images, Font files

Software Architecture Key Features


Software / Tools


Freescale Image Encoder

Image File(gif, bmp, jpegpng, others)

FreescaleImage

Encoder

*.h

*.c SpectrumGraphicsLibaries


Freescale Font Encoder

Angel CodeFont BitmapGenerator

FreescaleFont

Encoder

*.fnt(xml file)

*_00.png[*_01.png]

…Spectrum

FontLibrary


Freescale HW Tools

►Current HW Available:

• Spectrum Axiom board

• MPC5606S EVB (Mini-module

+ Motherboard

►In development:

• Spectrum EVB (low cost) estimated production date:

April’10


Spectrum

Graphic Application Design


Typical Work Flow

Graphic Designer

Tools

IllustratorPhotoshop

PaintGimp

Blender

UsesImagesFontsSkins

Vector Files3D Models

Outputs

UI Designer

Tools

Adobe FlashGIMPExcel

Image processingBatch processing

[Others tools]

OutputsAre used by

Images

Fonts

Vector Files

Specification

(excel files)

(requirements document)

+

ImagesFontsSkins

Vector Files3D Models

Uses


Typical Work Flow

Developer

Tools & Libraries

Spectrum LibrariesImage EncoderFont Encoder

OutputsAre used by

Images

Fonts

Vector Files

Specification

(excel files)

(requirements document)

+Uses

Spectrum

Rainbow

Application


Cross Family Compatibility

CROSSBAR SWITCH

40K

SRAM

PowerPCTMe200z0

Core

VReg


Crossbar Slaves


Crossbar Masters

Nexus

JTAG

Debug

512KbFlash Boot

AssistModule

(BAM)

Oscillator

System Integration

DMARTC

I/O

Bridge

1or2

FlexCAN

1

eSCI

Mc T

imer

3DSPI

FMPLL

FlexRay

Mc T

ime

r

Mc T

ime

r

Mc P

WM ADC I/F

10 bit650 nsec

S&H S&H

mux mux

CROSSBAR SWITCH

40K

SRAM

PowerPCTMe200z0

Core

VReg


Crossbar Slaves


Crossbar Masters

Nexus

JTAG

Debug

512KbFlash Boot

AssistModule

(BAM)

Oscillator

System Integration

DMARTC

I/O

Bridge

1or2

FlexCAN

1

eSCI

Mc T

imer

3DSPI

FMPLL

FlexRay

Mc T

ime

r

Mc T

ime

r

Mc P

WM ADC I/F

10 bit650 nsec

S&H S&H

mux mux

CROSSBAR SWITCH

32KSRAM

PowerPCTM

e200z0

Core

VReg


Crossbar Slaves

Interrupt

Controller

Crossbar Masters

Nexus

JTAG

Debug

512KbFlash Boot

AssistModule

(BAM)

Oscillator


System Integration

DMA

ReadyRTC

I/O

Bridge

3

FlexCAN

4

LINFlex

32 ch

ATD12bit

eMIOSLite

8ch IO

36ch shiftPWM

3

DSPI

FMPLL

2

I2C

Power Sw

PIT 4ch 32b

MCM

CROSSBAR SWITCH

48K

SRAM

PowerPCTMe200z3

Core

SIMDMMU

VReg


Crossbar Slaves

Interrupt

Controller

Crossbar Masters

Nexus

JTAG

Debug

1Mb

Flash Boot

Assist

Module

(BAM)

Oscillator

System Integration

DMARTC

I/O

Bridge

2

FlexCAN

2

eSCI

32 ch

ATD

12bit

eMIOSLite

24ch

2

DSPI

FMPLL

eTPU

32 ch.

2.5K Code

RAM

12K Data

RAM

Ca

l B

us I

nte

rfa

ce

CROSSBAR SWITCH

48K

SRAM

PowerPCTMe200z3

Core

SIMDMMU

VReg


Crossbar Slaves

Interrupt

Controller

Crossbar Masters

Nexus

JTAG

Debug

1Mb

Flash Boot

Assist

Module

(BAM)

Oscillator

System Integration

DMARTC

I/O

Bridge

2

FlexCAN

2

eSCI

32 ch

ATD

12bit

eMIOSLite

24ch

2

DSPI

FMPLL

eTPU

32 ch.

2.5K Code

RAM

12K Data

RAM

Ca

l B

us I

nte

rfa

ce

CROSSBAR SWITCH

64KSRAM

PowerPCTM

e200z0

Core

External

Bus

(208MAPBGA)

VReg


Crossbar Slaves

Interrupt

Controller

Crossbar Masters

Nexus

JTAG

Debug

1MbFlash Boot

AssistModule

(BAM)

Oscillator


System Integration

DMA

DisplayInterface

UnitRTC

I/O

Bridge

2

CAN

2

LIN

Flex

16 ch

ATD10bit

6

gaugedrivers

eMIOSLite

24 ch.

2I2C

3

DSPI

so

un

d

40x4

LCD

FMPLL

Video

RAM

(tbd)

CROSSBAR SWITCH

64KSRAM

PowerPCTM

e200z0

Core

External

Bus

(208MAPBGA)

VReg


Crossbar Slaves

Interrupt

Controller

Crossbar Masters

Nexus

JTAG

Debug

1MbFlash Boot

AssistModule

(BAM)

Oscillator


System Integration

DMA

DisplayInterface

UnitRTC

I/O

Bridge

2

CAN

2

LIN

Flex

16 ch

ATD10bit

6

gaugedrivers

eMIOSLite

24 ch.

2I2C

3

DSPI

so

un

d

40x4

LCD

FMPLL

Video

RAM

(tbd)

Monaco(Powertrain)

Pictus/Tokay(Airbag/Steering)

Bolero(Body)

Spectrum(Instrument Cluster)

3232--bit standard architecture adopted across all product familiesbit standard architecture adopted across all product families

� Maximum IP reuse

� Faster time-to-market

� Reduced risk

� Leverage software and tools investments

nuevas soluciones power architecture para desarrollo … · tm freescale, the freescale logo,...

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