Homework Assignment #4 SolutionQ4.1(a) Iteration bound

(2Ta+1Tm)/2 = 18ns

(b) Critical path6Ta+2Tm = 88ns

(c) Retiming so that critical path delay equal to iteration bound (18ns)

Note: the retiming solution may not be unique

Q4.3(a) Iteration boundLoop 1 bound = (3Ta+2Tm)/4 = 7/4, loop 2 bound = (1Tm+1Ta)/4=3/4Iteration bound = max{7/4,3/4} = 7/4

(b) Critical pathLoop 1 also corresponds to the critical path, the total computation time along the path is 7 u.t.(c) Pipeline/retime the design to achieve a critical path of 2 u.t.

Note: since a delay is inserted to the input, the timing relationship between IN and OUT would change from “IN(n) vs. OUT (n)” to “IN(n) vs. OUT(n-1)”. In other words, the output generated at clock “n” has a time instance “n-1”. The output’s time instance is 1 clock behind that of input because of one extra delay in the computing pipeline.

final retiming result with a critical path of 2 u.t.Note: the retiming solution may not be unique

Q4.5.(a) Critical path & iteration bound

Critical path delay = 1Tm+5Ta = 7 u.t.

Iteration bound = (1Tm+2Ta)/1=4u.t.(b) Retiming

The critical path delay is 1Tm+2Ta = 4 u.t.

Q3.3

Find an equivalent data broadcast implementation of the designStep 1. Reverse the direction of summation path for y(n)

Step 2. cut set retiming

Q3.8 recursive filter x (n )=ax (n−2 )+u(n)

(a) Pipeline the multiply-add operator by 2 stages

(b) Interleave the computation with y (n )=ay (n−2 )+v (n)Step 1: time scaling by a factor of 2

After timing, both input and output work at 1/2 throughput rate, and one half of the clock cycles (odd ones) are idle, where the second computing stream can be admitted

Step 2: pipeline interleaving

Note: you may further retime the design by evenly distributing the 4 delays along the loop to reduce the critical path delay

Q3.11

Assume , Vdd = 4V, Vt = 6V, the design is M-stage pipelined

When the design is either not pipelined or just 1-stage pipelined, the loading or

charging capacitance along the critical path is .

Assume the data path is evenly pipelined, the charging capacitance for each pipeline

stage is

Note: since the latch delay is ignored, we do not include the latch capacitance into the charging capacitance of the critical path. If otherwise, you should see

in each pipeline stage

is now a function of M

The normalized power consumption of the pipelined design, i.e. = Ppipelined/Psequential would become

Since is a function of pipeline stage M, we have

The minimum power consumption occurs at .The nearest integer value is M = 13 and the normalized power consumption is 0.1717.Note: You CANNOT ignore the power consumption of the pipeline latches although its propagation delays are ignored when determining the critical path delay.

Otherwise, the normalized power consumption becomes , which reaches a

minimum when M approaches infinity.