Agenda

1. Motivation

2. Testing Inter-Switch Wire Segments

3. Testing Switch Blocks

4. Conclusion

Offline Test and Diagnosis of Network-on-Chips6/9/2009 2

Agenda

1. Motivation



4. Conclusion


1. Motivation


Network-on-Chip (NoC) TestingTechnology miniaturization

Post fabrication testing

Low cost testing

Use NoCs in critical applications

Types of Test:Offline Test

Online Test

1. Tradeoffs

NoC NoC

Test Source

Test Source

External Test

Methodology

Built-In-Self-Test

Methodology


Small Area OverheadHigher Test Time

Large Area OverheadLower Test Time

The network is used as a Test-Access-Mechanism (TAM)

Minimized by using parallelism (Multicast)

Unlimited parallel test

Minimized by using shared test units instead of dedicatedunits

1. Tradeoffs

NoC NoC

Test Source

Test Source

External Test

Methodology

Built-In-Self-Test

Methodology


Small Area OverheadHigher Test Time

Large Area OverheadLower Test Time

Tradeoff(test area overhead & testing time)

1. NoC Testing

Blocks to be tested in a NoC:1. Inter-switch wire segments

2. Switches

3. IP Cores with the RNIs

IP Core

RNI

SW

IP Core

RNI

SW

IP Core

RNI

SW

IP Core

RNI

SW


IP: Intellectual PropertyRNI: Resource Network Interface

Agenda

1. Motivation



4. Conclusion


2.1 Maximum Aggressor Fault Model (MAF)

This fault model addresses worst case

Crosstalk errors during data transmission

Y2 is called Victim Line & Y1,Y3 are called Aggressor Lines

86/9/2009

Y1

Y2

Y3


[Cuviello, ICCAD’99]

Falling delay ( )

Positive glitch ( )

Rising delay ( )

Negative glitch ( )

Rising speed-up ( )

Falling speed-up ( )

2.2 Testing Inter-Switch Wire Segments

Built-In-Self-Test (BIST) Structure

TDG: Test Data Generator

TED: Test Error Detector

96/9/2009

Driver Load

TEDTDG

Swit

ch

Swit

ch Inter-switchLink


[Grecu, VTS’06]

2.2 The BIST Structure

Implementation of the TDG and TEDFinite state machine

Counter

Barrel shifter

XOR network for comparison (TED only)

106/9/2009

0 0 0 0 0

1 1 1 1 1

0 0 0 0 0

1 1 0 1 1

0 0 1 0 0

1 1 0 1 1

1 1 1 1 1

0 0 1 0 0

s1

s2

s3

s4

s5

s6

s7

s8

statei-2 … i … i+2

s0

s1s2

s3

s4s5

s8

s6

s7

Count = n-1T_start

T_startLine:


[Grecu, VTS’06]

Reminder

Y1

Y2

Y3

Falling delay ( )

Agenda

1. Motivation



4. Conclusion


3.1 Switch Architecture

Main Blocks:1. FIFO Buffers

2. Routing Logic Block

3. Multiplexers withintra-switch links

MUX

M U X

M U X

MUX

FIFO Out

FIFO In

FIFO

In

FIFO

Out

FIFO Out

FIFO In

FIFO

Out

FIFO

In

East

South

North

West

NERS

(W)

NRSW(E)

N E R W (S)

E R S W (N)

RoutingLogicBlock(RLB)


[Raik, ETS’07]

3.3 Testing the RLBs

External-based test structure

Test source is connected to theTest Access Switch (TAS)

Each Switch forwards the test-vectors to all neighbor switches NoC

SW1

SW2

SW3

SW4

TestSource

TAS


CLK

SW2Input

Output

t0 t1 t2 t3 cap

t0 t1 t2 t3 idle r0.1 r0.2 r0.3

Comparing the incoming

result with the captured

result

SW1Input

Output

t0 t1 t2 t3 cap r0.1 r0.2 r0.3

SW3Input

Output

t0 t1 t2 t3 cap

t0 t1 t2 t3 idle

r0.1 r0.2 r0.3

r1.1 r1.2 r1.3

SW4Input

Output

t0 t1 t2 t3 cap r1.1 r1.2 r1.3

[Hosseinabady, DATE’06]

3.3 Diagnose the Faulty RLB

Assume single fault


NoC

SW1

SW2

SW3

SW4

TestSource

TAS

SW1 is Faulty

+ve

-ve

feedback

feedback


Assume single fault


NoC

SW1

SW2

SW3

SW4

TestSource

TAS

SW1 is FaultySW3 is Faulty

+ve

-ve

feedback

feedback


Assume single fault


NoC

SW1

SW2

SW3

SW4

TestSource

TAS

SW1 is FaultySW3 is Faulty

??SW2 is Faulty +ve

-ve

feedback

feedback

3.3 Broadcast routing tree

Two different NoC topologies configured with optimum broadcast routing tree:

TAS

(1)

(1)(1)

(2)

(2) (2)

(2)

(2)

(2)

(3)(3)(3)

(3)

(1)

(1)

(1)

(2)

(2)(2)

(2)

TAS

Topology 1 Topology 2


[Hosseinabady, DATE’06]

3.4 Testing the Multiplexers and Intra-Switch Links

Multiplexers:Distinguished value at the tested input

All possible inputs should be tested

Intra-Switch Link:Physical link connecting I/O portsinside the switch


MUX

00

01

10

11

In1=X

In2=X

In3=X

In4=X

Out

Address = 00 Targeted

structural

faults

N

S R

EW

Link

[Raik, ETS’07]

3.4 Testing Configurations


N

S R

EW

Deterministic

XY/YX-Routings

N

S R

EW

Straight Path

Routings

N

S R

EW

Resource

I/O-Routings

N

R

EW


Configuration 1: Straight Path Routings


S

N

S R

EW

N

S R

EW

4-possibilities

Deterministic

XY/YX-Routings

Straight Path

Routings

Resource

I/O-Routings

N

R

EW


Configuration 2: Deterministic XY/YX Routings


S

N

S R

EW

N

S R

EW

4-possibilities8-possibilities

Deterministic

XY/YX-Routings

Straight Path

Routings

Resource

I/O-Routings

N

R

EW


Configuration 3: Resource I/O Routings


S

N

S R

EW

N

S R

EW

4-possibilities8-possibilities 8-possibilities

20 total possibilities

Deterministic

XY/YX-Routings

Straight Path

Routings

Resource

I/O-Routings


Three test configurations for mesh-based network


2.

Deterministic

XY/YX-Routings

1.

Straight Path

Routings

3.

Resource

I/O-Routings

[Raik, ETS’07]

End

Start

Row: r++

Error E-Wr,?

Error E-Wr,k-1 Error E-Wr,n

Error E-Nr,k

Error N-Er,k

Error R-E,W,Sr,k

Error N-Rr,k

E-W Test

E-N Test

N-E Test

ResourceTest

E-N Test

Fail Pass

Pass all turnsFailat

Turn‘k’ Fail

atTurn‘k’ Mismatch

at singleO/P Mismatch

betweenI/P & O/P

Pass

Pass all turns

Failat

Turn‘k’

All rows tested: r=n

r<n

6/9/2009 22Offline Test and Diagnosis of Network-on-Chips

3.4 Diagnose Faulty Intra-Switch Link

Passall

turns

Intra-switch faulty linkTest vector 101010…

[Raik, ETS’07]

Example

Agenda

1. Motivation



4. Conclusion


4. Conclusion

Steps for the overall test strategy:


SW

TEDTDG

TEDTD

G

TED

TDG

SW

SWSW

1.Testing theInter-switch linksBy BIST structure

TEDTDG

BIS

TC

ontr

olle

r

SWFIFO

SWFIFO

SWFIFO

SWFIFO

LRA LRA

LRA LRA

2.Testing theFIFO BuffersBy BIST structure

2a 3

2b1TestSource

3.Testing the RLBBy external test

Test Source

VH-Test

XY-Test

4.Testing theMUXs andIntra-switch linksBy 3-test config.& Diagnose Algor.


Thank you

6/9/2009

offline test and diagnose of network-on-chips

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