on the design of wideband cmos low-noise · pdf file · 2017-09-14kcl kirchhoff...

ON THE DESIGN OF WIDEBAND CMOS LOW-NOISE AMPLIFIERS

by

Reza Molavi

B.A.Sc., Sharif University of Technology, 2003

A THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OF

MASTER OF APPLIED SCIENCE

in

The Faculty of Graduate Studies

Electrical and Computer Engineering

THE UNIVERSITY OF BRITISH COLUMBIA

September 2005

© Reza Molavi, 2005

ii

ABSTRACT

Integrated wideband low-noise amplifiers (LNAs) are used in communication applications in

which either the signal bandwidth is large or multiple narrowband signals are processed

simultaneously. An example of the former case is the recently popular ultra wideband (UWB)

wireless technology that can be used for high-data-rate low-power short-range wireless

communications. A multi-mode multi-standard wireless system is an example of the latter case.

Providing large enough gain while introducing as little noise as possible over a wide frequency

band is a challenging design task, in particular if the LNA is designed in CMOS. In this work, a

methodology for designing wideband CMOS LNAs is presented. The core of the design is the

inductively degenerated LNA which is a popular architecture in narrow-band applications due to

its superior noise and input matching properties as well as low power consumption. Wideband

performance of inductively degenerated LNA is explored both at the circuit and system level.

Trade-offs among different design requirements and their impacts on circuit parameters is

discussed in detail.

To demonstrate the effectiveness of the design technique, two wideband LNAs are designed and

simulated in a 0.18µm CMOS technology. The first LNA is intended for a multi-standard system

with the frequency range of 1.4 to 2.5GHz. The frequency band of the second LNA is from 3 to

5GHz which covers the lower band of UWB technology.

iii

TABLE OF CONTENTS

Abstract ............................................................................................................................... iiTable of Contents............................................................................................................... iiiList of Tables ..................................................................................................................... ivList of Figures ..................................................................................................................... vAcronyms.......................................................................................................................... viiAcknowledgements .........................................................................................................viiiChapter 1 INTRODUCTION .......................................................................................... 1

1.1 Motivation........................................................................................................... 11.2 Research Goals.................................................................................................... 51.3 Thesis Outline ..................................................................................................... 5

Chapter 2 BACKGROUND ............................................................................................ 72.1 Noise ................................................................................................................... 82.2 Nonlinear Effects .............................................................................................. 162.3 Input Matching.................................................................................................. 202.4 S Parameters...................................................................................................... 242.5 Wideband LNA Topologies.............................................................................. 26

Chapter 3 WIDEBAND LNA METHODOLOGY ....................................................... 383.1 Power gain and Impedance mismatch factor .................................................... 393.2 Wideband noise and input matching................................................................. 443.3 SNR-based Optimization Technique ................................................................ 523.4 Proposed Design Technique ............................................................................. 583.5 Wideband Impedance Matching Networks....................................................... 64

Chapter 4 SIMULATION RESULTS AND LAYOUT ISSUES .................................. 704.1 Wideband LNA for multi-standard application in 1.5-2.5GHz ........................ 704.2 Wideband LNA for UWB application (3.2-5GHz)........................................... 74

Chapter 5 CONCLUSIONS AND FUTURE WORK ................................................... 805.1 Conclusions....................................................................................................... 805.2 Future Work ...................................................................................................... 81

References......................................................................................................................... 82Appendix A Linear two port noise analysis .................................................................. 86Appendix B Classic MOS device noise analysis........................................................... 90

iv

LIST OF TABLES

Table 1 Wireless standards characteristics......................................................................... 3Table 2 Summary of Performance ................................................................................. 75

v

LIST OF FIGURES

Figure 1.1 Block diagram of a simplified RF receiver ...................................................... 2Figure 2.1 Thermal noise of a resistor ............................................................................. 10Figure 2.2 (a) Dominant sources of noise in a MOS - (b) Thevenin equivalent circuit . 12Figure 2.3 Two-port network model of MOS device for noise calculations ................... 14Figure 2.4 NF calculations for a cascaded system .......................................................... 15Figure 2.5 1dB compression point ............................................................................... 17Figure 2.6 (a) Signal spectrum of a nonlinear system (b) Graphical interpretation of IIP3

................................................................................................................................... 18Figure 2.7 Different input matching topologies (a) resistive termination...................... 21Figure 2.8 Small signal model of an inductively degenerated LNA................................ 23Figure 2.9 S parameters definition of two-port networks ................................................ 25Figure 2.10 Two port model of a hunt-series amplifier ................................................... 28Figure 2.11 Common drain feedback LNA ..................................................................... 29Figure 2.12 Two-stage LNA for UWB applications........................................................ 30Figure 2.13 Two stage wideband LNA for UWB applications........................................ 31Figure 2.14 Simplified block diagram of a shunt-feedback LNA.................................. 32Figure 2.15 Schematic of thermal noise cancelling technique......................................... 33Figure 2.16 Block diagram of balanced amplifier .......................................................... 35Figure 2.17 Schematic of a basic distributed amplifier ................................................... 36Figure 3.1 Conceptual diagram of power transfer in an amplifier................................... 39Figure 3.2 Input mismatch factor with matching network............................................... 40Figure 3.3 (a) Narrowband LNA (b) Wideband LNA .................................................... 41Figure 3.4 block diagram of a unilateral amplifier with port matching.......................... 43Figure 3.5 Small signal model of an inductively degenerated LNA................................ 44Figure 3.6 Gain of LNA vs. Re{Zin} and Re{Zopt} for UWB applications in 3-5GHz ... 49Figure 3.7 NF of LNA vs. Re{Zin} and Re{Zopt} for UWB applications in 3-5GHz...... 49Figure 3.8 Gain of LNA vs. Re{Zopt} (ω) for several values of Re{Zin} (Ls).................... 50Figure 3.9 NF of LNA vs. Re{Zopt} (ω) for several values of Re{Zin} (Ls) ...................... 50Figure 3.10 Graphs of Re{Zin} and Re{Zopt} vs. frequency for UWB applications in 3-5GHz

(W=75μm)................................................................................................................. 51Figure 3.12 SNRout vs. Re{Zin} and Re{Zopt} for UWB applications in 3-5GHz .......... 55Figure 3.13 SNR of LNA vs. Re{Zopt} (ω) for several values of Re{Zin} (Ls) .............. 56Figure 3.14 Optimum value of Re{Zin} (Ls) for variations of NFeq................................ 57Figure 3.15 Contour plots of total power consumption .................................................. 60Figure 3.16 Transit frequency (ft) vs. overdrive voltage................................................. 61Figure 3.17 Contour plots of equivalent noise resistance (Rn)........................................ 62Figure 3.18 (a) π matching network (b) T matching network....................................... 65Figure 3.19 Contours of constant Qn displayed in the smith chart ................................. 66Figure 3.20 (a) π matching network (b) Equivalent circuit........................................... 67Figure 3.21 Real parts of impedances Zin and Zeq over the UWB band .......................... 68Figure 3.22 Imaginary parts (equivalent inductance) of impedances Zin and Zeq over the UWB

band........................................................................................................................... 69Figure 4.1 Complete schematic of the multi-standard LNA............................................ 71

vi

Figure 4.2 Real part matching of Rin and Ropt for multi-standard LNA ......................... 72Figure 4.3 Simulated S-parameters of the multi-standard LNA .................................... 73Figure 4.4 Simulated NF and NFmin of the multi-standard LNA .................................... 73Figure 4.5 Complete schematic of the UWB LNA......................................................... 74Figure 4.6 Layout of cascade amplifier for the UWB LNA .......................................... 76Figure 4.7 Nine-element equivalent model of spiral inductors....................................... 77Figure 4.8 Simulated S-parameters of the UWB LNA (post-layout) ............................ 78Figure 4.9 Simulated NF of the UWB LNA (post-layout) ............................................ 79Figure A.1 (a) block diagram of noisy two-port network (b) Equivalent network with input and output noise current sources…………………………………………..…. 86Figure A.2 Input Referred equivalent noise model……………………………………...87Figure B.1 (a) Noise sources of a MOS device b) Equivalent input referred model….. 90

vii

ACRONYMS

ADC Analog to Digital ConverterADS Advanced Design SystemsCAD Computer Aided DesignCMOS Complementary Metal Oxide SemiconductorCNM Classical Noise MatchingDA Distributed AmplifierDAC Digital to Analog ConverterDSM Deep Sub MicronDSP Digital Signal ProcessingGPS Global Positioning SystemGSM Global System for Mobile CommunicationIMF Impedance Mismatch FactorIMP Inter Modulation ProductKCL Kirchhoff Current LawKVL Kirchhoff Voltage LawLNA Low Noise AmplifierLO Local OscillatorMCM Multi Chip ModuleMIM Metal Insulator MetalNF Noise FigurePCNO Power Constrained Noise OptimizationPCSNIM Power Constrained Simultaneous Noise and Input MatchingPCWSNIM Power Constrained Wideband Simultaneous Noise and Input MatchingRF Radio FrequencySiP System in PackageSNIM Simultaneous Noise and Input MatchingSNR Signal to Noise RatioUMTS Universal Mobile Telecommunication SystemUWB Ultra Wide bandVCO Voltage Controlled OscillatorVSWR Voltage Standing Wave RatioWLAN Wireless Local Area NetworkWPAN Wireless Personal Area Network

viii

ACKNOWLEDGEMENT

There are many friends and colleagues that I would like to thank for their invaluable help and

support during my years at UBC. First of all, I would like to thank my supervisor and friend, Dr.

Shahriar Mirabbasi who gave me the opportunity to join his research group at UBC. His keen

knowledge on the design of analog/RF integrated circuits was the key factor in the success of this

research project. I am particularly grateful for the great advises, both technical and personal, that

he gave me over these years. Also, I would like to thank Dr. Ivanov and Dr. Schober for reading

my thesis and serving as my committee members.

I am honoured to call myself part of SoC research group. Working with a group of

brilliant researchers who were, undoubted fully, great motives throughout my research years, was

a great privilege I benefited in SoC lab. I would like to express appreciations to all my friends at

SoC particularly to Howard Yang, Scott Chin, Amit Kedia, Karim Allidina, Neda Nouri, Melody

Chang, Samad Sheikhai, Pedram Sameni, Dipanjan Sengupta, Peter Hallschmid, Marwa

Hamour,Behnoosh Rahmatian, Xiongfei Meng and Shirley Au. I also thank Roberto Rosales,

Roozbeh Mehrabadi and Sandy Scott for their help and support in the SoC lab. I would like to

extend my gratitude to all my friends and relatives in Canada and US with whom I shared great

memories in the past two years, especially my uncles in Seattle, Maryam Esfahanian, Farbod

Abtin, Amirhossein Heydari, Amir Sadaghianizadeh and Ali Mashinchi.

The last but the most, I would like to express my deepest appreciation to my wonderful

parents and brother for their continuous love, inspiration and support. I could feel their

supportive presence in every single moment of these two years even though they were physically

miles away from me. Thank you from the bottom of my heart!

This research was supported by NSERC and SiRF Technology Inc.

ix

This thesis is dedicated to:

My father who is and will always be my best friend and teacher,

My mother without whose unconditional support I would not be where I am today,

My brother who is and will always be my most trustworthy friend,

Maryam who gave me love and inspiration over these years,

and

My beautiful country, Iran.

Chapter 1 - Introduction 1

CHAPTER 1

INTRODUCTION

1.1 Motivation

Communication technology is moving toward a major milestone. The explosive growth of the

wireless industry, global access to the internet, and the ever increasing demand for high speed

data communication are spurring us toward rapid developments in communication technology.

Wireless communication plays an essential role in this transformation to the next generation of

communication systems. Cellular phones, pagers, wireless local area networks (WLAN), global

positioning system (GPS) handhelds, and short-range data communication devices employing

Bluetooth and ultra wideband (UWB) technologies are all examples of portable wireless

communication devices. Nowadays, driven by the insatiable commercial demand for low-cost

and low-power multi-standard portable devices, RF designers are urged to develop new

methodologies that allow the design of such products.

An irreplaceable component of any RF receiver is the front-end low-noise amplifier

(LNA). As the first active building block in the receiver front-end, the LNA should provide

considerable gain while minimizing the noise introduced to the system. Fig. 1.1 depicts the

simplified structure of an RF receiver. The received signal is typically filtered, amplified by an

LNA and translated to the base-band by mixing with a local-oscillator (LO). After being

demodulated, the signal is applied to an analog-to-digital converter (ADC) which digitizes the

analog signal. The digital signal is then processed in a digital signal processing unit (DSP). As


can be seen, the first step of signal amplification is done by the LNA. Therefore, the performance

of LNA can greatly affect sensitivity and noise parameters of the overall receiver.

Figure 1.1 Block diagram of a simplified RF receiver

Why Wideband?

Recently, there has been a tremendous effort to develop wireless devices that integrate multiple

applications (phone, video-game console, navigator, digital camera, web browser, etc.) on a

single chip. A variety of standards exist for each of these applications. The plethora of standards

include global system for mobile communication (GSM) and universal mobile

telecommunication system (UMTS) for cellular telephony, IEEE802.11a/b/g and HiperLAN2 for

LAN access, Bluetooth for short-range communication, and GPS. A brief summary of these

standards is provided in Table 1 [1][2][3]. The growing number of these wireless communication

standards promotes the need for a multi-standard transceiver. The RF front-end of such a receiver

has to cover a wide range of different carrier frequencies (see Table 1). To achieve this goal,

wideband performance of the receiver front-end is desired. A variety of architectures have been

proposed to fulfill this requirement. One approach is to use a parallel combination of several

tuned narrowband LNAs. This solution, although straightforward, is power hungry and area


inefficient. Therefore, it is not particularly suitable for low-cost portable systems. Two other

LNA architectures that can be used for multi-standard signal reception are concurrent LNA [4]

and tuneable LNA [5]. The former technique is applicable when the frequency bands of desired

standards are well separated, while the latter design approach is complicated if a wideband

tuning-range is desired [6]. An alternative solution is to design a single wideband LNA covering

the entire band of interest, which is the subject of this research.

Wireless Standard

Carrier Frequency

Channel Spacing

Access Scheme

Modulation Technique

Data Rate

GSM 880–960MHz 200kHz TDMA/FDD GMSK 270.8kb/sPCS 1900 1.88–1.93GHz 200kHz TDMA GMSK 270.8kb/s

GPS 1.575GHz 2MHz C/A code N/A BPSK/SS 50b/sIEEE 802.11a 5.15–5.85GHz 20MHz OFDM QPSK up to 54Mb/sIEEE 802.11b 2.4–2.48GHz 22MHz CDMA/DSSS QPSK up to 11Mb/s

Bluetooth 2.4–2.48GHz 1MHz CDMA/FH GFSK 1Mb/sUWB 3.1–10.6GHz N/A OFDM QPSK up to 480Mb/s UMTS 1.92–2.17 GHz 5MHz CDMA QPSK 3.84Mb/s

Table 1 Wireless standards characteristics

Wideband LNAs also find application in the recently introduced UWB systems. Over the

last few years, these systems, initially developed for wireless personal area network (WPAN)

application, have received significant attention from industry, media and academia.

Theoretically, UWB systems support data rates from 110Mb/s at a distance of 10 meters to

480Mb/s at a distance of 2 meters, while consuming little power [7]. The allocated frequency

band for the UWB system is 3.1-10.6GHz (low-frequency band: 3.1-5GHz; high frequency band:

6-10GHz). Therefore, the design of a wideband LNA covering the entire band of interest is of

major concern in the development of a UWB receiver.


Other applications of wideband LNAs include analog cable (50-850MHz), satellite (950-

2150MHz) and terrestrial digital (450-850MHz) video broadcasting [8]. Transceivers used in

optical links with a high number of channels also need a wideband LNA at the front-end [9].

Why CMOS?

Currently, most commercial RF transceivers are implemented as multi-chip modules

(MCMs) or system in packages (SiPs), using various technologies [10]. Base-band and mixed-

signal components (e.g., DAC, ADC, and DSP) are mainly implemented in complementary

metal-oxide semiconductor (CMOS) technology, while RF and analog sections are typically

implemented in silicon-germanium (SiGe) or gallium-arsenide (GaAs) technologies. High

quality passive filters are mostly realized as discrete components. MCM and SiP approaches

suffer from many shortcomings, such as large size, high power consumption, and high

integration cost. The aforementioned problems account for the global trend toward a single

technology that can support a commercially viable single chip RF transceiver.

Historically, CMOS technology was not considered a good candidate for analog and RF

applications. Relatively small transconductance, low drive capability, and poor quality of on-chip

passive elements are among the several limitations of this technology. However, the incredible

growth of the digital industry due to the continuous scaling in CMOS technology has motivated

designers to develop analog and RF CMOS circuits that can be integrated along with the digital

circuitry. This has led to the tremendous research and development in implementing single chip

systems. Furthermore, the transit frequency (ft) of MOS devices has recently increased due to the

evolution of CMOS into deep-sub-micron (DSM) technologies (ft’s exceeding 100GHz have


been recently reported [11]). This greatly improves the performance of integrated RF CMOS

circuits.

To summarize, despite the inferior performance of RF CMOS circuits compared to their

SiGe and GaAs counterparts, the dominance of CMOS in the digital world, combined with the

feasibility of integrating digital/RF/analog circuits on a single chip and the potential cost and

power advantage of this integration, provide reasonable motives to adopt CMOS over other

technologies.

1.2 Research Goals

The objective of this thesis is to develop a wideband LNA design technique suitable for the

inductively-degenerated LNA architecture. To accomplish this task, first a detailed analysis of

this architecture is presented and the wideband performance of LNA is studied from both the

circuit and the system level perspectives. Afterwards, the effect of different circuit parameters on

the wideband performance of the LNA is discussed. Finally, the results of this research are used

to develop a step-by-step design technique that satisfies the requirements of low noise, high gain,

and the input matching over a wide frequency range.

The proposed wideband design technique is used to successfully design and simulate two

different wideband LNAs in a 0.18μm CMOS technology. The results of these simulations

demonstrate the applicability of the proposed methodology to the design of wideband RF front-

ends needed for many applications such as UWB and multi-standards transceivers.

1.3 Thesis Outline

This thesis is organized as follows: Chapter 2 reviews the fundamentals of the LNA design such

as its noise figure and the input matching. Different LNA architectures, which are suitable for


wideband applications, and their corresponding advantages and disadvantages, are presented.

This chapter emphasizes the need to develop a wideband LNA methodology.

Chapter 3 suggests the use of an inductively degenerated topology as an appropriate

candidate for the wideband LNA design. A detailed analysis of this topology and the underlying

concept of the wideband noise and input matching are presented. Furthermore, the trade-off

among different design issues such as noise, gain, input matching, and power consumption is

addressed.

Chapter 4 demonstrates the simulation results of two different CMOS LNAs designs

using the proposed design technique. Issues related to the layout of high frequency CMOS LNA

are also discussed. Finally, Chapter 5 presents concluding remarks and suggestions for future

work.

Chapter 2 – Background 7

CHAPTER 2

BACKGROUND

In a receiver chain, LNA is usually the first active signal-processing block after the antenna. The

amplitude of the received signal at the input of LNA may vary from few nV (less than -130dBm

for GPS signals) to tens of mV (e.g., large interferers accompanying the signal). The LNA should

be capable of amplifying all these signals without causing any significant distortion.

Furthermore, the sensitivity1 of LNA determines the sensitivity of the overall receiver. This

requires that very little noise from the LNA be introduced to the entire receiver [12]. Another

major requirement of the LNA is to provide a large gain to suppress the noise of subsequent

blocks. This issue will be discussed in detail shortly.

LNAs are usually preceded and followed by passive filters for out-of-band rejections and

channel selection. The transfer function of such filters is usually a function of their termination

impedance. This imposes the requirement of certain input and output impedances, such as 50Ω,

on the LNA. On the other hand, as will be shown in the following sections, the amount of noise

introduced by the LNA is also a function of source impedance. The optimum source impedance,

which results in the minimum noise figure of the LNA, may not be equal to that required by the

preceding stage, e.g., 50Ω. This may result in an LNA having a good input matching and a poor

noise figure or vice versa.

1 The sensitivity of a receiver (or block) is defined as the minimum level of the input signal for which the receiver (or block) provides an acceptable signal quality.


The design of an LNA satisfying all these requirements in a wide bandwidth is even more

challenging and needs a careful study of the different parameters affecting noise, gain, and

linearity. To achieve this goal one needs to develop an accurate mathematical model for the LNA

and find the analytical expressions for noise, gain, and linearity.

2.1 Noise

In communication systems, any signal other than the desired signal is called noise and will

reduce the sensitivity of the overall system. Different sources of noise with different noise

generation mechanisms exist. The dominant sources of noise in integrated circuits are shot noise,

flicker noise, and thermal noise. Shot noise is mainly caused by the hopping of electric charges

over a potential barrier and is specific to nonlinear devices such as diodes and transistors. In

MOS devices, which are the subject of this work, the only source of shot noise is the DC gate

leakage current, and hence it is not considered a major problem [12]. This is in contrast to

bipolar transistors in which base and collector shot noise may significantly degrade the

performance of the overall receiver.

Flicker noise, also known as pink noise, occurs due to the trapping of charges in the

defects and impurities of the channel region in MOS devices [12]. As a general rule, larger MOS

devices experience less flicker noise. The spectral density of this noise is given by:

22

2

.

.m

fnox

K gi

f WLC (2.1)

where K is a device-specific constant, gm is the transconductance of the MOS device, f is the

operating frequency, Cox is the gate-oxide capacitance per unit area, and W and L are the width

and length of the MOS device, respectively.


As can be seen from (2.1), the amount of flicker noise is inversely proportional to the

frequency of operation. Therefore, flicker noise can be a dominant noise source at very low

frequencies. In LNAs where the frequency of the received signal is about several gigahertz,

flicker noise does not play an important role and is usually ignored. It is worth mentioning that in

other receiver stages such as mixers or voltage controlled oscillators (VCO) flicker noise can be

a major problem.

Thermal Noise

Thermal noise is the noise caused by the agitation of carriers in a conductor, and its

spectrum density is given by the following quantity known as available noise power [12].

PNA=kTΔf (2.2)

where k is the Boltzman constant (≈1.38 ×1023 J/K), T is the absolute temperature in Kelvins, and

Δf is the bandwidth of the noise measured in Hz. The value of this quantity for 1Hz of noise

bandwidth at room temperature (290K) is −174dBm and is often called the noise floor of the

system. The noise floor is an important quantity in determining the sensitivity of the receiver

[13].

The available noise power is the maximum power delivered to a load from a noise source.

On the basis of this definition, the thermal noise of each passive or active element can be

modelled with an equivalent voltage or current noise source. To demonstrate this equivalency,

consider the network shown in Fig. 2.1 and the equivalent noise voltage source of the resistor

Rs,2

ne .


Figure 2.1 Thermal noise of a resistor

1

1 1

2 22

1 12max1 max

4R Rn n

R R R

e eP kT f i R R P

RR R

(2.3)

Therefore, the mean square noise voltage over a noisy resistor ( 2ne ) is 4kTRΔf. As a reference

point, the rms voltage noise of a 50Ω resistor is equal to 1nV/ Hz .

Dominant sources of noise in MOS devices

MOS devices act like a trans-conductance in the saturation region, and like a resistance in the

triode region. So, one should expect a thermal noise associated with the carriers in the channel

similar to the noise of carriers in a conductor. Van der Ziel in [14] has derived the expression for

the drain current noise of MOS devices, also known as channel thermal noise:

204nd di kT g f (2.4)

where gd0 is the drain conductance for zero drain-source voltage and γ is a technology-dependant

parameter and has a value of around 2/3 for long-channel devices in saturation (in short channel

devices γ is larger and its value is between 2 and 3) [15].


A careful examination of noise characteristics in a MOS device reveals that channel

thermal noise does not fully take into account all the noise associated with a MOS device [16].

The extra noise can be modelled by introducing a frequency-dependant gate conductance:

2 2

05gs

gd

Cg

g

(2.5)

and an equivalent gate current noise of:

2 4ng gi kT g f (2.6)

where δ is the gate noise coefficient and is also a technology-dependant parameter. Its value is

4/3 for long channel devices and is augmented by a factor of 2 in short channel devices.

Note that the gate current noise is partially correlated with the channel thermal noise and

their correlation coefficient factor is given by:

*

2 2

g d

g d

i ic

i i (2.7)

where c is a complex number and its value is theoretically computed to be around −0.395j for

long channel devices [14]. This value is higher for short channel MOS and an experimental value

of −0.5j is usually assumed for noise calculations.

The exact value of γ and δ depends on the technology and, unless provided by the

foundry, is cumbersome to measure. However, it can be shown that the noise behaviour of an

LNA depends on the ratio of these two numbers and not their exact value. Fortunately, this ratio

is almost a constant (δ/γ≈2) regardless of whether we use long channel or short channel devices.

Hence, one can determine the characteristics of an LNA without knowing the exact values of

these parameters.


Another source of noise in MOS devices that may contribute to the total noise of the

LNA is the noise generated by the distributed resistance of poly-silicon gate [17]. The value of

this resistance is given by:

23g

R WR

n L � (2.8)

where R� is the sheet resistivity of the gate terminal, n is the number of gate fingers in the layout

of the device, and W and L are the width and the length of the MOS device, respectively. The

value of this resistance (and the associated noise) can be decreased through the careful layout of

transistor, and therefore be rendered insignificant in the noise calculations.

Different sources of noise in a MOS device are shown in Fig. 2.2.

(a) (b)

Figure2.2 (a) Dominant sources of noise in a MOS - (b) Thevenin equivalent circuit

Another resistance associated with the gate of MOS devices, known as the non-quasi-

static gate resistance (RG,NQS), is also reported in the literature [20][18][19]. In fact, RG,NQS is the

equivalent series resistance of the Thevenin network representation of the conductance gg and

noise current source i2ng discussed earlier (see Fig. 2.2b).

,

1

5G NQSm

Rg

(2.9)


Noise Figure

Noise figure (NF) is a measure of signal-to-noise ratio (SNR) degradation as the signal

traverses the receiver front-end. Mathematically, NF is defined as the ratio of the input SNR to

the output SNR of the system.

in

out

SNR total output noise powerNF

SNR output noise power due to source (2.10)

NF may be defined for each block as well as the entire receiver. NFLNA, for instance, determines

the inherent noise of the LNA, which is added to the signal through the amplification process.

With the use of the classical two-port network theory, it can be shown that the NF of a noisy

two-port network is given by (Appendix A):

2 2min [( ) ( ) ]n

s opt s opts

RNF NF G G B B

G (2.11)

where NFmin is the minimum achievable NF, Bopt and Gopt are the optimum source susceptance

and conductance corresponding to NFmin, and Rn is an equivalent noise resistance, which

quantifies the sensitivity of NF to departure from optimum conditions. Note that NF is a function

of source admittance seen from the input terminal of the two-port network. To achieve the NFmin,

an optimum admittance, namely Yopt, should be introduced to the network. The expressions for

NFmin and Yopt can be derived for a MOS device by considering a two-port network model for the

MOS device. In this model the gate-source terminal is the input port and the drain-source

terminal is the output port.

Figure 2.3 shows the small signal model of a MOS device (including all sources of

noise), connected to the noise source 2si and the source admittance Ys=GS+jBs.


Assuming that 2ndi and 2

ngi are dominant sources of noise in MOS devices, the following

expressions for NFmin and the noise parameters can be obtained:

Figure 2.3 Two-port network model of MOS device for noise calculations

02

dn

m

gR

g

(2.12)

2(1 )

5opt gsG C c

(2.13)

(1 )5opt gsB C c

(2.14)

2

min

21 (1 )

5 t

NF c

(2.15)

where α is the ratio of gm and gd0 and is equal to one for long channel devices and decreases as

devices shrink to smaller dimensions. It is evident from (2.15) that the minimum noise figure

decreases with the increasing transit frequency (ft). This will be an advantage of using the CMOS

process because, as mentioned in the previous chapter, CMOS scaling into DSM technologies

increases the value of ft.


Figure 2.4 cascade of several noisy blocks

Noise figure: System level considerations

In a receiver path, as the signal propagates from the antenna to digital back-ends, different blocks

may introduce noise to the signal. The overall NF of the receiver depends on the NF of each

block as well as the gain of preceding stages. Intuitively, larger signals are less susceptible to

noise, and this is why the large gain of one stage makes the noise of the following stage less

important. Friis [20] shows that the overall NF of a cascaded system (such as the one shown in

Fig. 2.4) is given by:

321

1 1 2

...tot

NFNFNF NF

A A A (2.16)

where NFi and Ai are the NF and available power gain2 of each stage, respectively. Assuming

that A1 is a large value then NF1 is the dominant term in (2.16). This accounts for the fact that the

low noise of the LNA, i.e., low NF1, is of great importance in the receiver design. Note that NF2

is the NF of the second stage, which is usually a mixer. Mixers usually exhibit much higher NF

than LNAs; therefore, it is essential that the gain of the LNA be large enough (high A1) to reduce

the contribution of NF2 to NFtot.

NFtot determines the sensitivity of the overall receiver. This relation is analytically given

by:

2 The available power gain is defined as the ratio the power available from the network to the power available from the source.


( ) 174 / 10 ( ) 10log( )tot outSensitivity dBm dBm Hz log BW NF SNR (2.17)

where −174dBm/Hz is the available noise power from the antenna (the noise floor) and BW is the

bandwidth of the desired signal, and the last term is the minimum acceptable SNR at the receiver

output, which is a function of minimum required bit-error-rate (BER) at the output of the

demodulator. As can be seen from (2.16) and (2.17), low NF of the LNA greatly improves the

sensitivity of the overall receiver.

2.2 Nonlinear Effects

The dynamic range (DR) is usually defined as the ratio of the maximum input signal that the

circuit can tolerate to the minimum input signal that provides adequate signal quality. The LNA

should possess a large DR to guarantee that it remains linear when receiving weak signals in the

presence of strong interferers. The upper limit of DR in low-frequency applications is usually

defined as the maximum input power that the circuit can handle without going into saturation.

However, in high-frequency applications, non-linear effects such as inter-modulation distortion

or signal compression may be prominent and limit this upper bound

There are many measures of linearity for high frequency circuits, but the most commonly

used are the 1-db compression point (P1dB) and third order intercept point (IP3) [13]. The input

1-dB compression point is usually defined as the amplitude of the input signal at which small-

signal gain drops 1dB below its nominal value (Fig. 2.5). Input signals above the compression

point are usually clipped or saturated at the output; therefore, the compression point is

considered an upper bound on the dynamic range of the LNA.


Figure 2.5 1dB compression point

Another issue that may cause signal distortion is the multiplication of the input signal

with its harmonics, generated due to the nonlinear nature of the realistic systems. This mixing

(multiplication) will produce output terms known as inter-modulation products (IMP). For

instance, if two adjacent sinusoids (also known as “two tones”) are applied to the input of a

nonlinear system, the harmonics of these signals will produce many unwanted components at the

output of the system. The frequency of some of these unwanted components may be very close

to that of the desired signals and cause signal distortion, see Fig. 2.6 (a).

To further illustrate the inter-modulation effect, consider a realistic system with the

following input-output relation:

2 31 2 3( ) ( ) ( ) ( ) ...y t x t x t x t (2.18)

Now assume the input is formed by two closely-spaced sinusoidal components of the same

amplitude:

1 2( ) (cos( ) cos( ))x t A t t (2.19)


Then at the output of the system, the following terms exist in the vicinity of ω1 and ω2 :

First-order terms:

31 1 1 3 1

32 2 1 3 2

9: ( )cos( )

49

: ( ) cos( )4

at y A A t

at y A A t

(2.20)

Third-order IMP terms: 1 2

2 1

31 2 2 3 1 2

32 1 2 3 2 1

32 : cos(2 )

43

2 : cos(2 )4

at y A t

at y A t

(2.21)

(a) (b)

Figure 2.6 (a) Signal spectrum of a nonlinear system - (b) Graphical interpretation of IIP3

In typical systems, α3 is usually a negative number and is much smaller than α1, so for small

input signals the first-order terms, i.e., (2.20), are dominant at the output. However, as the

amplitude of the input signals increases, first-order terms do not grow as fast as the IMP terms

(the former increases linearly with the amplitude while the latter increases proportional to A3).

The input level for which fundamental terms and IMP at the output have the same power is

called third-order input intercept point (IIP3). Mathematically, this can be expressed as follows:


3

3 11

3

3 3 4( 3) 3

4 3

IIPIIP IIP

(2.22)

These calculations are based on the assumption that the terms (9/4α3A3) are negligible in yω1 and

yω2 expressions. However, at the intercept point where the amplitude of signals are quite large,

this assumption no longer holds and therefore the calculated value of IIP3 in (2.22) is just an

extrapolation of the small input behaviour of the system. Nevertheless, in practical systems the

effect of these terms, i.e. (9/4α3A3), is to increase the actual IIP3, and the calculated value of IIP3

may be used without any difficulty. This can also be verified from Fig. 2.6 (b) where the actual

IIP3 is higher than the extrapolated one.

Linearity: System level considerations

The overall linearity of a receiver consisting of a cascade of several blocks depends on the gain

as well as the linearity of each stage. This can analytically be shown by once again considering

the chain of Fig 2.4 and expressing the input-output relation of the different stages in the chain.

However, finding a closed-form expression for the linearity of overall system is rather difficult

and requires some simplifying assumptions. The following expression gives an estimate of the

worst-case IIP3 of the system in terms of the IIP3 of individual blocks in the chain [21]:

2 2 21 1 2

2 2 2 23, 3,1 3,2 3,3

1 1...

IIP tot IIP IIP IIPA A A A

(2.23)

where AIIP3,i and αi are the IIP3 and gain of the i-th stage, respectively. A careful examination of

(2.23) reveals that if each stage in a cascade has a gain greater than unity, then the nonlinearity of

the following stage becomes more critical [21]. This means that the nonlinearity of the LNA, as

the first building block, does not affect the overall nonlinearity as much as the nonlinearity of the


following stages, e.g., mixers, does. This expression also states that the high gain of LNA

degrades the overall linearity of the system. This is in contrast with the NF scenario in which the

high gain of the LNA improves the overall NF. Despite the opposing behaviours of NF and

linearity, designers typically try to maximize the gain of the LNA to achieve a better NF

response.

2.3 Input Matching

To deliver the maximum power from the antenna to the LNA, matching to the impedance of

antenna, e.g., 50Ω, is required at the input port of the LNA. For wideband applications, this

impedance matching should be obtained over a wide frequency range at the input port of the

LNA and is usually a major challenge considering the noise and power consumption

requirements.

To quantify the degree of the impedance matching, it is customary to introduce the

concept of voltage standing wave ratio (VSWR) [22]:

1

1VSWR

(2.24)

where Γ is the reflection coefficient and is defined as

o

o

Z Z

Z Z

(2.25)

In this expression, Z is the actual input impedance and Zo is the characteristic impedance of the

source, which is usually equal to 50Ω. Perfect matching (Z=Zo) results in Γ=0 (−∞ dB) and

equivalently VSWR=1. However, for practical purposes Γ<-10dB is usually sufficient to meet the

matching requirement.


Figure 2.7 Different input matching topologies (a) resistive termination

(b) 1/gm termination (c) shunt feedback (d) inductive degeneration

There exist several architectures that generate the required 50Ω impedance at the input

port of the LNA. Some popular topologies are shown in Fig. 2.7. The simplest method to obtain

matching over a wide range of frequencies is to use the resistive termination illustrated in Fig.

2.7 (a). However, this method suffers from a relatively high NF due to the thermal noise of

resistive termination. Referring all noise sources to the input of the LNA and using the definition

of NF, it is easy to show that:

,

0 0

2

4 12 .g

n MOS

c and i

m

PTotal input referred noiseNF

input noise due to source only KTR f

NFg R

(2.26)

This is just a low-frequency limit for which the gate noise is totally ignored. The actual

NF is much higher and gets even worse at higher frequencies. Another shortcoming of the

resistive termination is that the input power is attenuated by the resistive divider before reaching

the MOS device, and this will reduce the maximum power gain.


An alternative approach to achieve input matching is to use the source of a MOS device

as the input termination, symbolically depicted in Fig. 2.7 (b). In common-gate architecture, the

impedance looking into the source terminal of active device is 1/gm. Therefore, proper bias and

sizing of the LNA will result in 1/gm=50 and satisfies the matching requirement. However, there

still exists the problem of high NF with this architecture. The impedance matching at the input

port yields the following lower bound on the NF of common gate LNA [12]

1NF

(2.27)

This will force a lower limit of around 4.7dB (γ/α ≈ 2) in short-channel devices, which is not an

acceptable value for applications such as GPS receivers.

Shunt feedback amplifier suggests yet another solution for achieving the required

matching at the input port (see Fig. 2.7 (c)). This type of amplifier employs negative feedback to

generate the 50Ω impedance at the input port. This architecture still suffers from the thermal

noise of the shunt resistor; however, the lower bound on NF is usually smaller than that of

resistive and 1/gm terminations. A modified version of this architecture that incorporates series

feedback is widely used in the wideband LNA designs and will be addressed in section 2.5.

To overcome the deleterious effect of real resistors on the NF of LNAs, designers suggest the use

of inductively degenerated LNA to generate the required input impedance. Consider Fig. 2.8

where the small signal model of an inductively degenerated LNA is shown. Writing the

KVL at the input port we obtain:

( ) ( )( ( ) ) ( )in in g s m gs sgs

jv i j L L g v jL

C

(2.28)


Figure 2.8 Small signal model of an inductively degenerated LNA

which yields ( ) 1

( ) ( )( )

inin s g t s

in gs

vZ j L L L

i jC

(2.29)

where ωt=gm/Cgs is the transit frequency of the MOS device. Evidently, the last term in (2.29) is

a real impedance with the advantage that it does not have the thermal noise of a resistor. The

value of source inductance needed to satisfy the input matching, i.e. ωtLs=50Ω, is usually very

small (e.g., a few nH). This small inductance is usually realized using bond-wires with high-

quality factors and hence negligible loss and noise.

One immediate observation from (2.29) is that impedance matching is only achievable at

a single frequency, more precisely, the resonance frequency of series inductors and gate-source

capacitance:

0

1

( )g s gsL L C

(2.30)


Due to the superior performance of L-deg LNA in terms of NF and power consumption, this

architecture has found many applications in industry. In the last few years, several design

techniques have been developed to satisfy the noise, gain, and power requirements of L-deg

LNA for different applications. However, due to the narrowband nature of (2.29), none of these

approaches are suitable for broadband applications.

To summarize, the important requirements of an LNA are low NF, high gain, good input

matching, and good linearity. With these goals in mind, we will now start our study of the

existing wideband architectures. Before doing so, we will introduce the concept of S-parameters,

which is a widely used concept in the context of high frequency amplifier design.

2.4 S Parameters

Two-port networks are described in numerous ways. The most well-known description is to

relate the four variables of input/output voltage/current by using a 2×2 matrix. Depending on

which two of these four elements are selected as the independent variables, different matrices

can be defined. Impedance (Z) matrix, admittance (Y) matrix, and hybrid (H) matrix are the most

common matrices that define the two-port network voltage-current relation. In order to find the

elements of these matrices, certain short and open-circuit tests must be performed on the

network. However, these tests might not be possible at very high frequencies where open and

short tests fail due to the existence of stray capacitances and inductances as well as transmission

line effects.


Figure 2.9 S parameters definition of two-port networks

The inability to perform short and open tests and the possibility of harming the circuit during

these tests suggest the use of an alternative solution to characterize the network at high

frequencies [23]. One popular solution is the introduction of the Scattering parameters (simply

S parameters), which defines the four variables as the incident /reflected input/output voltage

waves (or powers).

The definition of S parameters exploits the fact that a transmission line terminated in its

characteristic impedance does not reflect any power at its termination [12]. To show the

usefulness of this property, consider the block diagram of a two-port network shown Fig. 2.9

where Z0 is the impedance of the source and the load terminations and Eii and Eri are the

magnitude of incident and reflected voltage waves, respectively. The S parameter coefficients are

expressed as:

1 11 1 12 2

2 21 1 22 2

b s a s a

b s a s a

(2.31)

where

1 1 0 2 2 0

1 1 0 2 2 0

/ /

/ /

i i

r r

a E Z a E Z

b E Z b E Z

(2.32)

The normalization to the square root of Z0 makes the square of magnitude of ai and bi equal to

the incident and reflected power at both ports.


Now, if we terminate port two in Z0, which sets a2 equal to zero, and apply a power

source to port one, we obtain the following relations:

2 2

1 1 2 211 21

1 1 1 10 0

r r

i ia a

b E b Es s

a E a E

(2.33)

where s11 is called the input reflection coefficient and is a practical measure for the impedance

matching at the input port of the LNA and s21 represents the forward gain of the amplifier.

If, on the other hand, port 1 is terminated to Z0 and power is sent from port 2:

1 1

1 1 2 212 22

2 2 2 20 0

r r

i ia a

b E b Es s

a E a E

(2.34)

where s12 is the reverse transmission or gain of the network and s22 is called the output reflection

coefficient of the network.

Using these definitions, we can predict that a good amplifier should possess a large s21 to

achieve high gain, small s11 and s22 to possess good input and output matching, and very small s12

to ensure stability and reverse isolation. The typical values of S parameters for an LNA are s11

and s22<-10dB, s21 >10dB, and s12<-40dB, which may vary according to the application.

2.5 Wideband LNA Topologies

The major challenges of a wideband LNA design can be summarized in terms of S parameters

and NF as follows: [24]

Forward gain degradation (decreases in s21) which necessitates some techniques to

compensate the gain roll-off.

Frequency variations of s11 and s22.


Increase in |s12| which will reduce the forward gain and increase the possibility of

oscillation and instability.

NF degradation at high frequencies.

To address these challenges in the design of a wideband LNA, several topologies and circuit

techniques have been proposed in the literature. In This section, we will introduce briefly some

of the popular wideband architectures and briefly discuss their advantages and disadvantages.

Negative Feedback Wideband LNA

The classical approach to satisfy the required impedance matching at the input of a wideband

LNA is to employ negative feedback. This technique will provide a flat gain and a very small

VSWR at the input and output ports, and also it reduces the sensitivity of the circuit to the MOS

device parameters. However, as discussed in the analysis of shunt feedback amplifier, the

feedback circuitry may increase the minimum NF and reduce the maximum achievable gain.

Different topologies of negative feedback amplifier exist in the literature. One of the most

popular variations of negative amplifier is the shunt-series amplifier, symbolically shown in Fig.

2.10 (as a two-port network).

To achieve wideband input and output matching, one should design for zero s11 and s22

after finding the S parameter expressions for this network. Solving for s11=s22=0, yields the

following equation that relates the values of R1 and R2 [24]:

20

21

1

m

ZR

R g (2.35)


Figure 2.10 Two port model of a hunt-series amplifier

An appropriate choice of R1 and R2 values will satisfy (2.35) and hence the input and

output matching. It will also result in a flat in-band forward gain with no dependency on the

MOS device parameters (see [24]). However, (2.35) is only valid in low frequencies where all

parasitic effects may be ignored. In gigahertz applications parasitic capacitances and inductances

become non-negligible and the power gain starts to roll-off. The input and output matching also

degrades significantly in high frequencies.

One implementation of a negative feedback amplifier is shown in Fig. 2.11. In this circuit

[25] the input stage is a common source amplifier and the feedback stage is a common drain

amplifier. A simple analysis of this circuit shows that gm,M2 of the common drain stage controls

the input impedance, while gm,M1 of the common source amplifier contributes to the gain and NF

of the overall LNA. This is in contrast to the 1/gm termination architecture where the gm of the

input transistor is set by the input matching requirements and leaves no freedom for NF

optimization. The main disadvantage of this architecture is the relatively high power

consumption due to the addition of the feedback stage.


Figure 2.11 Common drain feedback LNA

In another work, negative feedback is employed to realize a UWB LNA covering a 7GHz

bandwidth (2 – 9 GHz) [26]. The schematic of this LNA is shown in Fig. 2.12. The input stage

adopts a shunt-series feedback structure to satisfy the wideband input matching. The inverter

configuration at the input is to increase the total trans-conductance (gm1+gm2), and hence the

open-loop voltage gain for a fixed power consumption. The increase in the total trans-

conductance also allows for a higher shunt resistor for a given 3dB bandwidth. This increase in

the value of shunt resistance will lend itself to a lower total NF. Two degeneration inductances

Ls1 and Ls2 are used to partially cancel the parasitic capacitances at the input of the LNA, which

would otherwise devastate the impedance matching at high frequencies. The second stage is a

simple cascode amplifier with a shunt-peaking load that provides the required gain of the entire

LNA.


Figure 2.12 Two-stage LNA for UWB applications

Negative feedback amplifiers may also be used as the second stage of wideband

amplifiers. One example is the work in [27] that combines the benefits of 1/gm termination with

those of the negative feedback amplifier. Fig 2.13 depicts the schematic of this architecture. The

input stage uses a common-gate amplifier to achieve 50Ω impedance matching. However, this

matching sets the value of gm,M1, and another stage is required to provide sufficient gain over the

entire band-width. This second stage is realized by employing M2 in a shunt-feedback

configuration. One drawback of this feedback is that the degradation of forward gain at high

frequencies causes a positive feedback through Rf., thus leading to oscillation at the output. To

alleviate this problem, Lf is connected in series with the shunt resistor, Rf. This will reduce the

feedback at high frequencies and also improve the gain flatness. Ld1 and Ld2 are inductive loads

to compensate the gain degradation at high frequencies.


R1

R2Vbias2

Vbias1 M1

M2

Lf

Cf

Ld1

Ld2

Figure 2.13 Two stage wideband LNA for UWB applications

In [27], a UWB LNA is successfully designed and simulated using this two-stage

architecture.

The aforementioned trade-offs among power, bandwidth, and gain are a serious drawback

of any feedback system. For illustration purposes, consider the conceptual schematic of a shunt

feedback amplifier as shown in Fig 2.14. The input impedance is given by

Zin(s)=Rs/(1+sRsCin),where Rf and A are chosen in a way that Rf /(1+A)=Rs. In order to achieve

input matching at 10GHz, i.e., |Γ|<-10dB, the input capacitance (Cin) is limited to as low as

200fF [28]. This limits the width of the input transistor and hence the maximum gain of this

stage. To overcome this problem, most of the feedback amplifiers must include a second stage to

boost the gain. Two stages of gain directly translate into higher power consumption, which is not

a desirable outcome.


Figure 2.14 Simplified block diagram of a shunt-feedback LNA

Thermal-noise-cancelled Wideband LNA

Feedback amplifiers, as discussed earlier, typically require two stages of amplification in order to

provide sufficient gain and thus dissipate a large amount of power. Also note that the input

impedance in a feedback amplifier is a function of the amplifier gain. However, this dependency

is not straightforward, and the impedance matching is susceptible to the variations of the gain.

To overcome these shortcomings, [29] suggests the use of a noise-cancelling feed-forward

technique that decouples noise and input matching requirements. The conceptual schematic of

this LNA is shown in Fig. 2.15. The noise current of the amplifier, In,i flows out of the MOS

device and passes through R and Rs. Therefore, the instant noise voltages at nodes X and Y have

the same polarity. Conversely, the signals at X and Y are of opposite polarities, simply due to the

negative gain of the amplifier. This difference between the sign of signal and noise suggest the

possibility of cancelling the noise while boosting the signal up.


+R

Rs

-Av

Node X

Node Y

in,i

Figure 2.15 Schematic of thermal noise cancelling technique

To do so, another gain stage is inserted between the first stage and the output. The voltage at

node Y (signal plus noise) is added with the properly scaled negative replica of the voltage at

node X (the block shown by −Av generate this replica)[30]. By the proper choice of Av, the noise

contribution of the MOS device becomes equal to zero, and a low NF can be obtained over a

wide range of frequency. The analysis in [30] derives the appropriate value of Av in terms of

circuit elements R and Rs:

1vs

RA

R (2.36)


It is also shown that, under these conditions, the noise contribution of different components is as

follows:

02 2

2

1

0

21 3( )

LNA MOS R A

MOS

sR

d sA

m s

NF EF EF EF

EF

REF

Rg R

EFg R R R

(2.37)

where the excess noise factor, EF, is used to quantify the contribution of different noise sources

to the NFLNA. Also note that the impedance of the LNA equals 1/gm1. Since the term gm1 is not

present in the NFLNA expressions, NF optimization and input matching can be done separately.

The idea of noise cancellation can be extended to any type of amplifier that has 1) a stage of

impedance matching, 2) an auxiliary amplifier for sensing the voltage across a real input source,

and 3) a circuit to combine the output of two amplifiers to cancel out the noise of the impedance

matching stage. Some implementations of this idea are proposed in the same paper.

Despite all these benefits, the dominant pole at the input (node X) may limit the

bandwidth at high frequencies. Furthermore, due to the existence of the parasitic capacitances,

NF increases quadratically with the frequency. These effects, along with the high power

consumption required by the two amplifiers, may limit the applications of this architecture.

Balanced Amplifier

A typical block diagram of a balanced amplifier is shown in Fig. 2.16 [24][31]. It consists of two

amplifiers in parallel and two 3dB Lange or hybrid couplers. The basic operation is as follows:


Figure 2.16 Block diagram of balanced amplifier

The input signal is split into two quadrature components (equal but with a 90o phase shift)

by the input hybrid coupler. The two quadrature signals are then amplified using two identical

LNAs. The output coupler combines the output signals of the two amplifiers by introducing an

additional 90o phase shift, thus bringing them in phase again [25]. Denoting the S parameters of

two amplifiers by SijA and Sij

B, one can relate the S parameters of the entire amplifier to that of

individual branches as follows:

11 11 11

1

2A BS S S

21 21 21

1

2A BS S S (2.38)

12 12 12

1

2A BS S S

22 22 22

1

2A BS S S

The advantage of this architecture is that it possesses a very good matching at the input and

output ports and continues to operate even if one of the amplifiers fails to function. However,

this architecture suffers from the increased power consumption of two amplifiers, increased

circuit size, and the bandwidth reduction caused by the couplers.


Figure 2.17 Schematic of a basic distributed amplifier

Distributed Amplifier

Distributed amplifiers (DA) (also known as travelling wave amplifiers) employ an architecture in

which several active devices are connected in parallel [32]. A basic distributed amplifier is

shown in Fig. 2.17. The output current of individual amplifiers combine in an additive fashion,

and this dictates a relatively low gain for this architecture. The advantage of this architecture

comes from the fact that the input capacitances of these amplifiers are distributed in an LC

network which allows for the realization of amplifiers with large bandwidths. In fact, the series

inductive elements and capacitances of MOS devices form an artificial transmission line, which

allows the flow of the signal to the end of the gate line. The signal fed to the gate of the MOS

device is transferred to the drain line through the trans-conductance (gm) of the device. If the

phase velocity on the gate and drain lines are identical, then the signals at the output add in the

forward direction as they arrive at the output. Many wideband LNAs in CMOS have been


realized using DA architectures [33][34]. However, the large power consumption of this

architecture is a major drawback and makes it unsuitable for low-power portable systems.

These architectures are the most well-known works in the literature of wideband LNA

design. Although successfully implemented for some applications, there are still many issues that

need to be addressed when it comes to the design of highly integrated LNAs. For instance, the

large power consumption of most of these architectures is a major problem, which may eliminate

the feasibility of their integration for low-power multi-standard applications. Moreover, a well-

established methodology is needed to provide the general guidelines for the design of wideband

and multi-standard LNAs.

Chapter 3 – Wideband LNA Methodology 38

CHAPTER 3

WIDEBAND LNA METHODOLOGY

As discussed in chapter two, the inductively degenerated LNA (L-deg LNA for short) satisfies

the input matching requirement without introducing the additional noise attributed to a real

resistor. In addition, compared to other architectures, L-deg LNAs consume less power and

therefore are especially suitable for low-power applications.

The design of L-deg LNA involves many trade-offs among gain, NF, power consumption,

matching, and linearity. Several design techniques have been proposed to satisfy these

requirements for different applications. The classical noise matching (CNM) technique [35],

simultaneous noise and input matching (SNIM) technique [36], power constrained noise

optimization (PCNO) technique [16], and power-constrained simultaneous noise and input

matching (PCSNIM) technique [37][38] are among the many design procedures developed for

this architecture.

All these design techniques have been developed based on the assumption of narrowband

input signal; i.e., the bandwidth of the input signal to be amplified is much smaller than the

centre frequency. However, low power consumption and the low NF capabilities of L-deg LNAs

have motivated us to develop a new methodology for broadband applications.

To study the requirements of wideband noise and input matching and establish a well-

defined design approach, a careful analysis of this architecture is presented in the following

sections. Also, the principles of operation and the role of different parameters on the

performance of the wideband L-deg LNA are discussed in detail.


3.1 Power gain and Impedance mismatch factor

It is a well-known fact that the power delivered from a power source to a load reaches its

maximum value if the source impedance is the complex conjugate of the load impedance.

Consider the basic block diagram of an amplifier shown in Fig. 3.1.

Figure 3.1 Conceptual diagram of power transfer in an amplifier

The current and power delivered to the system, Iin and Pin, are:

21

2s s

in in ins in s in

V VI P R

Z Z Z Z

(3.1)

When Zin = Zs* (Rin = Rs , Xin = -Xs) or, in terms of reflection coefficient Γin = Γs

*, the maximum

available power, denoted by PA, is transferred to the load:

*

21

2 4in s

sA in

s

VP P

R (3.2)

However, in general, when Zin ≠ Zs*, the input power to the system may be written as:

2 2

12

41 1.

2 2 4

A

ss sin in A

s in ss in

PIMF

VV R RP R IMF P

Z Z RZ Z

(3.3)

where IMF is the impedance mismatch factor (IMF)[39][40].


12

1

4 s

s

R RIMF

Z Z

2

4' T in

T in

R RIMF

Z Z

Figure 3.2 Input mismatch factor with matching network

Recall from (2.24) that VSWR is a measure of the impedance matching at the input port of the

LNA. IMF is another way of expressing the quality of matching and is related to VSWR through

the following relation

1 1

1 1

IMFVSWR

IMF

(3.4)

IMF also determines how much power is absorbed by the input port of the amplifier. For

instance, if IMF =1 then the power delivered to the system is equal to PA and the power gain

reaches its maximum value.

Now consider Fig. 3.2 where a lossless matching network is inserted between the source

and the input port of an amplifier. In this figure ZT is the series impedance of the Thevenin

equivalent of the circuit to the left of the amplifier. Note that IMF and IMF’ represent the value

of the impedance mismatch factor at the two reference planes of A and B, respectively. An

analysis of this network, assuming lossless passive elements in the matching network, proves that

IMF = IMF’ [41]. This is an important observation because it shows that the choice of reference


plane has no effect on the value of IMF, and hence the power gain. So, we can choose a

reference plane that best suits our application, e.g., simplifies the analysis.

Ls

Zs

iin

Matchingnetwork

vS

TheveninEquivalent

iout

vin

Rs

Zs

Zin

VT

ZT

(a) (b)

Figure 3.3 (a) Narrowband LNA (b) Wideband LNA

Let us now apply these concepts to an L-deg LNA. Consider Fig. 3.3 (a) which depicts the input

port of a typical narrowband LNA. The overall trans-conductance of the amplifier, under the

matching requirements, is given by:

1. .

( ) 2gsout out t

m min gs in gs s t s s

vi iG g

v v v C R L R

(3.5)

where ωtLs=Rs is the input impedance at the resonance and ωt=gm/Cgs is the transit frequency of

the amplifier. The last expression implies that the transconductance of the LNA, at the resonance,

is independent of the MOS device transconductance and its width. Therefore, the only way to

boost the gain of a matched amplifier is to increase the transit frequency of the MOS device.


Now, consider Fig. 3.3 (b) which shows a wideband LNA and its wideband matching

network. For our convenience we move the reference plane to the gate of the MOS device. Under

wideband matching conditions, we have Zin=Z*T over the entire range of frequency. If the

matching network is lossless, the power conservation theorem states that:

2 21 1. .

2 4 2 4s T

As T

V VP

R R (3.6)

Also note that, the current into the gate of the input transistor is given by iin=VT/(RT+Rin). Using

(3.6), the overall transconductance Gm can be written as:

1. . . . .

( ) 2gsout out tT T

m ms gs T s gs in T s T s

Vi i V RG g

V V V V C R R R R R

(3.7)

where the last expression assumes Rin=RT over the entire band of interest. This equation shows

that Gm is inversely proportional to the frequency of operation. Therefore, if one can compensate

the 1/ω term in Gm with an appropriate load at the output, constant gain will be obtained over the

wide band of interest. This compensation can be accomplished by employing an inductive load at

the output of the LNA. More discussion on how to design the output load will follow shortly.

The foregoing discussion suggests that if we achieve input matching at the gate of the

MOS device, i.e., the new reference plane, then it is possible to achieve a constant gain over a

wide frequency range. To achieve this goal and also maximize the power gain, IMF should be as

close to one as possible over the entire band of interest.


Figure 3.4 block diagram of a unilateral amplifier with port matching

To include the effect of IMF on the power gain of the LNA, consider Fig 3.4, which

shows a unilateral1 amplifier and its input and output matching networks. It can be shown that

the total unilateral power gain (from source to load) is given by [24]:

2 22

212 2

11 22

1 1

1 1S L

TU

S L

G SS S

(3.8)

where Sij are the S parameters of the amplifier and ΓS and ΓL are the source and load reflection

coefficients, respectively. This equation is in terms of reflection coefficients and should be re-

expressed in terms of impedances to explicitly reflect the effect of IMF. Note that the maximum

power gain results when both the input and output ports are matched (i.e., ΓS =S*11 and ΓL =

S*22):

2

max 212 2

11 22

1 1. .

1 1G S

S S

(3.9)

1 Unilateral amplifiers possess zero reverse power gain (S12 = 0) and are more flexible to design. There are several techniques to make an ordinary amplifier unilateral, one of which is the use of cascode architecture. In the following sections, we will further investigate the properties of this architecture.


MatchingNetwork

v2ns

i2ng gg Cgs gmvgs i2

nd

Ls

Rs

Reference Plane

Zin Zs

Figure 3.5 Small signal model of an inductively degenerated LNA

Now, if there is an impedance mismatch at the input port of the LNA, the available power gain

of the LNA can be written as the product of the maximal power and IMF:

max2

4

( )s in

LNAin S

IMF

R RG G

Z Z

(3.10)

where Zin are ZS are the input and source impedances at the reference plane shown in Fig. 3.4.

This last expression incorporates the effect of input port on the gain of the LNA and is

extensively used in the development of the proposed LNA design technique

3.2 Wideband noise and input matching2

The generic small-signal model of an inductively-degenerated CMOS LNA is shown in Fig. 3.5.

This model is used to study the different parameters affecting the design and performance of

LNA.

2 All the calculations and impedances in this section are based on the small signal model and the reference plane

shown in Fig. 3.5


In this model i2nd and i2

ng are dominant sources of noise and their respective power

densities are given in (2.4) and (2.6).

Recall from chapter two that the NF of a two-port network is given by:

2 2min [( ) ( ) ]n

LNA s opt s opts

RNF NF G G B B

G (3.11)

This expression shows the dependency of NF on the admittance of the source seen from the gate

of the transistor. To make this expression compatible with that of the gain formula in (3.10), it is

convenient to re-express (3.11) in terms of source impedance rather than source admittance. The

new expression for NFLNA is as follows:

2 2min 2

[( ) ( ) ]nLNA s opt s opt

s opt

RNF NF R R X X

R Z (3.12)

where Xopt and Ropt are the optimum source reactance and the optimum source resistance, and

|Zopt|2 is the magnitude of the optimum impedance. Analytic expressions for Yopt (or Zopt)

3, NFmin,

and Rn can directly be calculated by applying KVL/KCL to the circuit shown in Fig. 3.5.

Calculations are tedious and are presented in Appendix B. The results of these calculations are

summarized below:

02

dn

m

gR

g

(3.13)

2

min

21 (1 )

5 t

NF c

(3.14)

2

2 22

(1 | | )

5Re{ }

(1 | | )[ (1 | | ) ]

5 5

opt

gs

c

Zc

C c

(3.15)

3 Throughout this section we interchangeably use Re{Zopt} for Ropt and Re{Zin} for Rin


222

(1 )5

Im{ }(1 )

(1 )5 5

opt s

gs

c

Z Lc

C c

(3.16)

As it is evident from (3.13) and (3.14), the expressions for Rn and NFmin are

approximately equal to that of a MOS device without the degeneration inductance. This is due to

the fact that a lossless inductor does not introduce additional noise to the circuit.

Also, we need to find the input impedance at the gate of the transistor in order to

calculate the power gain expression in (3.10). The input impedance at the gate plane, ignoring

the losses of inductors, is given by

Re{ } m sin t s

gs

g LZ L

C (3.17)

1Im{ }in s

gs

Z LC

(3.18)

Now that GLNA and NFLNA expressions are related to the design parameters of the LNA, we can

study the requirement of simultaneous noise and input matching for the L-deg LNA.

To obtain the wideband noise and input matching, the source impedance seen from the

gate of the input transistor (Zs shown in Fig. 3.5) should be the complex conjugate of the input

impedance, Zin (to deliver the maximum power) and at the same time be equal to Zopt (to achieve

NFmin). Thus the following four conditions should hold over the entire frequency band of interest:

Re Re

Im Im

Re Re

Im Im

opt s

opt s

in s

in s

Z Z

Z Z

Z Z

Z Z

(3.19)

Combining the above criteria, simultaneous noise and input matching are achieved when:


*in optZ Z (3.20)

To satisfy this equation we should analyze the real and imaginary parts of the two

impedances Zin and Zopt.

As can be seen from (3.16), Im{Zopt} is of the form of -Ls+K/(Cgs) which is the

negative of Im{Zin}in (3.18), if K=1. K=f(α, γ, δ) is a technology-dependant parameter, and its

value approaches 1 as the MOS devices scale down to smaller dimensions (K0.7 for 0.25m

and K0.8 for 0.18m technology). Furthermore, at high frequencies, the inductive terms in both

expressions become dominant and the effect of the capacitive terms in (3.16) and (3.18) fade

away, further improving the matching [42].

On the other hand, the matching of Re{Zopt} and Re{Zin} in a wide frequency range is very

challenging. This is due to the fact that the former is frequency-dependant while the latter is

constant and bias-dependant (proportional to the cut-off frequency, t). However, Re{Zin} is also

a function of Ls and by the proper choice of this inductance we can optimize the circuit for

wideband operation. Before proceeding, note that Re{Zopt} is in the form of m/(Cgs), where

m=f(α, γ, δ) is again a technology-dependant parameter. The expression for Cgs of a MOS device

in the saturation region is [43]:

2

3gs oxC WLC (3.21)

So once we choose the width of the input transistor based on the power budget and the

NF requirements (to be discussed in section 3.4), Re{Zopt} is only a function of the frequency.

The frequency range of the LNA (e.g., 3-5GHz for UWB applications) sets the valid range of

Re{Zopt} over which the optimization should be carried out. To explain the details of this


optimization, we rewrite GLNA and NFLNA equations when there is a mismatch among Re{Zopt},

Re{Zs}, and Re{Zin}as follows:4

max2

4

( )s in

LNAin S

R RG G

R R

(3.22)

2min 2

( )nLNA s opt

s opt

RNF NF R R

R Z (3.23)

where Rs is the real part of the source impedance and should be a compromise between Rin and

Ropt. As it is evident from (3.22) and (3.23) GLNA and NFLNA are functions of Rin and Ropt.5 The

idea behind this optimization is to find a value of Rin, i.e., Ls, for which we can satisfy both

requirements of NF ≤ NFmax and G ≥ Gmin where NFmax and Gmin are the maximum tolerable NF

and the minimum acceptable G of the LNA.

Note that the term Rs is present in both GLNA and NFLNA expressions. However, the design

of the matching network that generates Rs, must be done after we satisfy the conditions for the

wideband matching. Therefore, different assumptions about the value of Rs can be made at the

early stages of the design. Since the value of Rs varies between Rin and Ropt, one pessimistic

assumption is to assume Rs = Ropt for the GLNA expression and Rs=Rin for the NFLNA expression.

Designing the LNA in this way guarantees that we will still meet the requirement of

simultaneously high GLNA and low NFLNA, even in the presence of some impedance mismatch at

the input port. Using this assumption, the graphs of GLNA and NFLNA are plotted vs. Rin and Ropt,

as shown in Figs. 3.6 and 3.7

4 These expressions assume Im{Zs}=Im{Zopt}= −Im{Zin}.5 This statement assumes that |Zopt|

2= D Ropt2 where D is a constant. This assumption will be justified later in this

chapter.


Figure 3.6 NF of LNA vs. Re{Zin} and Re{Zopt} for UWB applications in 3-5GHz

for input transistor width of 75μm

Figure 3.7 Gain of LNA vs. Re{Zin} and Re{Zopt} for UWB applications in 3-5GHz

for input transistor width of 75μm


50 60 70 80 90 100 11014.5

15

15.5

16

16.5

17

17.5

18

18.5Re(Z

in) = 60 ohms

Re(Zin) = 78 ohms

Re(Zin) = 96 ohms

Re(Zopt

) (ohms)

Gai

n (d

B)

Figure 3.8 Gain of LNA vs. Re{Zopt} (ω) for several values of Re{Zin} (Ls)

50 60 70 80 90 100 1100.8

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8Re(Z

in) = 60 ohms

Re(Zin) = 78 ohms

Re(Zin) = 96 ohms

Re(Zopt

) (ohms)

NF

(dB

)

Figure 3.9 NF of LNA vs. Re{Zopt} (ω) for several values of Re{Zin} (Ls)


In order to perform the optimization we should examine the vertical slices of both graphs

of GLNA and NFLNA. Each of these slices correspond to a different value of Ls (i.e., Re{Zin}). The

graphs of NFLNA and GLNA for several values of Ls are shown in Figs. 3.8 and 3.9. It can be seen

that the best NFLNA and GLNA are obtained for Re{Zin}≈ 78Ω6.

To verify the results of our calculations, we also simulated the circuit using Agilent

advanced design systems (ADS). The results of this simulation show an optimum value of

around 75Ω for Re{Zin} and are illustrated in Fig. 3.10.

Figure 3.10 Graphs of Re{Zin} and Re{Zopt} vs. frequency for UWB applications in 3-5GHz (W=75μm)

6 Now we can justify our assumption in footnote 5: For the optimum value of the degeneration inductance we have

Rin≈Ropt(ω), or in terms of circuit parameters ωtLs≈m/ ωCgs, where ω varies over the frequency band of interest. On

the other hand, Xopt(ω)=k/ ωCgs- ωLs. Note that 1) ωLs <<ωtLs=m/ ωCgs and 2) k and m are comparable values.

Therefore ωLs<< k/ ωCgs and we may write Xopt(ω)≈ k/ ωCgs. So, Xopt=nRopt where n=k/m and is a constant.

Therefore |Zopt|2=Ropt

2+ Xopt

2 = (1+n2) Ropt2=D. Ropt

2 where D is a constant.


As Fig. 3.10 shows Re{Zin} is not quite a constant value and varies slightly over the band of

interest. This is mainly due to the parasitic capacitances of MOS devices (e.g., Csb) which

become non-negligible at very high frequencies. Therefore, calculations based on the simplified

small-signal model of Fig. 3.5 give an estimate of the optimum values and are not exact.

Consequently, advanced CAD tools with accurate models should be used to design the circuit for

wideband performance.

3.3 SNR-based Optimization Technique

So far our objective was to optimize the LNA over a wide bandwidth based on the assumption

that the LNA is a stand-alone block with certain requirements (NFLNA<NFmax and GLNA>Gmin).

However, in a more realistic scenario where the LNA is followed by the rest of the receive chain;

a better approach is to include the effects of the following blocks and optimize the performance

of the overall system rather than the LNA as a single block.

Previous work in the design of LNA attempted to include the trade-off between the

minimum NF and maximum gain by introducing the concept of noise measure (NM) [44] and

optimizing its value at the frequency range of operation:

1

1 1/

NFNM

G

(3.24)

This formula is obtained by considering the definition of NF for a cascade of an infinite number

of identical LNA stages, that is:

2

1 1...tot

NF NFNF NF

G G

(3.25)


where G is the available power gain of each LNA stage. Yet, this definition does not

properly reflect the effect of following stages in a realistic RF front-end where LNA is usually

followed by a mixer and not an identical LNA.

LNARF FilterEquivalent Block

with NFeq

Figure 3.11 Equivalent model of RF front end

To include these effects, consider the system of Fig 3.11, in which LNA is taken out of the

receiver chain and the rest of the system is treated as a single block with an equivalent NF, NFeq.

The expression for the SNR at the output of the receiver is given by:

/in in

tot outout LNA eq LNA

SNR SNRNF SNR

SNR NF NF G

(3.26)

where NFLNA and GLNA are the NF and available power gain of the LNA, respectively. In order to

obtain the best SNRout, this expression should be optimized using the equations for GLNA and

NFLNA in (3.22) and (3.23). After this substituting we observe that SNRout is an explicit function

of the source resistance, Rs. The value of Rs that maximizes the SNRout expression can be found

by taking the first derivative of SNRout with respect to Rs:

0out

s

SNR

R

(3.27)


After some algebraic manipulations we have:

2 3 2 2max

, 2 2max

4( 1) 16

4( 1) 16

eq opt in in n opt

s opt

eq opt in in n

NF Z R G R R RR

NF Z R G R R

(3.28)

As can be seen, the optimum source resistance (Rs,opt) is a function of input resistance, Rin, and

the optimum resistance, Ropt. Also note that Gmax and Rn expressions are provided in (3.9) and

(3.13), respectively.

A few interesting observation can be made from the Rs,opt expression in (3.28). First,

assume that NFeq is considerably high, i.e., NFeq→ ∞, then (3.28) reduces to Rs,opt ≈ Rin. This

result can be interpreted in the following way: when the noise of blocks following the LNA is

very high, the dominant term in the denominator of (3.26) is the term NFeq/GLNA, and therefore

GLNA should be very large to suppress the contribution of NFeq. Therefore, in the trade-off

between Rin and Ropt, Rs,opt should be equal to Rin to maximize the gain. As the second special

case, assume that NFeq is very small, i.e., NFeq→1, then we obtain Rs,opt ≈ Ropt . This result is also

intuitively satisfying, for NFLNA is now the dominant term in SNRout expression and hence Rs

should be equal to Ropt over the entire band to minimize NFLNA (maximize SNRout).

Another important situation occurs in narrow-band applications where it is possible to

match Ropt and Rin at a certain frequency. Therefore we obtain Rs=Ropt=Rin from (3.28), which is

the same criteria used in classic narrowband design techniques. For narrowband applications this

requirement can be satisfied by a proper choice of Ls that guarantees Rin =Ropt at the frequency of

operation. To complete the design, an appropriatematching network should then be inserted

before the amplifier to produce Rs=Ropt at the single frequency of operation.


In wideband applications, we can use the expression in (3.26) to plot SNRout vs. Re{Zin}

and Re{Zopt} (Fig. 3.12) and then find an appropriate value of Re{Zin}, which results in the best

overall SNRout over the entire frequency band of interest.

Figure 3.12 SNRout vs. Re{Zin} and Re{Zopt} for UWB applications in 3-5GHz

(NFeq=20dB, W=75μm and Gmax =20dB)

This last task can be accomplished by examining the vertical slices of SNRout vs. Re{Zopt} (or

frequency) and choose the one that results in the best overall SNRout7 The Ls corresponding to this

particular slice is the optimum value of the source degeneration inductance. Graphs of SNRout vs.

Re{Zopt} for different values of Re{Zin} are shown in Fig. 3.13.

7 One measure for the best overall SNRout is the average value of SNRout taken over the entire bandwidth.


50 60 70 80 90 100 1104.4

4.6

4.8

5

5.2

5.4

5.6

5.8

Re(Zopt) (ohms)

SN

Ro

ut (

dB)

Re(Zin) = 60 ohms

Re(Zin) = 78 ohms

Re(Zin) = 96 ohms

Figure 3.13 SNR of LNA vs. Re{Zopt} (ω) for several values of Re{Zin} (Ls)

Thus far we have studied the effect of NFeq variations on the value of Rs,opt. We observed

that Rs,opt takes different values over the entire bandwidth to balance the effect of NFeq and NFLNA

on the SNRout. Now, we should study how NFeq variations may affect the optimum value of Ls

obtained from the graphs of Fig. 3.12 and Fig. 3.13. For this purpose SNRout is plotted vs.

Re{Zopt} and Re{Zin} for different values of NFeq and the optimum Ls, i.e., Rin,opt is found for each

of the SNRout plots (by examining different slices of SNRout for each of these plots). The graph of

Fig. 3.14 depicts the variations of Rin,opt vs. NFeq for our UWB example. As can be seen from this

figure, for large variations of NFeq (from 0 to 40dB) Rin.opt varies in a very small range (from 79Ω

to 73Ω). This is an interesting observation because it reflects the fact that the optimum value of

Rin is almost independent of NFeq variations. Also note that the Rin,opt obtained in this analysis


(73Ω -79Ω) is approximately equal to that of the standalone LNA analysis in the previous section

(Rin=75Ω).

0 5 10 15 20 25 30 35 4073

74

75

76

77

78

79

NFeq (dB)

Rin

,op

t (oh

ms)

Figure 3.14 Optimum value of Re{Zin} (Ls) for variations of NFeq

To summarize, we can use either the stand-alone or the SNR-based design technique to

find the optimum value of Ls (Rin). After finding the appropriate value of Rin, we must design a

matching network to produce the required Rs,opt over the entire band of interest; see (3.25).

However, for most practical purposes, it may not be possible to design such a matching network

that tracks the value of Rs,opt with the variations of the frequency. Therefore, we may

alternatively match Rs to either Rin or Ropt, i.e., satisfying GLNA and NFLNA requirements for the

stand-alone analysis.


3.4 Proposed Design Technique

Thus far, we have studied the requirements for wideband noise and input matching from both

circuit and system level perspectives. Now we can develop a design technique based on the

analysis we performed in the last section.

The design parameters of L-deg LNA are the overdrive voltage of the input transistor,

Vov, the width of the input transistor, W, and the source degeneration inductance, Ls. By

appropriately choosing these parameters, we should satisfy the requirements of low power

consumption, low NF, and simultaneous noise and input matching at the input port. The

conditions needed to satisfy the wideband noise and input matching is discussed in detail in

Section 3.3. In this section, we study the NF and power requirements from a circuit-level

perspective and find their corresponding expressions in terms of circuit parameters.

Using the expression for the drain current of a MOS device the power dissipation of an L-

deg LNA can be written as [12]:

( )[(( ) || )]2

n oxD DD D gs t gs t sat

C WP V I V V V V LE

L

(3.29)

where μn is the mobility of electrons, Esat8 is the velocity saturated electric field, and Vt is the

threshold voltage of transistor. After slight simplifications, (3.29) can be rewritten as:

2

1D DD ox sat satP V WLC E

(3.30)

where vsat=μnEsat/2 is the saturation velocity and ρ is called the normalized overdrive voltage and

is given by:

8 Esat is the field strength at which the carrier velocity has dropped to half the value extrapolated from low-field

mobilities.


gs t

sat

V V

LE

(3.31)

As evident from (3.30), the total power consumption is a function of W and Vov. Fig. 3.15 shows

the contour plot of power consumption in the design space of W and Vov. The requirement for

certain power consumption for the LNA, e.g. 10mW, limits our design space to one portion of

the W-Vov plane.

Now, remember the equation of NFLNA from (3.9):

2 2min [( ) ( ) ]n

LNA s opt s opts

RNF NF G G B B

G

To achieve low values of NFLNA we should guarantee 1) NFmin is a small value and 2) Rn is as

small as possible to suppress any deviations from optimum conditions, i.e., Ys=Yopt. To satisfy

these two conditions let us study the two expressions again:

2

min

21 (1 )

5 t

NF c

(3.32)

02

dn

m

gR

g

(3.33)

To minimize the NFmin in (3.32) transit frequency, ωt, should be much higher than the operating

frequency, ω. Recall from chapter two that the expression for ωt is gm/Cgs, where gm is the

transconductance of the device and can easily be found by differentiating ID with respect to Vov:

0

02

1 / 2( )

(1 )d

Dm n ox gs t d

ov

g

I Wg C V V g

V L

(3.34)


0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

40

60

80

100

120

140

160

180

200

Vov (volts)

Wid

th o

f in

put

tran

sist

or (

um)

10mW

10mW

10m

W

20mW

20mW

20m

W

30mW

30mW

30mW

30mW

40mW

40mW

40mW

50mW

50mW

50mW

60mW

60mW

60mW

69mW

69mW

69mW

79mW

79mW

89mW89m

W99mW

99mW

108mW108m

W

118mW

118mW

128mW

138mW

147mW

157mW

167mW

177mW

Figure 3.15 Contour plots of total power consumption

The substitution of Cgs and gm from (3.20) and (3.30) yields the following expression for the

transit frequency:

2

2

/ 23

( )

2

sat sat ovn ov

sat ovmt

gs

E L E VV

LE Vg

C L

(3.35)

Therefore, ωt is only a function of Vov, and the graph of this dependency is shown in Fig. 3.17.

Using this graph we can find a Vov,min such that for Vov> Vov,mn we satisfy ωt>> ω in the

frequency range of operation, e.g. Vov>200mV is sufficient for UWB applications .

Rn, as seen from (3.33), is a function of actual transconductance (gm) and zero drain-

source voltage transconductance (gd0). Note that the relation between gm and gd0 is earlier defined

in (3.34).


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 110

20

30

40

50

60

70

80

Vov

(volts)

Tra

nsit

Fre

quen

cy (

GH

z)

Figure 3.16 Transit frequency (ft) vs. overdrive voltage

By substituting gm and gd0 in (3.33), we find that Rn is also a function of width (W) and overdrive

voltage (Vov). Fig 3.17 shows the contour curves of Rn vs. W and Vov. For small values of Vov both

the gm and gd0 increase linearly with Vov and hence, Rn decreases rapidly. As Vov further increases,

the velocity saturation phenomenon occurs and gm becomes almost constant. However, gd0 keeps

increasing in a linear fashion, and this causes Rn to roll up after a certain value of Vov. Therefore,

for a fixed device width, there exists an optimum Vov for which Rn is the minimum (Fig. 3.17).

Now the steps of the proposed power constrained wideband simultaneous noise and input

matching design technique, in short PCWSNIM, can be explained as follows:

The contours of power consumption and equivalent noise resistance (Rn) are plotted in the

design space of W and Vov. Parameters W and Vov are chosen in a way that the pair (Vov,

W) meets the power consumption requirement and minimizes the Rn.


Once Vov and W are chosen, Re{Zopt} is only a function of frequency; see (3.15). So, we

can plot NFLNA and GLNA vs. Re{Zin} and Re{Zopt} and find the optimum value of Re{Zin},

and the corresponding Ls, that achieves the best NFLNA and GLNA over the frequency range

of interest.

A suitable matching network should be designed to satisfy the input matching over the

entire band of interest.

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

40

60

80

100

120

140

160

180

200

Vov

(volts)

Wid

th o

f in

put

tran

sist

or (

um)

Figure 3.17 Contour plots of equivalent noise resistance (Rn)

The last task should be accomplished using lossless passive elements (capacitors and inductors).

A number of architectures can be used to generate the required wideband impedance matching

network, some of which will be introduced in section 3.5.


Additional considerations

To complete the discussion, we now study the existing trade-offs among different requirements

and how they may affect the proposed PCWSNIM design technique. Assume we decrease our

power budget and want to study the feasibility of designing a ultra low-power wideband LNA. A

low-power budget translates directly into small values of transistor width. This is because a low-

power budget limits the location of the point (W,Vov) to a very small portion of W-Vov design

space. Since the requirement of Vov>Vov,min from the previous section, the value of W has to

decrease in proportion to the power budget.

Recall from equation (3.15) that Re{Zopt}=m/ωCgs and note that 1/Cgs acts as a multiplier

in this expression and amplifies the variations of Re{Zopt} over a wide frequency range.

Therefore, a small value of transistor width, i.e., small Cgs, results in large variations of Re{Zopt}.

Since |Re{Zopt}-Re{Zin}| is a measure of simultaneous matching over the entire band, the large

variations of Re{Zopt} deteriorates the wideband noise and input matching.

Furthermore, we know that Re{Zin} approximates Re{Zopt} to satisfy the simultaneous

noise and input matching over the frequency band of interest. Therefore, large values of Re{Zopt}

also require a large Re{Zin} to meet this requirement. However, recall from (3.7) that the overall

transconductance and hence the overall gain is inversely proportional to Re{Zin}(Rin).

Consequently, a small power budget may result in a severe reduction of the power gain which is

not desirable.

Considering the foregoing discussion, we can modify the proposed wideband LNA

design technique as follows. Start the design with a limited power budget and find the

appropriate values of Vov, W, and Ls. If the circuit fails to satisfy the noise and gain requirements


over the entire bandwidth after the insertion of the matching network, return to step one, increase

the power budget and repeat the subsequent steps.

3.5 Wideband Impedance Matching Networks

As pointed out in previous sections, to achieve the maximum power transfer and minimum NF,

we need to insert a matching network before the input port of the transistor. There exist many

techniques to design the matching network for narrowband applications. Most of these

approaches rely on Smith chart as a graphical tool. Smith chart highly simplifies the complicated

calculations needed for the synthesis of the matching network. Smith chart gives an initial

solution to our problem and can be made more precise through the use of some advanced CAD

tools.

The applications of the abovementioned narrowband techniques can be extended to

broadband amplifiers through the use of the so-called nodal quality factor, Qn, technique [24].

This technique is based on the observation that the total impedance at each node of matching

network can be expressed either as an equivalent series impedance or parallel admittance.

Therefore we can assign a quality factor to each node of circuit defined as the ratio of absolute

value of reactance |Xs| to that of resistance Rs at that particular node:

sn

s

XQ

R (3.36)

or equivalently Pn

P

BQ

G (3.37)

For narrowband applications, there is an exact relation between the nodal quality factor and the

bandwidth of the matching network. However, for broadband applications where the network

configuration is usually more complicated, Qn only gives an estimation of the network


bandwidth. As a rule of thumb, the maximum value of nodal quality factor is usually considered

as the actual quality factor of the network. The three-element matching network is the simplest

network that allows us to achieve impedance matching over a wide frequency range. Two

variants of three element matching network are illustrated in Fig. 3.18.

(a) (b)

Figure 3.18 (a) π matching network (b) T matching network

Note that when we use these networks in our LNA design, Zl represents the impedance seen at

the gate of the input transistor looking into the transistor (denoted by Zin in the previous section)

and jXis and jBis are the reactances and susceptances of the matching network elements,

respectively. Since the nodal Q is considered as the quality factor of this filter, the bandwidth of

input network becomes approximately:

o

n

fBW

Q (3.38)

Therefore, for broadband applications we should use networks with very low values of Qn.

Fig.3.19 shows the contours of constant Qn in the smith chart.


Figure 3.19 Contours of constant Qn displayed in the smith chart

The details of matching network design using smith chart are provided in [24]. Here, we

introduce an alternative approach to the design of π matching network and study its broadband

nature. Consider the schematic of Fig. 3.20 (a) where a π matching network is inserted between

the source and the input of a MOS device. Fig. 3.20 (b) shows the high frequency model of the

same circuit used for matching purposes. Recall from section 3.1, that IMF is the same for

different reference planes, assuming the matching network is lossless. Therefore, we choose the

reference plane to be in the middle of the network, as shown in Fig. 3.20 (b). The impedance

looking to the left of the reference plane is given by:

2 2 2 2 21

2 2 21 1

2 2 2 2 21

(1 )

( )

(1 )

seq

p s p g

g p g seq

p s p g

RR

C R C L

L C L RL

C R C L

(3.39)


(a) (b)

Figure 3.20 (a) π matching network (b) Equivalent circuit

To satisfy the matching at this reference plane the following, conditions should hold:

e in

2 2

1( )

q t s

eq in s ggs

R R L

L L L LC

(3.40)

Req , as expressed in (3.39), is not a constant and varies with the frequency. However, there exists

a maximum for Req expression at the frequency ω1:

21

1 21

2

2g p s

p g

L C R

C L

(3.41)

In the vicinity of this maximum frequency, Req is almost constant. So, by proper choice of Lg and

Cp we can set the maximum frequency,ω1, and the maximum resistance, Req,max, in a way that Req

closely approximates Rin , i.e., ωtLs in the frequency band of interest.

On the other hand, the equivalent inductance, Leq, should also satisfy the requirement in

(3.40) to guarantee wideband matching over the entire band. Leq, as described by (3.39), has a

zero at the frequency given by:


21

2 21

g p s

p g

L C R

C L

(3.42)

Once the values Cp and Lg1 are chosen to ensure Rin=Req over the band of interest, ω2 will have a

fixed value. Now, by proper choice of Lg2, we must attempt to satisfy (3.40).

We have performed this analysis for a UWB LNA using Agilent ADS, and the following

values for the passive elements are obtained: Lg1=1.68nH, Cp=540fF, and Lg2=5nH. The graphs of

Req (Rin) and Leq(Lin) are shown in Figs 3.21 and 3.22.

Figure 3.21 Real parts of impedances Zin and Zeq over the UWB band


Figure 3.22 Imaginary parts (equivalent inductance) of impedances Zin and Zeq over the UWB band

Chapter 4 – Simulation Results and Layout Issues 70

CHAPTER 4

SIMULATION RESULTS AND LAYOUT ISSUES

To demonstrate the applications of the proposed design technique, two wideband inductively

degenerated LNAs are designed and simulated in a 0.18μm CMOS technology. In this chapter

we present the design stages of these two LNAs and the corresponding simulation results. The

layout of the second LNA has also been drawn and has been sent for fabrication. Issues related to

the layout of this LNA will be discussed in the last section.

4.1 Wideband LNA for multi-standard application in 1.5-2.5GHz

The first LNA is intended for multi-standard applications in the frequency range of 1.5-2.6GHz.

This choice of frequency band covers the bands of GPS (1.575GHz), UMTS (1.9GHz and

2.1GHz), Bluetooth (2.4-2.48GHz), and IEEE802.11b/g (2.4-2.48) standards.

In the design of this LNA, cascode architecture is used to reduce the Miller1 effect and

improve the reverse isolation (s12≈0). Also, to eliminate the need for a balun2 a single-ended

amplifier is preferred over its differential counterpart. Fig. 4.1 shows the complete schematic of

this LNA. The width (130μm) and over-drive bias of transistor M1 (220mV) are chosen to satisfy

the power budget requirement and to achieve the minimum Rn and NFmin (first step of design

technique). With this choice of parameters, the cascode core draws a small current of 6mA from

a 1.5V power supply. M1, M3 and RB1 form a current mirror to provide the bias for the input

1 For a through study of Miller effect refer to [45]2 RF balun transformers convert the single input of the antenna into a differential pair to be used by differential amplifiers


transistor. The width of M3 is chosen to be very small to minimize the power headroom of the

bias circuitry (WM3=2.2μm). The resistor RB2 is chosen very large to reduce its noise contribution

to the input of LNA [12].

To achieve the wideband noise and input matching Re{Zin} and Re{Zopt} are simulated in

Agilent ADS. Fig. 4.2 shows the results of this simulation. An appropriate choice of the

degeneration inductance (Ls=1.2nH) brings the two curves are very close two each other over the

band of interest.

Figure 4.1 Complete schematic of the multi-standard LNA


Figure 4.2 Real part matching of Rin and Ropt for multi-standard LNA

Also, a T matching network is designed to obtain the desired bandwidth. The values of passive

elements in this network are L1=8nH, C1=700fF, and L2=28nH. This T matching network is

intended to be off-chip. The output load of LNA is a shunt-peaking structure and is formed by an

inductor (Ld=3nH) in series with a resistor (Rd=40Ω). The inductive nature of this load

compensates the gain roll-off of LNA at high frequencies.

To avoid the use of an output buffer, which will result in extra power consumption and

chip area, the shunt peaking structure also provides the 50Ω matching at the output port. To

achieve this goal, an extra capacitance, Cd, is added in parallel with the gate-drain capacitance of

M2. The value of this capacitance is chosen to satisfy |Γ|<-10dB at 2.6GHz. (Cd=300fF).

Figs. 4.3 and 4.4 depict the simulated performance of this LNA. Low values of S11 (<-

10dB) in Fig. 4.3 are an indication of input matching over the entire bandwidth. Fig. 4.4 shows


both NF and NFmin on the same graph. As can be seen, NFmin is in close agreement with NF over

the bandwidth of interest and satisfies the wideband low NF requirement.

Figure 4.3 Simulated S-parameters of the multi-standard LNA

Figure 4.4 Simulated NF and NFmin of the multi-standard LNA


4.2 Wideband LNA for UWB application (3.2-5GHz)

The second LNA is designed to operate in the frequency range of 3.2-5GHz, which

covers the lower frequency band of UWB systems. The schematic of this LNA is similar to the

first LNA, except that the output matching is achieved by using a common drain amplifier. Fig.

4.5 shows the complete schematic of this LNA.

Figure 4.5 Complete schematic of the UWB LNA

The values of all elements at the input port are chosen based on the steps of the proposed design

technique. The value of the parameters are as follows: WM1=160μm, Vov,M1=230mV, Ls=720pH,

L1=1.7nH, L2=5nH, and C1=300fF. These values of input network elements facilitate the on-chip

implementation of the matching network. Shunt peaking load is used at the drain of the cascode

transistor to enhance the bandwidth of the LNA. The value of Rd (41Ω) is chosen as a

compromise between the gain at low frequencies and the linearity. The inductance Ld (4.1nH)

also compensates the current gain roll-off at high frequencies.


The output buffer is properly sized to produce the required 50Ω impedance at the output

(WM3=50μm). The inductor LL provides the DC path to the ground and is chosen large enough so

that it does not deteriorate the impedance matching at high frequencies (LL=4.5nH). The width of

the cascode transistor is somewhat arbitrary and is usually chosen as a compromise between two

competing factors of low noise and input matching [12]. For this LNA, the width of M2 is chosen

to be equal to the width of M1 to simplify the layout and to improve the high frequency

performance (refer to the layout considerations section). The entire LNA, including the buffer,

draws 10mA from a 1.5V power supply. The current usage of the core amplifier is around

7.7mA. Table 2 summarized the performance results of the two LNA.

Multi-standard LNA(external matching)

UWB LNA(post-layout)

|S21|max 13.6dB 17.7dB

NFmax (in 3dB bandwidth) 0.8 dB 3.2dB

IIP3 (worst case) -2.5 dBm -4.5dBm

1dB CP (worst case) -13.2 dBm -15dBm

Power 9.1 mW 11.6mW

-3dB Bandwidth (|S21|) 1-2.6 GHz 3.16-5.05GHz

Bandwidth (|S11|<-10dB) 1.48-2.65 GHz 3.2-6GHz

Bandwidth (|S22|<-10dB) >2.55 GHz 3-6GHz

Table 2 Summary of Performance

Layout Considerations

The circuit of this UWB LNA is laid out in a 0.18μm CMOS technology with 6 metal layers

using the Cadence Virtuoso layout tool. The careful layout of high frequency circuits is quite


necessary to minimize the noise and loss contribution of parasitic elements. For this purpose, a

large effort is made to reduce the effect of these parasitics wherever possible. Wide interconnects

and a large number of vias are used all over the chip to reduce the parasitic resistances and

improve the gain and NF.

Two cascode transistors are interdigitated with the gate fingers connected at both ends.

This will highly reduce the distributed gate resistance, Rg, and hence improve the NF. Also, the

contact windows at the common node of the two transistors are eliminated to decrease the

junction capacitance at the drain of M1 and improve the high-frequency performance [46]. Large

number of substrate contacts surrounds the cascode architecture to reduce the substrate

resistance, Rsub, and its contribution to the NF of LNA [47]. Fig. 4.6 illustrates the layout of the

interdigitated transistors M1 and M2.

Figure 4.6 Layout of cascade amplifier for the UWB LNA


The capacitors are implemented using the metal-insulator-metal (MIM) option in 0.18μm

technology with CTM and metal5 as the two plates. These capacitances possess high values of

quality factor (Q>300) and are suitable for our high frequency applications.

The inductors are all implemented as on-chip spiral inductors. To realize these inductors,

thick metal-6 layer (the top-most layer) with the lowest resistivity is employed. However, the

quality factor of these inductors is still very low and is about 5 to 10. A lumped RLC equivalent

circuit is used to model these spiral inductors [48] and is employed for simulation purposes. Fig.

4.7 shows the 9-element RLC model provided by the foundry.

Figure 4.7 9-element equivalent model of spiral inductors

This model is developed based on the S parameter fitting of the data obtained from the

measurements of stand alone inductors. The information provided by the foundry is valid up to

6GHz, which is sufficient for our UWB LNA.


Post-layout simulation results of UWB LNA

The layout of this LNA is extracted using the Diva extraction tool from Cadence. All parasitic

resistances are included in this extraction. Due to the inability of this tool to extract the inductors,

all spiral inductors are substituted with their corresponding 9- element model available from

foundry measurement. The following figures show the post-layout simulations of this LNA. As

can be seen from Fig. 4.8 the 3 dB bandwidth of S21 covers the entire band from 3.1 to 4.8GHz

and S11 and S22 are less than -10dB over the entire band. Fig. 4.9 shows the NF and NFmin on

the same graph. The rapid degradation of NF at high frequency is mainly due to the parasitics of

spiral inductors and the increase of NFmin at high frequencies.

2.5 3 3.5 4 4.5 5 5.5 6-25

-20

-15

-10

-5

0

5

10

15

20

Frequency (GHz)

dB

S21S11S22

Figure 4.8 Simulated S-parameters of the UWB LNA (post-layout)


2.5 3 3.5 4 4.5 5 5.5 62

2.5

3

3.5

4

4.5

Frequnecy (GHz)

dB

NFNF

min

Figure 4.9 Simulated NF of the UWB LNA (post-layout)

Chapter 5 – Conclusions and Future Work 80

CHAPTER 5

CONCLUSIONS AND FUTURE WORK

5.1 Conclusions

This thesis presents a wideband power constrained LNA design technique that satisfies

simultaneous noise and input matching over a wide range of frequency. Several steps are taken to

develop this new methodology. First, the existing wideband architectures are explored and their

advantages and disadvantages are briefly discussed. As the result of this overview, the L-deg

LNA is chosen as a suitable solution due to its superior performance in terms of NF and power

consumption.

Second, the wideband performance of L-deg LNA is explored from both the circuit and

the system level perspectives. It has been shown that, under power dissipation constraint, the

source degeneration inductance plays a significant role in the fulfillment of the simultaneous

noise and input matching requirement. Finally, combining all the requirements of low-power

consumption, low NF, and simultaneous noise and input matching, a step-by-step design

technique is developed. The trade-offs among different requirements and the way they may

affect the circuit parameters are also discussed in detail.

Also, two LNAs are designed and simulated using the proposed design technique. The

first LNA was intended for multi-standard application in the frequency range of (1.2-2.5GHz)

and the second LNA was aimed for the lower band of UWB applications (3-5GHz). Both LNAs

Chapter 5 – Conclusions and Future Work 81

are designed and simulated in a 0.18μm CMOS technology and exhibit high gain as well as good

NF and impedance matching, while consuming little power.

5.2 Future Work

Large signal behaviour and the linearity performance of the LNA were not priories in the

development of the proposed wideband design technique. The linearity of the broadband LNA

requires further investigation to clarify the effects of the frequency variation on the linearity of

the LNA. Also, a more careful analysis of the L-deg LNA should be carried out to reveal the

design trade-offs when high linearity is a major requirement.

As discussed in section 3.3, Rs,opt is a frequency-dependant value. However, the existing

matching networks cannot track the value of Rs,opt as the frequency varies. Therefore, the best

alternative, at present, is to design a wideband matching network that produces Rs=Rin (i.e., a

constant value) at the gate input reference plane. To surmount this shortcoming, one promising

area of research is to study the different matching networks in more detail, and find ways to

facilitate broadband matching to variable impedances. This will result in a more flexible LNA

design that can be optimized for frequency-variant gain and NF requirements.

Finally, developing software and CAD tools to automatically design a broadband LNA

based on the proposed design technique is of great importance. This will highly simplify the

design of integrated RF and mixed-signal circuits and systems.

References 82

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Appendix A – Linear Two-port Network Noise Analysis 86

APPENDIX A LINEAR TWO-PORT NETWORK NOISE ANALYSIS

In this Appendix, we present the theory of linear two port network noise analysis. The formulae

obtained in this section are widely used throughout the thesis.

Consider the noisy two port network shown in Fig. A.1a

Noisy two-portnetwork

+

-

+

-

I1 I2

V1 V2Noise free two-port

networki2n1i2n2

V1

+

-

V2

+

-

I1 I2

(a) (b)

Figure A.1 (a) block diagram of noisy two-port network (b) Equivalent network with

input and output noise current sources

The total noise in the network can be represented by two independent noise sources at the input

and outputs of the network. So, in admittance matrix representation we can write:

1 11 12 1 1

2 21 22 2 2

n

n

I Y Y V i

I Y Y V i

(A.1)

Rearranging the parameters, we can convert the admittance representation to the inverse hybrid

representation:

1 11 12 2

1 21 22 2

n

n

V H H V i

I H H I e

(A.2)

where all the noise sources are transformed to the input of network and are represented by

voltage and current noise sources, Vn and In:

221

1n ne i

Y and 11

1 221

n n n

Yi i i

Y (A.3)


Using this simplification we arrive at the network model shown in Fig A.2, where the noisy

admittance, Ys, and the corresponding parallel current noise are connected to the input of the

network.

Figure A.2 Input Referred equivalent noise model

The definition of NF is given by:

total input referred noise powerNF

input referred noise power due to source (A.4)

Assuming that the two-port network and the source noise are uncorrelated, then the following

expression for the NF of the network can be written:

22

2

s n s n

s

i i Y eNF

i

(A.5)

Note that (A.5) does not assume that the internal noise sources in and en are uncorrelated. To

include this correlation, in can be expressed as the sum of two components:

n u ci i i (A.6)

where iu is uncorrelated with en and ic is the correlated with en. Since ic is fully correlated with en,

we can introduce a correlation admittance Yc, which relates the two components:

c c ni Y e (A.7)


Now, the NF expression in (A.5) can be simplified as follows:

2 22 2

2 2

( ) ( )1

s u s c n u c s n

s s

i i Y Y e i Y Y eNF

i i

(A.8)

Each of the noise sources iu, is, and en can be represented by an equivalent resistance or

conductance that generates the same noise:

2

4n

n

eR

kT f

(A.9)

2

4u

u

iG

kT f

(A.10)

2

4s

s

iG

kT f

(A.11)

Therefore, (A.8) can be rewritten as:

2

2 2

1

[( ) ( ) ]1

u c s n

s

u c s c s n

s

G Y Y RNF

G

G G G B B R

G

(A.12)

This last expression explicitly shows the dependence of NF on the conductance and susceptance

of source, i.e. Gs and Bs. Hence, one can optimize NF by properly choosing these values. Taking

the first derivative of (A.12) with respect to Gs and Bs, we can find the optimum value of the

source admittance and that of NFmin:

2, ,

us opt c s opt c

n

GG G B B

R (A.13)

2min 1 2 u

n c cn

GNF R G G

R

(A.14)


It is also possible to express NF in terms of NFmin and the optimum impedance:

2 2min [( ) ( ) ]n

s opt s opts

RNF NF G G B B

G (A.15)

The contours of constant NF in the Smith chart are circles that have their centres located along a

line drawn from the origin to Yopt.

Appendix B – Classic MOS Device Noise Analysis 90

APPENDIX B CLASSIC MOS DEVICE NOISE ANALYSIS

In this appendix we apply the formulae obtained in Appendix A to a MOS device to find

analytical expressions for Gopt, Bopt and NFmin in terms device parameters.

Recall from chapter 2 that dominant sources of noise in a MOS device are the channel

thermal noise, i2nd, and the gate induced current noise, i2

ng with the power spectral densities given

by:

204nd di kT g f (B.1)

2 4ng gi kT g f (B.2)

where i2ng can be rewritten as the sum of two term, one correlated with i2

nd and one totally

uncorrelated:

2 22 2 2 4 (1 ) 4ng ngu ngc g gi i i kT g f c kT g f c (B.3)

where i2ngu is the uncorrelated portion, i2

ngc is the correlated portion, and c is the correlation factor

and is defined in chapter 2.

In order to relate NF to the noise parameters of MOS device, we should find the internal

noise sources en and in in terms of i2nd and i2ng. To do this, consider the MOS noise model in Fig.

A.1a and its equivalent input-referred model in FigA.2

(a) (b)

Figure B.1 (a) Noise sources of a MOS device b) Equivalent input referred model


Equating the input-referred noise in the two figures yields the following expressions for en and in:

22 0

2 2

4nd dn

m m

i kT f ge

g g

(B.4)

2

2 ( )nd gsn ng

m

i j Ci i

g

(B.5)

To calculate Gopt and Bopt, we need to find Yc given by the expression ic=Ycen., see (A.7). A

simple way to find Yc is to re-express (A.7) in the following way:

*

2

n nc

n

i eY

e (B.6)

After substituting (B.4) and (B.5) in (B.6), and after some simple algebraic manipulation we

obtain:

2

*ng ndc gs m

nd

i iY j C g

i (B.7)

Multiplying both the numerator and denominator by (i2ng)

1/2 and recalling the definition of

correlation factor from (2.6) yields:

2

2

ngc gs m

nd

iY j C g c

i (B.8)

Substituting the expressions for i2nd and i2

nd from (B.1) and (B.2) we find that:

2 2

20

(1 )5 5

gsc gs m gs

d

CY j C g c j C c

g

(B.9)

where the last equality is written on the assumption that the correlation factor is a purely

imaginary number, i.e. c=-j|c|.

Based on these calculations we can now find the expressions for noise conductances and

resistance in terms of MOS noise parameters:


20

24 .n d

nm m

geR

kT f g g

(B.10)

2 22 22 2

0

4 (1 ) (1 )

4 4 4 5u ngu g gs

ud

kT f g c C ci iG

kT f kT f kT f g

(B.11)

Therefore we obtain:

, (1 )5s opt c gsB B C c

(B.12)

22, (1 )

5u

s opt c gsn

GG G C c

R

(B.13)

2 2min

21 2 [ ] 1 (1 | | )

5u

n c cn t

GNF R G G c

R

(B.14)

and also for Zopt we have

2

222

(1 )(1 )

5 51

(1 )(1 )

5 5

optopt

gs

cj c

ZY c

C c

(B.15)

The calculations for inductively degenerated LNA can be performed in the same way. The

details of these calculations are provided in [38].