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7/31/2019 N THI H THNG NHNG (QUANG)

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N THI H THNG NHNG

1.

Typical Small Microcontroller (Vi iu khin in hnh)

Hnh 1: Essential components of a microcontroller.

(Cu trc ch yu ca 1 vi iu khin)

Central processing unit (CPU)

Arithmetic logic unit (ALU) thc hin chc nng tnh ton.

Cc thanh ghi cn thit cho hot ng c bn ca CPU, chng hn nh ccprogram counter (PC), stack pointer (SP), v status register (SR).

Hn na thanh ghi cha kt qu tm thi.

Lnh gii m v logic khc kim sot CPU, x l reset, interrupt, v.v....

Memory for the program:bt bin (b nh ch c, ROM), ngha l n lu gi ni

dung b nh khi mt in.

Memory for data: c bit n nh l b nh truy cp ngu nhin (RAM) v thngd kh bin (thay i).

Input and output ports: cung cp thng tin lin lc k thut s vi th gii bn ngoi.

Address and data buses: lin kt cc h thng con truyn d liu v cc lnh.

Clock: gi cho ton b h thng c ng b.


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* Sau y l vi thit b ngoi vi ph bin hn:

Timer: hu ht cc vi iu khin c t nht mt timer v phm vi rng ca hm mchng cung cp.

Watchdog timer: l mt tnh nng an ton, reset b vi x l nu chng trnh b mckt trong mt vng lp v hn.

Communication interfaces: mt s la chn rng ca giao din c sn trao ithng tin vi mt vi mch hoc h thng.

Nonvolatile memory for data: c s dng lu tr d liu c gi tr phi clu gi khi tt ngun.

Analog-to-digital converter: rt ph bin bi v s lng qu nhiu trong th giithc thay i lin tc.

Digital-to-analog converter: t ph bin hn, bi v hu ht cc output tng t c thc m phng bng cch s dng PWM.

Real-time clock: cn thit trong cc ng dng phi theo di thi gian trong ngy.

Monitor, background debugger, and embedded emulator: c s dng tichng trnh vo MCU.

2. S khi tng th ca chp TI MSP430G2231


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3. B nh: Cch nh a ch. Phn b v tr b nh

Mi thanh ghi hoc nh cha 8 bit hoc 1 byte v y l thc th nh nht c thc chuyn t b nh

Memory address bus di 16 bit: t 0x0000 n 0xFFFF

Memory data bus di 16 bit v c th truyn 1 word 16 bit hoc 1 byte 8 bit

a) Cch nh a ch:

Hnh 3: Ordering of bits, bytes, and words in memory, adapted from the MSP430x2xxFamily Users Guide. Addresses increase up the page.

(Th t ca cc bit, byte, v word trong b nh, chuyn th t hng dn ca ngidng dng MSP430x2xx. a ch tng ln cc trang.)

Little-endian ordering: byte th t thp c lu tr ti a ch thp v byte th tcao a ch cao hn. c s dng bi MSP430 v l nh dng ph bin hn.

Big-endian ordering:byte th t cao c lu tr ti a ch thp hn. c s dngbi Freescale HCS08


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b) Phn b v tr b nh:

Hnh 4: Memory map of the MSP430F2013, based on the data sheet and theMSP430x2xx Family Users Guide. Addresses increase up the page and are not drawnto scale. Gray regions are unused and their size varies considerably between devices.The F2013 does not have a bootstrap loader but I have shown its location because it is

present in most variants of the MSP430.

(Bn b nh ca MSP430F2013, da trn cc bng d liu v hng dn cangi dung dng MSP430x2xx. a ch tng ln v khng c rt ra vi quy m.Vng mu xm l khng s dng v kch thc ca chng khc nhau ng k gia

cc thit b. F2013 khng c mt trnh np bootstrap nhng ti cho thy v tr can bi v n l hin din trong hu ht cc bin th ca MSP430)


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Special function registers: ch yu l lin quan n vic cho php cc hm ca mt sm-un v cho php v tn hiu ngt t thit b ngoi vi.

Peripheral registers with byte access and peripheral registers with word access:cung cp cc thng tin lin lc chnh, gia CPU v cc thit b ngoi vi. Mt s phi

c truy cp nh word v byte

Random access memory: c s dng cho cc bin. Lun lun bt u ti a ch0x0200 v gii hn trn ph thuc vo kch thc ca b nh RAM. F2013 c 128 B.

Bootstrap loader: c cha mt chng trnh giao tip bng cch s dng mt giaothc chun ni tip, thng xuyn vi cc cng COM ca PC.

Information memory: mt khi 256B ca flash memory c dnh cho vic lu trd liu bt bin. C th bao gm cc s serial nhn dng thit b - mt a ch mng

chng hn - hoc cc bin cn c lu gi ngay c khi mt in. DCO thuc dngMSP430F2xx v c bo v theo mc nh.

Code memory: gi chng trnh, bao gm cc m thc thi ca chnh n v bt k dliu hng no. F2013 c 2KB nhng F2003 ch c 1KB.

Interrupt and reset vectors: c s dng x l "ngoi l", khi hot ng bnhthng ca b x l ngt hoc khi thit b c reset. Bng ny nh hn v bt u ti0xFFE0 trong cc thit b trc .

4. Cu to CPU v ngha cc thanh ghi trong CPU

The central Processing Unit (CPU) thc hin cc lnh c lu tr trong b nh. Nbc thng qua cc lnh trong trnh t m chng c lu tr trong b nh cho n khin gp mt nhnh hoc khi xy ra trng hp ngoi l (interrupt hoc reset).

N bao gm cc arithmetic logic unit (ALU), thc hin tnh ton, mt tp hp ca 16thanh ghi R0-R15 v logic cn thit gii m cc lnh v thc hin chng.

CPU c th chy tn s xung nhp (clock) ti a fMCLK 16MHz


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Hnh 5: Thanh ghi trong CPU ca MSP430

Program counter, PC: cha cc a ch ca lnh tip theo c thc hin, tr tilnh trong thut ng thng thng.

Stack pointer, SP: khi mt chng trnh con c gi, CPU nhy n chng trnhcon, thc thi code, sau tr v cc lnh sau khi gi.

Status register, SR: cha mt tp hp cc c (bit n), c chc nng chia lm ba loi.

Cc c c s dng ph bin nht l C, Z, N v V, cung cp thng tin v kt qu cas hc cui cng hoc hot ng hp l.

Constant generator: cung cp 6 gi tr c s dng thng xuyn nht chngkhng cn phi c ly t b nh bt c khi no chng cn.

General purpose registers: 12 thanh ghi cn li, R4-R15, l nhng thanh ghi lm vicchung. Chng c th c s dng cho d liu hoc a ch bi v c hai u c gi tr16-bit, m n gin ho cc hot ng ng k.

5. Cc loi xung nhp (clock) v cc ch hot ng

Xung nhp (clock) cn thit cho mi h thng ng b k thut s.

Thng thng, mt tinh th vi mt tn s ca mt vi MHz s c kt ni vi haichn. N s chy CPU trc tip v thng c chia bi mt nhn t ca 2 hoc 4main bus.

ng tic l, nhu cu xung t cho hiu sut cao v cng sut thp c ngha l hu htcc vi iu khin hin i c xung nhp phc tp hn nhiu, thng c hai hay nhiungun.


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Trong nhiu ng dng MCU dnh hu ht thi gian ca n trong mt ch cng sutthp cho n khi mt s s kin xy ra, khi n phi hot ng li v x l cc s kinnhanh chng.

Master clock, MCLK, c s dng bi CPU v mt vi thit b ngoivi.

Subsystem master clock, SMCLK, c phn phi cho cc thit bngoi vi.

Auxiliary clock, ACLK, cng c phn phi cho cc thit b ngoi vi.

ACLK n t mt b dao ng tinh th tn s thp, in hnh l ti 32KHz.

MCLK v SMCLK c cung cp t cc DCO, c iu khin bi 1requency-locked loop (FLL). Kha tn s ny tn s gp 32 ln ACLK,gn n 1MHz cho watch crystal thng thng.

6. Hm v cc bc thc hin khi gi mt hm (b)

7. Khi nim ngt v chng trnh phc v ngt

a) Khi nim ngt:

Interrupts: thng c to ra bi phn cng (mc d chng c th c khi tobng phn mm) v thng ch ra rng mt s kin xy ra m cn mt phn ngkhn cp. Mt gi d liu c th c nhn, chng hn, v cn c x l trc khicc gi tin tip theo n. B vi x l dng li nhng g n lm, lu tr y thngtin (ni dung ca b m chng trnh v thanh ghi trng thi) cho n tip tc sauny v thc hin mt interrupt service routine (ISR). N tr v hot ng trc khiISR c hon thnh. Do ISR l mt ci g ging nh mt chng trnh conc gi l phn cng (ti mt thi im khng th on trc) ch khng phi l

phn mm.

Resets: thng c to ra bi phn cng, hoc khi bt ngun hoc khi mt ci g thm hi xy ra v khng th tip tc hot ng bnh thng. iu ny tnh tnh cc th xy ra nu watchdog timer khng b v hiu ha, m d dng qun. Reset lmcho thit b restart li t mt trng thi xc nh.

Ngt c s dng ph bin cho mt lot cc ng dng:

S kin khn cp phi c thc hin kp thi mc u tin cao hn so vimain code. Tuy nhin, n thm ch cn nhanh hn thc hin mt s kin trc

tip bi phn cng nu c th


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S kin t xy ra, chng hn nh x l u vo chm t ngi dng. Gip titkim chi ph kim sot vng thng xuyn.

nh thc CPU ng.

Gi n mt h iu hnh.

b) Cc chng trnh phc v ngt:

* Interrupts Service Routine

Cc code x l mt ngt c gi l mt trnh x l ngt hoc interrupt serviceroutine (ISR).

C v b ngoi ging nh mt hm nhng c mt vi sa i quan trng.

Cc tnh nng m interrupts pht sinh vo nhng thi im khng th ontrc c c ngha l mt ISR phi thc hin hnh ng ca n v dn dptrit main code c th c tip tc m khng c li n khng th cho bitrng mt ngt xy ra.

* Interrupt Flags

Mi ngt c mt c, m c bt (t) khi iu kin cho ngt xy ra. V d, Timer_Athit lp c TAIFG trong thanh ghi TACTL khi b m TAR tr v 0.

Hu ht cc interrupts l c th che giu, c ngha l chng c hiu qu ch khi general

interrupt enable (GIE) bit c bt trong status register (SR). Chng b pht l nu GIEtt.

* Interrupt vector

MSP430 s dng interrupts vectored, ngha l a ch ca mi ISR vector c lutr trong mt vector table ti mt a ch xc nh trong b nh.

Mi interrupt vector c quyn u tin khc nhau, c s dng la chn m vectorc thc hin nu c nhiu hn mt interrupt hot ng khi vector c np. Cc u

tin c c nh trong phn cng v khng th thay i bi ngi dng.

8. Cc bc thc thi khi thc hin mt ngt

B1: Nu CPU ang hot ng th phi hon tt cng vic lm d, nu CPU tt phi btMCLK.

B2: Lnh tip theo c a vo stack.

B3: a SR vo stack.

B4: La chn u tin ca interrupt khi c nhiu interrupt.


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B5: T ng xa cc c.

B6: Xa SR phc v chng trnh mi.

B7: a interrupt vo PC v CPU thc hin cc lnh nhng cc a ch

9. Cc ch cng sut thp

Active mode: CPU, tt c cc xung nhp, v cc m-un cho php hot ng, I 300Ua. MSP430 khi ng trong ch ny, phi c s dng khi CPU c yucu. Interrupt t ng chuyn cc thit b active mode. Hin ti c th c gim bngcch chy MSP430 in p cung cp thp nht ph hp vi cc tn s MCLK, VCCc th c h xung 1.8V cho Fdco = 1MHz, cho I 200Ua.

LPM0: CPU v MCLK b v hiu ha, SMCLK v ACLK vn cn hot ng, I 85Ua. c s dng khi CPU khng c yu cu, nhng mt s m-un yu cu mtxung nhp nhanh nh SMCLK v DCO.

LPM3: CPU, MCLK, SMCLK, v DCO b v hiu ha; ch c ACLK vn cn hotng, I 1Ua. y l ch tiu chun cng sut thp khi cc thit b phi khi tochnh n chu k bnh thng v do cn c mt xung nhp (chm). N cng cyu cu nu MSP430 phi duy tr mt xung nhp thi gian thc. Hin ti c th cgim xung cn khong 0.5uAby s dng VLO thay v bn ngoi ca tinh th trongMSP430F2xx nu Faclk khng cn chnh xc.

LPM4: CPU v tt c xung nhp b v hiu ha, I 0.1Ua. Thit b ny c th ckhi to ch bi mt tn hiu bn ngoi. Cng c gi l RAM duy tr ch .

10. Cc cng nhp xut s (Digital Input and Output)

Cu ny kh hiu qu nn mnh ko dch, ai dch share mnh vi

11. Qut ma trn bn phm. Chng di

Nhiu sn phm yu cu s u vo v cung cp mt bn phm cho ngi dng.

Chng thng c 12 phm nh in thoi hoc nhiu hn. Mt kt ni ring l cho miswitch s s dng s chn qu cao, do chng thng c sp xp nh mt ma trn.


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Hnh 6: Connection of a 12-button telephone keypad as a 3x4 matrix

(Kt ni ca mt bn phm in thoi 12 nt nh l mt ma trn 3x4)

* Cc bc qut ma trn:

B1: a X1 thp v cc ct X2 v X3 cao. iu ny lm cho cc switch trong ct X1 hotng v tng ng vi u vo Y xung thp nu mt nt c nhn. V vy, chng ta cth pht hin trng thi ca switch 1, 4, 7 hoc *. Cc switch trong cc ct khc khng chiu lc bi v thit b u cui ca chng ti VCC.

B2: a X2 thp v cc ct khc cao c cc switch trong ct X2.

B3: Lp li cho ct X3.12. Cc loi LCD

Mt Liquid Crystal Display (LCD) s dng in nng t hn nhiu so vi n LED.

Mn hnh LCD gm ba loi:

Segmented LCDs: n gin v c th c iu khin trc tip bi dngMSP430x4xx. Nhng mn hnh ny gm c 7 on hin th s quen thuc ctm thy trong ng h v nhiu ng dng khc. (ng h in t - ch hin th

s)


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Character-based LCDs: c mt mn hnh ma trn im, thng c 1-4 hng 8-72 k t. Chng thng c th hin th mt tp hp ca khong 256 k t ly rat cc k t ASCII, phm mi tn, v la chn cc biu tng khc (hin thc ch ABC..)

Fully graphical LCDs: c tm thy trn mi in thoi di ng (hin thhnh nh)

13. Cc loi timer

Watchdog timer:bao gm tt c cc thit b. Chc nng chnh ca n l bo v hthng chng trc trc, nhng thay v n c th c s dng nh mt khong timer nus bo v ny khng cn thit.

Timer_A: cung cp trong tt c cc thit b. N thng c ba knh v nhiu hn na,

linh hot hn so vi cc timer n gin ch lit k. Timer_A c th x l bn ngoi uvo v u ra trc tip o tn s, u vo time-stamp, v kt qu u ra a ti thiim xc nh r, hoc mt ln hoc nh k.

Timer_B:bao gm trong cc thit b ln hn tt c cc dng. N tng t nhTimer_A vi mt s phn m rng lm cho n ph hp hn cho u ra a chng hnnh iu bin rng xung.

14. Cu trc v cc ch hot ng ca TimerA0

Hnh 7: Simplified block diagram of Timer_A showing the timer block andcapture/compare chanel 1. The circles show external signals that may be brought out to

pins of the device


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(S khi n gin ca Timer_A hin th timer block v capture/compare chanel 1. Ccvng trn hin th tn hiu bn ngoi m c th c a ra khi chn ca thit b)

y l timer h iu hnh a nng linh hot nht trong MSP430 v bao gm tt c ccthit b.

Timer block: ct li, da trn thanh ghi 16 bit TAR. C s la chn ngun cho xungnhp, c tn s c th c chia xung (prescaled). Timer block khng c output,nhng mt c TAIFG c bt ln khi counter tr v 0.

Capture/compare channels: trong hu ht cc s kin xy ra, da trn thanh ghiTACCRn. Tt c cc cng vic theo cch ging vi ngoi l quan trng ca TACCR0.

Capture (nm bt) mt input, ngha l ghi "thi gian" (gi tr trong TAR) m ti nhng thay i input trong TACCRn, input c th hoc external (bn ngoi) hoc

internal (bn trong) mt thit b ngoi vi hoc phn mm. Compare (so snh) gi tr hin ti ca TAR vi gi tr c lu tr trong TACCRn v

cp nht output khi chng ph hp; output c th li l hoc external (bn ngoi) hocinternal (bn trong).

Request an interrupt (yu cu mt ngt) bng cch thit lp c TACCRn CCIFG trncc s kin ny, iu ny c th c thc hin ngay c khi khng c tn hiu output.

Sample (ly mu) mt output ti mt s kin so snh, cc tnh nng c bit ny cbit hu ch nu Timer_A c s dng cho thng tin serial trong mt thit b thiu

giao din chuyn dng.

*Ghi ch: Phn di ny mnh ko bit c cn phi hc ko nhng mnh c dch ra,cc bn c ri cho kin nha

Timer Block (TASSELx bits)

SMCLK l internal (ni b) v thng nhanh chng (MHz).

ACLK l ni b v thng chm, in hnh l 32 KHz t 1 watch crystal,nhng c th c thc hin t VLO trong dng MSP430F2xx.

TACLK l external (bn ngoi).

INCLK cng l bn ngoi, i khi mt chn ring bit, nhng thng n ckt ni thng qua mt bin tn chn cho TACLK INCLK = TACLK.


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* 4 ch counter:

Stop (MC = 0): timer phi dng li. Tt c cc thanh ghi, bao gm c TAR, gi li gitr ca chng timer c th c khi ng li sau n li tt.

Continuous (2): counter t do chy qua phm vi full ca n t 0x0000 n 0xFFFF, tiim n trn v quay li v 0.

Up (1): counter m t 0 n gi tr trong TACCR0, thanh ghi capture/compare choknh 0. N tr v 0 chuyn i xung nhp tip theo.

Up/Down (3): counter m t 0 ln TACCR0, sau li xung 0 v lp i lp li.

* Capture/Compare Channels :

Timer_A c ba knh hu ht cc MSP430 mc d knh 0 s b mt nhiu ng dngbi v thanh ghi TACCR0 ca n l cn thit thit lp cc gii hn m v ch up/down, nh chng ta va thy.

Mi knh c iu khin bi mt thanh ghi TACCTLn.

Cc tnh nng trung tm ca mi knh l thanh ghi capture/compare TACCRn.


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* Interrupts from Timer_A :

TACCR0 c u tin v c interrupt vector, TIMERA0_VECTOR. u tin cao hnso vi cc vector khc, TIMERA1_VECTOR, c chia s bi capture/comparechannels v timer block cn li.

MSP430 cung cp mt thanh ghi interrupt vector TAIV xc nh ngun gc cainterrupt nhanh chng

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