ScanBurst™

ScanBurst is an innovative new at-speed DFT (Design-for-Test) tool from LogicVision, designed specifically to overcome the limitations of traditional at-speed DFT techniques. ScanBurst complements Mentor’s TestKompress® and FastScan™ ATPG products by providing an environmentto allow for easy insertion of scan and clock control structuresfor accurate at-speed testing, based on LogicVision’s patented BurstMode Timing™ technology. A fully automated and integrated analysis, insertion and test generation flow ensures low impact to the design schedule, while full and tight integration to all major 3rd party physical designflows ensures no impact to design performance.

OVERVIEW BENEFITS

• Reduced Field Returns: › Accurate at-speed testing › Signal integrity screening

• Reduced Test Costs: › Shorter test times › Minimal tester hardware requirements

• Shortened Time-To-Market: › Hierarchical test pattern generation › Immediate bring-up due to timing robustness

• Lower Power Testing: › Hierarchical test pattern application

CAPABILITIES

• Patented BurstMode Timing architecture for true at-speed test application and power control

• Comprehensive RTL automation flow for fast test integration › Automatically integrates TestKompress EDT logic › Automatically creates procedure files and control scripts for TestKompress and FastScan pattern generation

• IEEE 1500 compliant distributed test access architecture and patented core SharedIsolation for hierarchical test generation and application

Figure 1. Hierarchical Scan Test Infrastructure

"BurstMode Timing is proven technologythat has been in production use at leading semiconductor companies."

ScanBurst™

ScanBurst, together with Mentor’s world-class automatic test pattern generation (ATPG) products, TestKompress and FastScan, provides a fully integrated solution for the highly accurate and efficient at-speed testing of today's nanometerSoC designs.

The traditional approach of testing for performance related defects with ATPG-based solutions has been to generate patterns that target transition delay faults. These patterns are applied using two at-speed functional clock cycles to create a “launch” and “capture” sequence. This approach is often referred to as “broadside” or “double-capture” timing. This technique, however, often lacks accuracy, resulting in test escapes or yield loss. In particular it suffers from what is referred to as “clock stretching.” This phenomenon is caused by the instantaneous drain on power rails during the launch and capture cycles that results in an increase of the clock period, an overly optimistic performance rating of the device, and reduced delay fault detection.

ScanBurst is designed specifically to complement existing ATPG-based DFT techniques by providing an environment to easily insert scan and clock control structures for at-speed testing based on LogicVision’s patented BurstMode Timing technology.

BurstMode Timing, illustrated in figure 2, provides the ability to achieve accurate at-speed test under conditions that reflect the functional mode of operation. During the burst phase, all functional clocks are enabled to produce a burst of clock cycles. The burst is long enough to make sure that the supply has time to stabilize before the launch and capture cycles. For each clock domain, the clock burst is configurable at runtime to mimic the functional mode of operation from a timing and power point of view. This is essential to catch subtle problems related to crosstalk or IR drop, for example. The alignment of synchronous clock domains is preserved.

BurstMode Timing is a proven technology that has been in production use at leading semiconductor companies as part of LogicVision’s ETLogic™ BIST solution.

SOLUTION DESCRIPTION

Figure 2. BurstMode Timing

ProgrammableClock Bursts

1 2 3 4 5

Shift Phase

Burst Phase

Clock

Scan Enable

1 2 3 4 5

21 3 4 5

1 2 3 4 5

ScanBurst™

ScanBurst supports a hierarchical architecture (see figure 1) to scale with design size, speed and power. A key component of this architecture is the ability to efficiently isolate each core during test application.

The core level diagram in Figure 3 illustrates the patented core isolation technique that uses a combination of existing functional flops (Shared Isolation flops) and some additional flops (Dedicated Isolation flops) to separate the design into independent core components, with minimal area overhead and no impact on performance. Existing functional flops at or near the periphery of the core are used whenever possible to serve as isolation points. Control logic is added to ensure that these flops do not capture data from outside the core during scan testing. Additional flops are sometimes needed to isolate core pins that are not in close proximity to a functional flop. The identification of Shared Isolation flop candidates as well as the insertion of all necessary isolation logic is performed automatically. With this isolation architecture, test pattern generation can be targeted to only the logic within the core, without any need to consider any periphery logic or effects.

A “shell” model is also created for each core that contains any core logic that resides beyond the isolation flops. The shell models are used to create a highly

reduced top level model of the chip so that test patterns can be efficiently generated for any remaining inter-core logic. All of the FastScan or TestKompress procedure files and execution scripts are automatically generated for each core as well as the top level, fully streamlining the test generation process.

There are several advantages to the automated hierarchical test generation flow provided by ScanBurst. Test pattern generation times are reduced as individual cores in isolation need only be considered by FastScan or TestKompress. Furthermore, if two or more instances of the same core exist within the design, then patterns do not have to be regenerated for each instance. This not only saves test generation time but also results in a significant reduction in test pattern volume, as the same core test pattern set can be reused for each instance.

A hierarchical test flow is also crucial in managing low power designs. Average power consumption during scan testing tends to be much higher than during functional operation. A key reason for this is that the typically large amount of clock gating used to conserve power must be disabled for the scan operation to work. In order to remain within an overall power budget, scan testing must be applied sequentially to each individual core or subset of cores.

Hierarchical Scan Test

Figure 3. Core Isolation Support

Dedicated Isolationflop for highfanout inputs

Shared Isolationflop

Core

SI

SO

WTAP

LogicTest

ABOUT LOGICVISION

LogicVision, Inc. (NASDAQ: LGVN), provides unique test and yield learning solutions in the design for manufacturing space. These capabilities enable its customers, leading semiconductor companies, to more quickly and efficiently learn to improve product yields. The company’s advanced Design for Test (DFT) product line, ETCreateTM, works together with ETAccessTM and Yield Insight yield learning applications to improve profit margins by reducing device field returns, reducing test costs, and accelerating both time to market and time to yield. LogicVision solutions are used in the development of semiconductor ICs for products ranging from digital consumer goodsto wireless communications devices and satellite systems. LogicVision was founded in 1992 and is headquarteredin San Jose, California. For more information visit www.logicvision.com.

ABOUT MENTOR GRAPHICSMentor Graphics® is a technology leader in electronic design automation (EDA), providing software and hardware design solutions that enable companies to develop better electronic products faster and more cost-effectively. The company offers innovative products and solutions that help engineers overcome the design challenges they face in the increasingly complex worlds of board and chip design. Mentor Graphics has the broadest industry portfolio of best-in-class products and is the only EDA company with an embedded software solution. For more information visit www.mentor.com.

The hierarchical BurstMode scan infrastructure is added to a design using LogicVision’s advanced LV2005™ automation flow (see figure 4). This fully hierarchical flow ensures limited impact to the design schedule and quick turn-around time. All design analysis and IP generation and integration can be performed at either the RTL or gate levels. The integrated IP includes both the BurstMode logic as well as optionally the TestKompress Embedded Deterministic Test (EDT) logic.

Scan chain stitching and optimization is performed post synthesis. This step is tightly integrated to all major 3rd party physical design flows, including RTL-to-GDSII flows, and has no impact on design performance.

Once the scan infrastructure is integrated, all necessary input files and invocation scripts for either FastScanor TestKompress are automatically created. These files can be used at any time to invoke the desired toolto generate all necessary manufacturing test patterns.

ScanBurst™

LogicVision, Inc.Corporate Headquarters25 Metro Drive, Third FloorSan Jose, CA 95110USATel: 408.453.0146www.logicvision.com

Mentor GraphicsCorporate Headquarters8005 SW Boeckman RoadWilsonfille, OR 97070USATel: 800.592.2210www.mentor.com

Integrated Automation flow

Figure 4. Integrated DFT and ATPG Flow

Rule Checking

Generation & Assembly

Verification

FunctionalRTL or gates

FunctionalRTL or gates

with ET

TestKompress®EDT Logic Generation

PhysicalSynthesis &

Optimization

FastScanTM orTestKompress®

Final Netlistwith ET

MFGTest Patterns

Scan Insertion

ScanBurstTM

Proc

Run Script