Slide No. 1Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

Design Procedure for Two-Stage CMOS Operational Amplifier using 0.35 um

CMOS Technology

Advisor : Cheng-Ta Chiang., Ph. DReporter: Asih Setiarini

Slide No. 2Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

Outline• Introduction• Design Plan• Simulation Result• Conclusion • Q&A

Slide No. 3Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

Introduction The advantages of two-stage operational amplifier : simple

structure and robustness

The parameters must be taken into consideration to design OP:

GBW, SR,CMR, OSR, offset, and for negative feedback

connection-frequency compensation is necessary.

Simple technique of FC is connecting Cc

Cc is important factor for determining the noise and power

consumption

Aim of this work make the size of Cc much smaller

Slide No. 4Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

Design PlanOP AMP Specification

Min Max unitVoltage 0 3 VCL 10 pFAo 80 dBUnity gain frequency (fu) 10 MHzPhase Margin 60 0degreeSlew rate 10 V/usVCMR 0.2 2 VVswing 0.5 2.5 V

Process Parameter TSMC 0.35 um CMOSup 0.0112 m2/(V·s)un 0.0414 m2/(V·s)upCox 53.03 uA/V2

unCox 213.8 uA/V2

|Vtp| 0.747 VVtn 0.565 V

Slide No. 5Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

Design Plan

Slide No. 6Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

Design PlanThe calculations of the design plan were realized in an Excel- Sheet, providing very fast easier for recalculating.

Slide No. 7Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

SimulationVariable of transistor for simulation

M = W/L

Slide No. 8Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

SimulationAc Gain, PM, BW

SR, Settling time

Slide No. 9Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

Simulation ResultThe comparison between basic two stage CMOS opamp and the two-stage CMOS operational amplifiers employing Miller capacitor in conjunction with the common-gate two stage Opamp

Basic 2-stage OP, Cc = 2pF, Cl = 10pF

PM = 180 – 128.9 = 51.10

By adjust the CL value, this 2-stage OP can obtain the phase margin as the specification at CL = 5 pF.PM = 180 – 118.6 = 61.40

Gain = 78.62 dB

fu = 4.158 MHz

Slide No. 10Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

PM = 180 – 106.6 = 75.40

Simulation Result

By mounting the CG in conjunction of Miller

Capacitance no effect on AC gain value, even increase the PM and unity gain frequency

Gain = 78.62 dB

fu = 5.111 MHz

Slide No. 11Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

• Based on the aim of this work, to design compensation capacitor (Cc) much smaller with PM at least 600. Choose Cc = 1.1 pF with CL = 5 pF.

PM = 180-117.5 = 62.50

Gain = 78.62 dB

Simulation Result

fu = 8.565 MHz

Slide No. 12Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

SR (+) = 9.38 V/us

Simulation Result

SLEW RATE (+)

Slew rate is the maximum rate of change of output voltage per unit time. (dVo/dt) The slope of the output signal is the slew rate.

Slide No. 13Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

SR (-) =-6.61V/us

SLEW RATE (-)

Simulation Result

Slide No. 14Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

Common Mode Rejection ratio is the ratio between differential gain and common mode gain.

CMRR = 78.0 dB at low frequency range

CMRR

Simulation Result

Slide No. 15Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

Offset = 1.50081 – 1.5=0.0081 = 8.1 mV

OFFSET

Simulation Result

Slide No. 16Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

ICMR

ICMR=0 - 1.979 V

Simulation Result

Slide No. 17Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

OSR

OSR (-) = 80.61 mVOSR (+) = 2.903 V

Simulation Result

Slide No. 18Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

Settling Time

The time required by the output to go from

10% to 90% of its final value is called the rise time.

Settling tine =307.3 ns

Simulation Result

Slide No. 19Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

PSRR

Simulation Result

Slide No. 20Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

Simulation ResultDesign Procedure Expected Result Simulation result

(Cc=1.1pF, CL = 5pF)

Av (dB) 80 78.62

Fu (MHz) 10 8.565

Phase Margin (deg) 60 62.5

SR (V/us) 10/-10 9.38/-6.61

CMR (V) 0.2/2 0/1.98

Output Swing (V) 0.5/2 0.08/2.93

Power consumption (W) 396 u 282 u

CMRR (dB) - 78.0 at low frequency

Settling time - 307.3 ns

PSRR dB) - 106 at low frequency

Slide No. 21Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

• The two-stage CMOS operational amplifiers employing Miller capacitor in conjunction with the common-gate two stage Op amp :

Increase : bandwidth, phase marginDecrease : size of Cc, power consumption.

Conclusion

Slide No. 22Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

[1] J. Mahattanakul and J. Chutichatuporn,“Design procedure for two-stage CMOS opamp with flexible noise-power balancing scheme,”IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 52, no. 8, pp. 1508–1514, Aug. 2005

Reference

Slide No. 23Department of Electrical Engineering ,Faculty of Science and Engineering , NCYU

VLSI LAB.

Thank you