open source hpc: an open source supercomputing platform
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PosterOpen Source HPC: An Open Source Supercomputing Platform
The idea of SoCs is starting to be applied to HPC, building chips from IP building blocks.
Motivation
Goal
Tiled Architecture Each tile will contain the open source RISC-V based Rocket core with a custom Personal Memory Engine (PME), connected to an OpenSoC Fabric network.
Hardware Architecture
Programming Model The Open Source HPC programming model will rely upon a MIMD approach where a single host (x86_64) application will launch multiple RISC-V threads. Each RISC-V thread may have additional, extended instruction support for application-specific computing workloads.
Software Infrastructure OpenHPC System Architect
FPGA Prototyping
To be able to test our proposed design, we’re using COTS FPGA systems with stacked memory to prototype the design.
Further Reading and Acknowledgements
http://www.opensuco.community
We’d like to acknowledge the Laboratory for Physical Science and the Department of Energy for helping fund this work.
Using pre-verified open source IP, we want to create an open source silicon chip complete with a full software toolchain, including specialized instructions.
§Lawrence Berkeley National Lab, ‡ Texas Tech University
Farzad Fatollahi-Fard§, David Donofrio§, John Shalf§ {ffard, ddonofrio, jshalf}@lbl.gov
John Leidel ‡, Xi Wang ‡, Yong Chen ‡
{john.leidel, xi.wang, yong.chen}@ttu.edu
North
East
South
Modules
VLSI Tools FPGA Tools
More and more projects are being made open- source, but they’re still based on closed-source IP.
New companies are being founded based on open source.
Open Source IP
Design
Personal Memory Engine The PME sits on the co-processor interface to the main Rocket core, providing a scratch pad, a basic scatter-gather engine, and message passing queues.
Rocket Tile
Router
Mesh Network The tiles will be arranged in a mesh networking using the open source OpenSoC Fabric, with a node for a connection to main memory and off-chip communication.
Compiler & Tool Chain The Open Source HPC compiler and tool chain will be based upon the LLVM compiler and tool infrastructure. The initial support will include C, C++ and ObjectiveC source compilation using the RISC- V LLVM target. In addition to basic RISC-V support, the OpenHPC System Architect environment will also provide auto-generated instruction, register and inline intrinsic extensions for application-specific architecture support.
Execution Environment The Open Source HPC execution environment will provide essential execution and debugging capabilities using an abstract set of interfaces. The OHPCRUN tool will provide users the ability to initiate application workloads on the device as well as provide a messaging interface for client debuggers to interact with an active workload. The LLVM LLDB client debugger will be utilized in order to provide a facility for breakpoints, single stepping, core file analysis, reading/modifying register state and reading/modifying memory state on an active OpenHPC device.
FPGA Top
HMC Controller
and between chips
Local HMC
Local HMC
Local HMC
Local HMC
AC-510 Module
We are targeting multiple FPGA boards to maximize prototyping capabilities.
PLXPCIe to Host
The idea of SoCs is starting to be applied to HPC, building chips from IP building blocks.
Motivation
Goal
Tiled Architecture Each tile will contain the open source RISC-V based Rocket core with a custom Personal Memory Engine (PME), connected to an OpenSoC Fabric network.
Hardware Architecture
Programming Model The Open Source HPC programming model will rely upon a MIMD approach where a single host (x86_64) application will launch multiple RISC-V threads. Each RISC-V thread may have additional, extended instruction support for application-specific computing workloads.
Software Infrastructure OpenHPC System Architect
FPGA Prototyping
To be able to test our proposed design, we’re using COTS FPGA systems with stacked memory to prototype the design.
Further Reading and Acknowledgements
http://www.opensuco.community
We’d like to acknowledge the Laboratory for Physical Science and the Department of Energy for helping fund this work.
Using pre-verified open source IP, we want to create an open source silicon chip complete with a full software toolchain, including specialized instructions.
§Lawrence Berkeley National Lab, ‡ Texas Tech University
Farzad Fatollahi-Fard§, David Donofrio§, John Shalf§ {ffard, ddonofrio, jshalf}@lbl.gov
John Leidel ‡, Xi Wang ‡, Yong Chen ‡
{john.leidel, xi.wang, yong.chen}@ttu.edu
North
East
South
Modules
VLSI Tools FPGA Tools
More and more projects are being made open- source, but they’re still based on closed-source IP.
New companies are being founded based on open source.
Open Source IP
Design
Personal Memory Engine The PME sits on the co-processor interface to the main Rocket core, providing a scratch pad, a basic scatter-gather engine, and message passing queues.
Rocket Tile
Router
Mesh Network The tiles will be arranged in a mesh networking using the open source OpenSoC Fabric, with a node for a connection to main memory and off-chip communication.
Compiler & Tool Chain The Open Source HPC compiler and tool chain will be based upon the LLVM compiler and tool infrastructure. The initial support will include C, C++ and ObjectiveC source compilation using the RISC- V LLVM target. In addition to basic RISC-V support, the OpenHPC System Architect environment will also provide auto-generated instruction, register and inline intrinsic extensions for application-specific architecture support.
Execution Environment The Open Source HPC execution environment will provide essential execution and debugging capabilities using an abstract set of interfaces. The OHPCRUN tool will provide users the ability to initiate application workloads on the device as well as provide a messaging interface for client debuggers to interact with an active workload. The LLVM LLDB client debugger will be utilized in order to provide a facility for breakpoints, single stepping, core file analysis, reading/modifying register state and reading/modifying memory state on an active OpenHPC device.
FPGA Top
HMC Controller
and between chips
Local HMC
Local HMC
Local HMC
Local HMC
AC-510 Module
We are targeting multiple FPGA boards to maximize prototyping capabilities.
PLXPCIe to Host