openpower foundation overview
DESCRIPTION
Steve Fields from IBM presented these slides at the recent Stanford HPC Conference. Learn more: http://www.open-power.org/ and http://www.hpcadvisorycouncil.com/events/2014/stanford-workshop/agenda.php Watch the video presentation: http://insidehpc.com/2014/02/14/openpower-foundation-overview/TRANSCRIPT
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OpenPOWER Foundation Overview
February 2014
Steve FieldsIBM Distinguished EngineerDirector of Power Systems Design
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Goal and Intent of OpenPOWER
Opening the architecture, providing ability to innovate across full Hardware and Software stack
– Simplify system design with alternative architecture– Includes SOC design, Bus Specifications, Reference Designs– Open Source Firmware + Operating System + Hypervisor
Driving an expansion of enterprise class Hardware and Software stack for the data center
Building a complete ecosystem to provide customers with the flexibility to build servers best suited to the POWER architecture
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The number of companies designing & building servers is increasing– Traditionally there have been few companies designing systems (HP, IBM, SUN, Dell etc…)– Today there are many more: Google, Microsoft, Facebook, Rackspace etc…– A fairly mature ecosystem including the Taiwanese ODMs is a key enabler of this trend
Two disruptive forces are impacting these custom system designs and driving designers to seek alternative architectures
– Technology integration is migrating what is board customization today to chip customization– A need for choice and options in processor sourcing
The POWER architecture is a proven server-class technology with a growing server software ecosystem
These trends creates an opportunity for a server targeted “chip-system-software” ecosystem
– OpenPOWER expands the opportunity for members to grow this ecosystem
There is an opportunity for POWER to participate in Web2.0 and large-scale data centers
Why form OpenPOWER?
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Giving ecosystem partners a license to innovate
OpenPOWER will enable datacenters to rethink their approach to technology
Member companies may use POWER for custom open servers and components for
Linux based cloud data centers
OpenPOWER ecosystem partners can optimize the interactions of server building
blocks – microprocessors, networking, I/O & other components – to tune performance
How will OpenPOWER Foundation benefit clients?
– OpenPOWER technology creates greater choice for customers
– Open and collaborative model on the Power platform will create more opportunity for innovation
– New innovators will broaden the capability and value of the Power platform
What does this mean to the industry?
– Game changer on the competitive landscape of the server industry–Will enable and drive innovation in the industry
–Provide more choice to the industry
How will OpenPOWER Foundation benefit clients?
– OpenPOWER technology creates greater choice for customers
– Open and collaborative model on the Power platform will create more opportunity for innovation
– New innovators will broaden the capability and value of the Power platform
What does this mean to the industry?
– Game changer on the competitive landscape of the server industry–Will enable and drive innovation in the industry
–Provide more choice to the industry
Platinum MembersPlatinum Members
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OpenPOWER Foundation – Structure
OpenPOWER is an industry foundation based on the POWER architecture, enabling an Open community for development and opportunity for member
differentiation and growth
Store
Channel Corp.
OPENEcosystemCommunity
Open Source Software Linkages to other groups Development workgroups
Chip Design Group Open IP Blocks Interface specifications
Development groups
System Design Group Specifications Reference Designs
Arc
hite
ctur
e &
S
peci
ficat
ion
Gro
up
Value Add
Num
erou
s Pa
rtic
ipan
ts
Development & Specification
Complementary“FOR PROFIT”
Ecosystem
OpenPOWER Compliance
Fee based component examples• Chip IP • IBM SW stack• Member SW stack• POWER on a card or board
To Ensure Compliance:All offerings must be validatedConsistent with Architecture &Interface Specifications
Store
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Proposed Ecosystem Enablement
CAPP
PCIe
POWER8
CAPI over PCIe
“Standard POWER Products” – 2014
Har
dwar
e
“Custom POWER SoC” – Future
Customizable
Framework to Integrate System IP on Chip Industry IP License Model
Multiple Options to Design with POWER Technology Within OpenPOWER
Power Open Source Software Stack Components
Firmware
CloudSoftware
OperatingSystem / KVM
Hardware
XCAT
ExistingOpen
Source Software
Communities
New OSS Community
Standard OperatingEnvironment
(System Mgmt)
System Operating Environment Software Stack
OpenPOWERTechnology
A modern development environment is emerging based on this type of tools and services
Softw
are
OpenPOWERFirmware
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TechnologyFAB
I/ONetworkingStorage
FWOpenSourceSYS
ODMOEM
SWLinuxISVOpen Source
Welcoming members at all levels
ChipSoC DevIP DevTechnology
FAB
I/ONetworkingStorage
FWOpenSourceSYS
ODMOEM
SWLinuxISVOpen Source
Welcoming members at all levels
ChipSoC DevIP Dev
Ecosystem Concept
WEB 2.0Data CenterMSPCloud
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Membership Options
Membership Level
Annual Fee FTEs IP contribution Technical Steering Committee
Board / Voting position
Platinum $100k 10 Desired significant, in addition to FTEs
One seat per member not otherwise represented
Includes board positionIncludes TSC position
Gold $60k 3 Not required May be on TSC if Project Lead
Gold members may elect up to one BOD member per three gold members
Silver $20k 0 Not required May be on TSC if Project Lead
One Board seat elected by all Silver members
Associate & Academic
$0 0 Not required May be on TSC if Project Lead
May be elected to one community observer board seat
Membership Levels
Organized as a distinct 501c6 Not-for-profit entity with a Board of Directors and a Technical Steering Committee.
• Membership levels provide either a default Board of Director position (Platinum) or an opportunity to be elected to the Board (Gold, Silver, and Assoc/Academic members). The Bylaws detail additional governance by the Board including maximum seats, terms, etc.
• Technical Steering Committee. Formed from the Project Leads from the core projects and one representative designated by each Platinum member
Includes tiered membership of Platinum, Gold, Silver, and individual memberships• Annual fee and dedicated full-time equivalent (FTEs) - verification of committed number of FTEs on honor system• Contributors, committers, and project leads influence Technical Steering Committee
Membership agreement, Bylaws, and IP Rights Policy available for reviewMembership agreement, Bylaws, and IP Rights Policy available for review
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OpenPOWER Foundation Progress
Completed legal formation activities
– Completed legal formation of entity as a standalone not-for-profit 501c6 entity, ratified Bylaws and IP Rights Policy
– Formalized Board of Directors and elected officers• Chairman: Gordon MacKean, Engineering Director, Platforms, Google• President: Brad McCredie, Vice President and IBM Fellow, IBM• Vice President: Michael Diamond, Senior Director Marketing, Nvidia
– Chartered Technical Steering Committee and initiated Work Groups:• System Software• Application Software• Open Server Development Platform• Hardware Architecture
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Work Groups and ProjectsWork Group Projects ParticipantsSystem Software Linux - Little Endian Public
(Open Source) KVM Public
Firmware–OpenPower FW Interface
Public
POWER LE ABI Public
Application Software
(Open Source)
System Operating Environment–OpenPOWER Software ecosystem enablement
Public
Toolchain Public
Open Server Development Platform
POWER8 Developer Board Restricted
POWER8 Reference Design Restricted
Hardware Architecture Compliance Member
OpenPOWER profile of architecture–POWER8 ISA Book 1, 2, 3
Restricted
Coherent Accelerator Interface Architecture (CAIA)
Restricted
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OpenPOWER Foundation Next Steps
Current initiatives to build industry momentum and strengthen organization– Make progress on work groups and projects, formalize process for initiating new work groups or
projects– Welcome new members via individual conversations, initiate on-boarding process– Develop identity / web site
March 2014 Launch with software development environment and preliminary hardware design
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Caches •512 KB SRAM L2 / core•96 MB eDRAM shared L3•Up to 128 MB eDRAM L4 (off-chip)
Memory•Up to 230 GB/s sustained bandwidth
Bus Interfaces•Durable open memory attach interface•Integrated PCIe Gen3•SMP Interconnect•CAPI (Coherent Accelerator Processor Interface)
Cores •12 cores (SMT8)•8 dispatch, 10 issue, 16 exec pipe•2X internal data flows/queues•Enhanced prefetching•64K data cache, 32K instruction cache
Accelerators•Crypto & memory expansion•Transactional Memory •VMM assist •Data Move / VM Mobility
Energy Management•On-chip Power Management Micro-controller•Integrated Per-core VRM•Critical Path Monitors
Technology•22nm SOI, eDRAM, 15 ML 650mm2
L3 Cache & Chip Interconnect
8M L3Region
Mem. Ctrl.Mem. Ctrl.
SMP LinksAccelerators
SMP LinksPCIe
POWER8 Processor
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CoreCore
L2L2
L3L3
POWER8 Building Blocks
System Infrastructure(SMP interconnect, memory,
I/O, energy mgmt, etc)
System Infrastructure(SMP interconnect, memory,
I/O, energy mgmt, etc)
• Flexible dynamic threading up to SMT8
• 64B L2 to L1 data bus
• 64KB Data Cache
• 32KB Instruction Cache
• Flexible dynamic threading up to SMT8
• 64B L2 to L1 data bus
• 64KB Data Cache
• 32KB Instruction Cache
• 512KB 8-way L2 cache per core
• 12-core chip provides 96MB L3 (12 x 8MB 8-way Banks)
• 12-core chip interconnect
• 150 GB/sec x 12 segments/direction = 3.6 TB/sec
• 512KB 8-way L2 cache per core
• 12-core chip provides 96MB L3 (12 x 8MB 8-way Banks)
• 12-core chip interconnect
• 150 GB/sec x 12 segments/direction = 3.6 TB/sec
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…with 16MB of Cache…
MemoryBuffer
DRAMChips
DDR InterfacesDDR Interfaces
POWER8POWER8LinkLink
Scheduler &Scheduler &ManagementManagement
16MB16MBMemoryMemoryCacheCache
Memory Buffer Functions•Memory Scheduling logic for 4 DIMM channels•L4 Cache for performance & energy efficiency•Energy Mgmt, RAS decision point
Processor Interface•9.6 Gbit/s interface•Robust error detection & dynamic lane sparing •Extensible protocol for innovation build-out
System Design Points•Support buffer on motherboard or on DIMM•Support 1, 2, 4 or 8 buffers per processor socket
• Up to 230 GB/sec per processor socket• Up to 128 GB of L4 Cache per processor socket
POWER8 Memory Buffer
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CustomHardware
Application
POWER8
CAPP
Coherence Bus
PSL
FPGA or ASIC
POWER8
PCIe Gen 3Transport for encapsulated messages
Processor Service Layer (PSL)• Present robust, durable interfaces to applications• Offload complexity / content from CAPP
Virtual Addressing• Accelerator can work with same memory addresses that the
processors use• Pointers de-referenced same as the host application• Removes OS & device driver overhead
Hardware Managed Cache Coherence• Enables the accelerator to participate in “Locks” as a normal
thread Lowers Latency over IO communication model
POWER8 CAPICoherent Accelerator Processor Interface (CAPI)
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CAPI for Hardware Acceleration
Custom Hardware Acceleration Unit (FPGA or ASIC)– Implement specific system, middleware or application function– Written to durable interface provided by PSL
Accelerator function operates as part of application– Behaves as another hardware thread running the application– Eliminates overhead associated with traditional PCIe attach
CustomHardware
Application
PSL
FPGA or ASIC
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CAPI for Attachment of I/O Devices
I/O Device can operate at user level– Behaves as another hardware thread running the application– Eliminates overhead associated with traditional I/O Device Driver model
• No pinned pages or memory copies required• Ability to address all of system memory
Advantages of CAPI protocol being transported over PCIe Gen3 interfaces– Compatible with industry ASIC design capabilities– Same device able to operate in PCIe and CAPI modes– CAPI devices have access to system tailstock for external connectivity
I/OController
PSL
FPGA or ASICNetwork or
Storage Interface
Network or Storage Interface
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OpenPOWER Foundation Benefits
System Design
Open the POWER Architecture to enable broader usage and collaboration
Enable and drive innovation in the industry
Data Center
Enable innovation across the stack to optimize deployment
Enable choice in architecture and processor sourcing
Customer
Greater choice
New levels of capability through innovation and broad collaboration in the POWER platform
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Membership Application and Inquiries
Membership Level
Annual Fee FTEs IP contribution Technical Steering Committee
Board / Voting position
Platinum $100k 10 Desired significant, in addition to FTEs
One seat per member not otherwise represented
Includes board positionIncludes TSC position
Gold $60k 3 Not required May be on TSC if Project Lead
Gold members may elect up to one BOD member per three gold members
Silver $20k 0 Not required May be on TSC if Project Lead
One Board seat elected by all Silver members
Associate & Academic
$0 0 Not required May be on TSC if Project Lead
May be elected to one community observer board seat
Membership Levels
Membership agreement, Bylaws, and IP Rights Policy available for reviewMembership agreement, Bylaws, and IP Rights Policy available for review
Very simple 2-page application:•Contact information for Representative, Accounts Payable contact, Technical contact, Marketing/Communications contact
•Desired Level of Membership
•Signature
For further information email [email protected]
Very simple 2-page application:•Contact information for Representative, Accounts Payable contact, Technical contact, Marketing/Communications contact
•Desired Level of Membership
•Signature
For further information email [email protected]
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20IBM Confidential20 Confidential
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© 2013 OpenPOWER