optical switching comprehensive article

L1 - 1© P. Raatikainen Switching Technology / 2005

Optics Switching Technology


General

•This document is collected from internet and is written by Lecturer:Pertti Raatikainen, research professor /VTTemail: [email protected]

• Exercises:Kari Seppänen, snr. research scientist /VTTemail: kari.seppä[email protected]

• Information: http://www.netlab.hut.fi/opetus/s38165


Goals of the course

• Understand what switching is about• Understand the basic structure and functions of a

switching system• Understand the role of a switching system in a

transport network• Understand how a switching system works• Understand technology related to switching• Understand how conventional circuit switching is

related to packet switching


Course outline

• Introduction to switching– switching in general

– switching modes– transport and switching

• Switch fabrics– basics of fabric architectures

– fabric structures– path search, self-routing and sorting


Course outline

• Switch implementations– PDH switches

– ATM switches– routers

• Optical switching– basics of WDM technology

– components for optical switching– optical switching concepts


Course requirements

• Preliminary information– S-38.188 Tietoliikenneverkot or

S-72.423 Telecommunication Systems(or a corresponding course)

• 13 lectures (á 3 hours) and 7 exercises (á 2 hours)• Calculus exercises• Grating

– Calculus 0 to 6 bonus points – valid in exams in 2005

– Examination, max 30 points


Course material

• Lecture notes

• Understanding Telecommunications 1, Ericsson & Telia, Studentlitteratur, 2001, ISBN 91-44-00212-2, Chapters 2-4.

• J. Hui: Switching and traffic theory for integrated broadband networks, Kluwer Academic Publ., 1990, ISBN 0-7923-9061-X, Chapters 1 - 6.

• H. J. Chao, C. H. Lam and E. Oki: Broadband Packet Switching technologies – A Practical Guide to ATM Switches and IP routers, John Wiley & Sons, 2001, ISBN 0-471-00454-5.

• T.E. Stern and K. Bala: Multiwavelength Optical Networks: A Layered Approach, Addison-Wesley, 1999, ISBN 0-201-30967-X.


Additional reading

• A. Pattavina: Switching Theory - Architecture and Performance in Broadband ATM Networks, John Wiley & Sons (Chichester), 1998, IBSN 0-471-96338-0, Chapters 2 - 4.

• R. Ramaswami and K. Sivarajan, Optical Networks, A Practical Perspective, Morgan Kaufman Publ., 2nd Ed., 2002, ISBN 1-55860-655-6.


ScheduleDay L/E Topic18.1. L Introduction to switching25.1. L Transmission techniques and multiplexing27.1. E Exercise 11.2. L Basic concepts of switch fabrics8.2. L Multistage fabric architectures 1

10.2. E Exercise 215.2. L Multistage fabric architectures 222.2. L Self- routing and sorting networ ks24.2. E Exercise 31.3. L Switch fabric implementations8.3. L PDH switches

10.3. E Exercise 415.3. L ATM switches17.3. E Exercise 522.3. L Routers 5.4. L Introduction to optical networks7.4. E Exercise 6

12.4. L Optical network architectures19.4. L Optical switches21.4. E Exercise 7


Introduction to switching

Switching Technology S38.165http://www.netlab.hut.fi/opetus/s38165


Introduction to switching

• Switching in general• Switching modes• Transport and switching


Switching in general

ITU-T specification for switching:

“The establishing, on-demand, of an individual connection from a desired inlet to a desired outlet within a set of inlets and outlets for as long as is required for the transfer of information.”

inlet/outlet = a line or a channel


Switching in general (cont.)

• Switching implies directing of information flows in communications networks based on known rules

• Switching takes place in specialized network nodes

• Data switched on bit, octet, frame or packet level

• Size of a switched data unit is variable or fixed


Why switching ?

• Switches allow reduction in overall network cost by reducing number and/or cost of transmission links required to enable a given user population to communicate

• Limited number of physical connections implies need for sharing of transport resources, which means– better utilization of transport capacity

– use of switching

• Switching systems are central components in communications networks


Full connectivity between hosts

Full mesh Number of links to/from a host = n-1

Total number of links = n(n-1)/2


Centralized switching

Number of links to/from a host = 1

Total number of links = n


Switching network to connect hosts

Number of links to/from a host = 1

Total number of links dependson used network topology


Hierarchy of switching networks

Localswitchingnetwork

Long distanceswitching network

To higher level of hierarchy


Sharing of link capacity

Space Division Multiplexing (SDM)

1

2

n

...

3 ...

Physicallink

CH 1

CH 2

CH n

Physicallink

1

2

n

...

3

Space to be divided:- physical cable or twisted pair- frequency- light wave


Sharing of link capacity (cont.)

1

2

n

...

1

2

n

...

123n12 …... n-1

Synchronous transfer mode (STM)

kOverhead Payload

Asynchronous transfer mode (ATM)1

2

n

...

1

2

n

...

12n1... idle 21 idle

Time Division Multiplexing (TDM)


Main building blocks of a switch

InputInterfaceCard #1

InputInterfaceCard #1Input

interface #1

Switchfabric

OutputInterfaceCard #1

OutputInterfaceCard #1Output

interface #1

Switch control

• input signal reception• error checking and recovery• incoming frame disassembly• buffering• routing/switching decision

• switching of data units from input interfaces to destined output interfaces

• limited buffering

• buffering, prioritizing and scheduling

• outgoing frame assembly • output signal generation and

transmission

• processing of signaling/connection control information• configuration and control of input/output interfaces and switch fabric


Heterogeneity by switching

• Switching systems allow heterogeneity among terminals – terminals of different processing and transmission speeds supported

– terminals may implement different sets of functionality

• and heterogeneity among transmission links by providing a variety of interface types

– data rates can vary

– different link layer framing applied

– optical and electrical interfaces

– variable line coding


Heterogeneity by switching (cont.)

…

Subscribermux

……

Remotesubscriber

switch

Analog interface

ISDN (2B+D) or E1

E1 or E2

E1, E2 or E3


Basic types of witching networks

• Statically switched networks – connections established for longer periods of time

(typically for months or years)– management system used for connection manipulation

• Dynamically switched networks– connections established for short periods of time (typically from

seconds to tens of minutes)

– active signaling needed to manipulate connections

• Routing networks– no connections established - no signaling– each data unit routed individually through a network– routing decision made dynamically or statically


Development of switching technologies

1950 1960 199019801970 2000 20202010

SPC, analog switching

Crossbar switch

Manual SPC - stored program control

Step-by-step

SPC, digital switching

Broadband, electronic

Broadband,optical

Source: Understanding Telecommunications 1, Ericsson & Telia, Studentlitteratur, 2001.


Development of switching tech. (cont.)

• Manual systems– in the infancy of telephony, exchanges were built up with manually operated switching

equipment (the first one in 1878 in New Haven, USA)

• Electromechanical systems– manual exchanges were replaced by automated electromechanical switching systems

– a patent for automated telephone exchange in 1889 (Almon B. Strowger)

– step-by-step selector controlled directly by dial of a telephone set

– developed later in the direction of register-controlled system in which number information is first received and analyzed in a register – the register is used to select alternative switching paths (e.g. 500 line selector in 1923 and crossbar system in 1937)

– more efficient routing of traffic through transmission network

– increased traffic capacity at lower cost


Development of switching tech. (cont.)

• Computer-controlled systems– FDM was developed round 1910, but implemented in 1950’s (ca. 1000 channels

transferred in a coaxial cable)

– PCM based digital multiplexing introduced in 1970’s – transmission quality improved –costs reduced further when digital group switches were combined with digital transmission systems

– computer control became necessary - the first computer controlled exchange put into service in 1960 (in USA)

– strong growth of data traffic resulted in development of separate data networks and switches – advent of packet switching (sorting, routing and buffering)

– N-ISDN network combined telephone exchange and packet data switches

– ATM based cell switching formed basis for B-ISDN

– next step is to use optical switching with electronic switch control – all optical switching can be seen in the horizon


Roadmap of Finnish networking technologies

1955 -60 -65 -70 -75 -80 -85 -90 -95 2000

Automation of long distance telephonyDigital transmission

Digitalization of ExchangesISDN

Data networks

WWW

Arpanet ---> Internet technology

NMT-450NMT-900

Circuit switching Packet sw

GSMUMTS


Challenges of modern switching

• Support of different traffic profiles• constant and variable bit rates, bursty traffic, etc.

• Simultaneous switching of highly different data rates• from kbits/s rates to Gbits/s rates

• Support of varying delay requirements• constant and variable delays

• Scalability• number of input/output links, link bit rates, etc.

• Reliability• Cost• Throughput


Switching modes



Narrowband network evolution

• Early telephone systems used analog technology - frequency division multiplexing (FDM) and space division switching (SDS)

• When digital technology evolved time division multiplexing (TDM) and time division switching (TDS) became possible

• Development of electronic components enabled integration of TDM and TDS => Integrated Digital Network (IDN)

• Different and segregated communications networks were developed – circuit switching for voice-only services

– packet switching for (low-speed) data services

– dedicated networks, e.g. for video and specialized data services


Segregated transport

Dedicatednetwork

Packet switchingnetwork

Circuit switchingnetwork

Voice

Data

DataVideo

Voice

Data

DataVideo

UNI UNI


Narrowband network evolution (cont.)

• Service integration became apparent to better utilize communications resources => IDN developed to ISDN (Integrated Services Digital Network)

• ISDN offered– a unique user-network interface to support basic set of narrowband services– integrated transport and full digital access– inter-node signaling (based on packet switching)

– packet and circuit switched end-to-end digital connections– three types of channels (B=64 kbit/s, D=16 kbit/s and H=nx64 kbit/s)

• Three types of long-distance interconnections– circuit switched, packet switched and signaling connections

• Specialized services (such as video) continued to be supported by separate dedicated networks


Integrated transport

Dedicatednetwork

Packet switchingnetwork

ISDNswitch

Circuit switchingnetwork

Signalingnetwork

ISDNswitch

UNI UNI

DataVideo

VoiceData

DataVideo

VoiceData


Broadband network evolution

• Progress in optical technologies enabled huge transport capacities=> integration of transmission of all the different networks

(NB and BB) became possible

• Switching nodes of different networks co-located to configure multifunctional switches

– each type of traffic handled by its own switching module

• Multifunctional switches interconnected by broadband integrated transmission (BIT) systems terminated onto network-node interfaces (NNI)

• BIT accomplished with partially integrated access and segregatedswitching


Narrowband-integrated access and broadband-integrated transmission

Ad-hocswitch

Packetswitch

ISDNswitch

Circuitswitch

Signalingswitch

UNI

VoiceData

DataVideo

Ad-hocswitch

Packetswitch

Circuitswitch

Signalingswitch

ISDNswitch

UNI

VoiceData

DataVideo

Multifunctionalswitch

Multifunctionalswitch

NNI NNI


Broadband network evolution (cont.)

• N-ISDN had some limitations: – low bit rate channels

– no support for variable bit rates

– no support for large bandwidth services

• Connection oriented packet switching scheme, i.e., ATM (Asynchronous Transfer Mode), was developed to overcome limitations of N-ISDN=> B-ISDN concept => integrated broadband transport and switching (no more need for specialized switching modules or dedicated networks)


Broadband integrated transport

UNI

VoiceDataVideo

UNINNI NNI

B-ISDNswitch

B-ISDNswitch

VoiceDataVideo


OSI definitions for routing and switching

Routing on L3

L2L3

L2L3

L2L3

L2L3

L2L3

L2L3

L4 L4

Switching on L2

L2L3

L2L3

L2L3

L2L3

L2L3

L2L3

L4 L4


Switching modes

• Circuit switching• Cell and frame switching• Packet switching

– Routing– Layer 3 - 7 switching– Label switching


Circuit switching

Layer 1 Layer 1Limited error

detection Layer 1 Layer 1Limited error

detection

Network edge Switching node Network edge

• End-to-end circuit established for a connection

• Signaling used to set-up, maintain and release circuits

• Circuit offers constant bit rate and constant transport delay

• Equal quality offered to all connections

• Transport capacity of a circuit cannot be shared

• Applied in conventional telecommunications networks (e.g. PDH/PCM and N-ISDN)


Cell switching

• Virtual circuit (VC) established for a connection

• Data transported in fixed length frames (cells), which carry information needed for routing cells along established VCs

• Forwarding tables in network nodes

Layer 1

Error recovery & flow control

Layer 1

Layer 2 (L) Layer 2 (L)

Layer 1

Layer 2 (L)

Layer 2 (H)

Limited errordetection Layer 1

Limited errordetection


Error & congestioncontrol

Error & congestioncontrol Layer 2 (L)

Layer 2 (H)


Cell switching (cont.)

• Signaling used to set-up, maintain and release VCs as well as update forwarding tables

• VCs offer constant or variable bit rates and transport delay

• Transport capacity of links shared by a number of connections (statistical multiplexing)

• Different quality classes supported

• Applied, e.g. in ATM networks


Frame switching

• Virtual circuits (VC) established usually for virtual LAN connections

• Data transported in variable length frames (e.g. Ethernet frames), which carry information needed for routing frames along established VCs


Layer 1


Layer 1

MAC MAC

Layer 1

MAC

LLC





Error & congestioncontrol MAC

LLC


Frame switching (cont.)

• VCs based, e.g., on 12-bit Ethernet VLAN IDs (Q-tag) or 48-bit MAC addresses

• Signaling used to set-up, maintain and release VCs as well as update forwarding tables

• VCs offer constant or variable bit rates and transport delay

• Transport capacity of links shared by a number of connections (statistical multiplexing)

• Different quality classes supported

• Applied, e.g. in offering virtual LAN services for business customers


Packet switching

Layer 1

Layer 2

Layer 3

Layer 1

Layer 2

Layer 3Routing & mux

Error recovery&

flow control

Layer 1

Layer 2

Layer 3

Layer 1

Layer 2

Layer 3Routing & mux

Error recovery&

flow control


• No special transport path established for a connection

• Variable length data packets carry information used by network nodes in making forwarding decisions

• No signaling needed for connection setup


Packet switching (cont.)

• Forwarding tables in network nodes are updated by routing protocols

• No guarantees for bit rate or transport delay

• Best effort service for all connections in conventional packet switched networks

• Transport capacity of links shared effectively

• Applied in IP (Internet Protocol) based networks


Layer 3 - 7 switching

• L3-switching evolved from the need to speed up (IP based) packet routing

• L3-switching separates routing and forwarding

• A communication path is established based on the first packet associated with a flow of data and succeeding packets are switched along the path (i.e. software based routing combined with hardware based one)

• Notice: In wire-speed routing traditional routing is implemented in hardware to eliminate performance bottlenecks associated with software based routing (i.e., conventional routing reaches/surpasses L3-switching speeds)


Layer 3 - 7 switching (cont.)

• In L4 - L7 switching, forwarding decisions are based not only on MAC address of L2 and destination/source address of L3, but also on application port number of L4 (TCP/UDP) and on information of layers above L4

Layer 1

Layer 2

Layer 3

Layer 1

Layer 2

Layer 3

Flow control

Error recovery&

flow control

Layer 1

Layer 2

Layer 3

Layer 1

Layer 2

Layer 3Routing

Error recovery&

flow control


Layer 4 Layer 4

Layer 7 Layer 7... ...

RoutingRou

ting

info


Label switching

Layer 1

Layer 2

Layer 3

Layer 1

Layer 2

Flow control

Error recovery&

flow control

Layer 1

Layer 2

Layer 1

Layer 2

Layer 3Error recovery

&flow control


• Evolved from the need to speed up connectionless packet switching and utilize L2-switching in packet forwarding

• A label switched path (LSP) established for a connection



Label switching (cont.)

• Signaling used to set-up, maintain and release LSPs

• A label is inserted in front of a L3 packet (behind L2 frame header)

• Packets forwarded along established LSPs by using labels in L2 frames

• Quality of service supported

• Applied, e.g. in ATM, Ethernet and PPP

• Generalized label switching scheme (GMPLS) extends MPLS to be applied also in optical networks, i.e., enables light waves to be used as LSPs


Latest directions in switching

• The latest switching schemes developed to utilize Ethernet basedtransport

• Scalability of the basic Ethernet concept has been the major problem, i.e., 12-bit limitation of VLAN ID

• Modifications to the basic Ethernet frame structure have been proposed to extend Ethernet’s addressing capability, e.g., Q-in-Q, Mac-in-Mac, Virtual MAN and Ethernet-over-MPLS

• Standardization bodies favor concepts (such as Q-in-Q and VMAN) that are backward compatible with the legacy Ethernet frame

• Signaling solutions still need further development


Transmission techniques and multiplexing hierarchies



Transmission techniques and multiplexing hierarchies

• Transmission of data signals• Timing and synchronization• Transmission techniques and multiplexing

– PDH– ATM– IP/Ethernet– SDH/SONET– OTN– GFP


Transmission of data signals

• Encapsulation of user data into layered protocol structure

• Physical and link layers implement functionality that have relevance to switching

– multiplexing of transport signals (channels/connections)

– medium access and flow control

– error indication and recovery

– bit, octet and frame level timing/synchronization

– line coding (for spectrum manipulation and timing extraction)


Encapsulation of user data

PLH Physical layer

LLH Link layer payload

NLH Network layer payload

TLH Transport layer payload

User data

• error coding/indication• octet & frame synchronization• addressing• medium access & flow control

• line coding• bit level timing• physical signal generation/

recovery


Synchronization of transmitted data

• Successful transmission of data requires bit, octet, frame and packet level synchronism

• Synchronous systems (e.g. PDH and SDH) carry additional information (embedded into transmitted line signal) for accurate recovery of clock signals

• Asynchronous systems (e.g. Ethernet) carry additional bit patterns to synchronize receiver logic


Timing accuracy

• Inaccuracy of frequency classified in telecom networks to– jitter (short term changes in frequency > 10 Hz)– wander (< 10 Hz fluctuation)

– long term frequency shift (drift or skew)

• To maintain required timing accuracy, network nodes are connected to a hierarchical synchronization network

– Universal Time Coordinated (UTC): error in the order of 10-13

– Error of Primary Reference Clock (PRC) of the telecom network in the order of 10-11


Timing accuracy (cont.)

• Inaccuracy of clock frequency causes– degraded quality of received signal– bit errors in regeneration

– slips: in PDH networks a frame is duplicated or lost due to timing difference between the sender and receiver

• Based on applied synchronization method, networks are divided into– fully synchronous networks (e.g. SDH)– plesiochronous networks (e.g. PDH), sub-networks have nominally the

same clock frequency but are not synchronized to each other

– mixed networks


Methods for bit level timing

• To obtain bit level synchronism receiver clocks must be synchronized to incoming signal

• Incoming signal must include transitions to keep receiver’s clock recovery circuitry in synchronism

• Methods to introduce line signal transitions– Line coding– Block coding– Scrambling


Line coding

+V1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1

Uncoded

+V

-V

AMI RZ

+VADI RZ

+VADI

ADI - Alternate Digit InversionADI RZ - Alternate Digit Inversion Return to ZeroAMI RZ - Alternate Mark Inversion Return to Zero


Line coding (cont.)

• ADI, ADI RZ and codes alike introduce DC balance shift=> clock recovery becomes difficult

• AMI and AMI RZ introduces DC balance, but lacks effective ability to introduce signal transitions

• HDB3 (High Density Bipolar 3) code, used in PDH systems, guarantees a signal transition at least every fourth bit

• 0000 coded by 000V when there is an odd number of pulses since the last violation (V) pulse

• 0000 coded by B00V when there is an even number of pulses since the last violation pulse

1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1

+V

-V

HDB3B V

V


Line coding (cont.)

• When bit rates increase (> 100 Mbit/s) jitter requirements become tighter and signal transitions should occur more frequently than in HDB3 coding

• CMI (Coded Mark Inversion) coding was introduced for electronic differential links and for optical links

• CMI doubles bit rate on transmission link => higher bit rate implies larger bandwidth and shortened transmission distance

1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1

+V

-V

CMI


Block coding

• Entire blocks of n bits are replaced by other blocks of m bits (m > n)

• nBmB block codes are usually applied on optical links by using on-off keying

• Block coding adds variety of “1”s and “0”s to obtain better clock synchronism and reduced jitter

• Redundancy in block codes (in the form of extra combinations) enables error recovery to a certain extent

• When m>n the coded line signal requires larger bandwidth than the original signal

• Examples: 4B5B (FDDI), 5B6B (E3 optical links) and 8B10B (GbE)


Coding examples

0 0 0 00 0 0 10 0 1 00 0 1 1 0 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

0 0 0 0 0 Quiet line symbol1 1 1 1 1 Idle symbol0 0 1 0 0 Halt line symbol1 1 0 0 0 Start symbol1 0 0 0 1 Start symbol0 1 1 0 1 End symbol0 0 1 1 1 Reset symbol1 1 0 0 1 Set Symbol0 0 0 0 1 Invalid0 0 0 1 0 Invalid0 0 0 1 1 Invalid0 0 1 0 1 Invalid0 0 1 1 0 Invalid0 1 0 0 0 Invalid0 1 1 0 0 Invalid1 0 0 0 0 Invalid

Input word

Other output wordsOutput word

1 1 1 1 00 1 0 0 11 0 1 0 01 0 1 0 1 0 1 0 1 00 1 0 1 10 1 1 1 00 1 1 1 11 0 0 1 01 0 0 1 11 0 1 1 01 0 1 1 11 1 0 1 01 1 0 1 11 1 1 0 01 1 1 0 1

4B5B coding 5B6B codingInput word Output word

0 0 0 0 00 0 0 0 10 0 0 1 00 0 0 1 1

...1 1 1 0 01 1 1 0 11 1 1 1 01 1 1 1 1

1 0 1 0 1 11 0 1 0 1 01 0 1 0 0 11 1 1 0 0 0

...0 1 0 0 1 10 1 0 1 1 10 1 1 0 1 10 1 1 1 0 0


Scrambling

• Data signal is changed bit by bit according to a separate repetitive sequence (to avoid long sequences of “1”s or “0”s)

• Steps of the sequence give information on how to handle bits in the signal being coded

• A scrambler consists of a feedback shift register described by apolynomial (xN + … + xm + … + xk + … + x + 1)

• Polynomial specifies from where in the shift register feedback is taken

• Output bit rate is the same as the input bit rate

• Scrambling is not as effective as line coding


Scrambler example

SDH/STM-1 uses x7+x6+1 polynomial

Preset

x7x6x5x4x3x2x1x0

D D D D D D D D +

+

Xi

Di

Si

Scrambler

Xi

Preset

x7x6x5x4x3x2x1x0

D D D D D D D D +

+

Ri =Di

Si

Descrambler

Xi = Si⊕⊕⊕⊕Di

Ri = Si⊕⊕⊕⊕Xi= Si⊕⊕⊕⊕(Si⊕⊕⊕⊕Di) = Di


Methods for octet and frame level timing

• Frame alignment bit pattern• Start of frame signal• Use of frame check sequence


Frame alignment sequence

• Data frames carry special frame alignment bit patterns to obtain octet and frame level synchronism

• Data bits scrambled to avoid misalignment• Used in networks that utilize synchronous transmission,

e.g. in PDH, SDH and OTN• Examples

– PDH E1 frames carry bit sequence 0011011 in every other frame (even frames)

– SDH and OTN frames carry a six octet alignment sequence (hexadecimal form: F6 F6 F6 28 28 28) in every frame


Start of frame signal

• Data frames carry special bit patterns to synchronize receiver logic

• False synchronism avoided for example by inserting additional bits into data streams

• Used in synchronous and asynchronous networks, e.g., Ethernet and HDLC

• Examples– Ethernet frames are preceded by a 7-octet preamble field

(10101010) followed by a start-of-frame delimiter octet (10101011)

– HDLC frames are preceded by a flag byte (0111 1110)


Frame check sequence

• Data frames carry no special bit patterns for synchronization

• Synchronization is based on the use of error indication and correction fields – CRC (Cyclic Redundancy Check) calculation

• Used in bit synchronous networks such as ATM and GFP (Generic Framing Procedures)

• Example– ATM cells streams can be synchronized to HEC (Header Error

Control) field, which is calculated across ATM cell header


Transmission techniques

• PDH (Plesiochronous Digital Hierarchy)

• ATM (Asynchronous Transfer Mode)

• IP/Ethernet

• SDH (Synchronous Digital Hierarchy)

• OTN (Optical Transport network)

• GFP (Generic Framing Procedure)


Plesiochronous Digital Hierarchy (PDH)

64 kbit/s

2.048 Mbit/s

...

8.448 Mbit/s

34.368 Mbit/s

139.264 Mbit/s

x 32

x 4

x 4

x 4

E0

E1

E2

E3

E4

1 channel

30 channels

120 channels

480 channels

1920 channels• Transmission technology of the

digitized telecom network• Basic channel capacity 64 kbit/s• Voice information PCM coded

• 8 bits per sample• A or µµµµ law• sample rate 8 kHz (125 µµµµs)

• Channel associated signaling (SS7)• Higher order frames obtained by

multiplexing four lower order frames bit by bit and adding some synchr. and management info

• The most common switching and transmission format in the telecommunication network is PCM 30 (E1)


PDH E1-frame structure (even frames)

F0 F1 . . . F14 F15

Multi- frame

T0 T1 T2 T0 . . . T15 T16 T17 . . . T28 T29 T30 T31

Voice channels 1 - 15 Voice channels 16 - 30

C 0 0 1 1 0 1 1

Frame alignment time-slot

Frame alignment signal (FAS)

Error indicatorbit (CRC-4)

0 0 0 0 1 A 1 1

Multi-framealarm

Multi-frame alignment bit sequence in F0

Signaling time-slot

B1 B2 B3 B4 B5 B6 B7 B8

Voice channel 28

Voice sample amplitude

Polarity


PDH E1-frame structure (odd frames)

F0 F1 . . . F14 F15

Multi- frame

T0 T1 T2 T0 . . . T15 T16 T17 . . . T28 T29 T30 T31

Voice channels 1 - 15 Voice channels 16 - 30

C 1 A D D D D D

Frame alignment time-slot

Data bits formanagement

Error indicatorbit (CRC-4) Far end

alarm indication

a b c d a b c c

Channel 1signalingbits

Signaling time-slot

Channel 16signalingbits

Nowadays, time slot 1used for signaling and time slot 16 for voice


PDH-multiplexing

• Tributaries have the same nominal bit rate, but with a specified, permitted deviation (100 bit/s for 2.048 Mbit/s)

• Plesiochronous = tributaries have almost the same bit rate• Justification and control bits are used in multiplexed flows• First order (E1) is octet-interleaved, but higher orders (E2,

…) are bit-interleaved


PDH network elements

• concentrator– n channels are multiplexed to a higher capacity link that carries m

channels (n > m)

• multiplexer– n channels are multiplexed to a higher capacity link that carries n

channels

• cross-connect– static multiplexing/switching of user channels

• switch– switches incoming TDM/SDM channels to outgoing ones


Example PDH network elements

Concentrator

... m outputchannels

nin

put

chan

nels

n > m

... m outputchannels

nin

put

chan

nels

n = m

Multiplexer

Cross-connect

DXC

Switch

4

2

23

4 3 1

1

4 3 2 1 4

2

2

34

3

1

1

4 3

2

1


Synchronous digital hierarchy

155 Mbit/s

622 Mbit/s

2.48 Gbit/s

10 Gbit/s

40 Gbit/s

x 4

x 4

x 4

STM-1

STM-4

STM-16

STM-64

STM-256

x 4

Major ITU-T SDH standards:- G.707- G.783

Notice that each frame transmitted in 125 µs !


SDH reference model

- DXC Digital gross-connect- MPX Multiplexer- R Repeater

Trib

utar

ies

R RSTM-n

MPX DXC MPX

Trib

utar

ies

STM-n STM-n STM-n

Regenerationsection

Regenerationsection

Regenerationsection

Multiplexing sectionMultiplexing

section

Path layer connection


SDH-multiplexing

• Multiplexing hierarchy for plesiochronous and synchronous tributaries (e.g. E1 and E3)

• Octet-interleaving, no justification bits - tributaries visible and available in the multiplexed SDH flow

• SDH hierarchy divided into two groups:– multiplexing level (virtual containers, VCs)– line signal level (synchronous transport level, STM)

• Tributaries from E1 (2.048 Mbit/s) to E4 (139.264 Mbit/s) are synchronized (using justification bits if needed) and packed in containers of standardized size

• Control and supervisory information (POH, path overhead) added to containers => virtual container (VC)


SDH-multiplexing (cont.)

• Different sized VCs for different tributaries (e.g. VC-12/E1, VC-3/E3, VC-4/E4)

• Smaller VCs can be packed into a larger VC (+ new POH)

• Section overhead (SOH) added to larger VC => transport module

• Transport module corresponds to line signal (bit flow transferred on the medium)

– bit rate is 155.52 Mbit/s or its multiples

– transport modules called STM-N (N = 1, 4, 16, 64, ...)

– bit rate of STM-N is Nx155.52 Mbit/s

– duration of a module is 125 µs (= duration of a PDH frame)


SDH network elements

• regenerator (intermediate repeater, IR)– regenerates line signal and may send or receive data via

communication channels in RSOH header fields

• multiplexer– terminal multiplexer multiplexes/demultiplexes PDH and SDH

tributaries to/from a common STM-n

– add-drop multiplexer adds or drops tributaries to/from a common STM-n

• digital cross-connect– used for rearrangement of connections to meet variations of capacity or

for protection switching– connections set up and released by operator


Example SDH network elements

Cross-connect

DXC

STM-n

STM-n

STM-n

STM-n

STM-n

STM-n

ADM

Add-drop multiplexer

2 - 140 Mbit/s

STM-n STM-nADM

Terminal multiplexer

2 - 140 Mbit/s

STM-n


Generation of STM-1 frame

VC-12PDH/E1 MUX VC-4 STM-1

Justification

+ POH + POH + SOH


STM-n frame

Three main fields:– Regeneration and multiplexer section overhead (RSOH and MSOH)

– Payload and path overhead (POH)– AU (administrative) pointer specifies where payload (VC-4 or VC-3) starts

RSOH

AU-4 PTR

MSOH

nx9 octets nx261 octets

3

1

5

POH


Synchronization of payload

• Position of each octet in a STM frame (or VC frame) has a number

• AU pointer contains position number of the octet in which VC starts

• Lower order VC included as part of a higher order VC (e.g. VC-12 as part of VC-4)

RSOHAU-4 PTR

MSOH

RSOHAU-4 PTR

MSOH VC-4 no. 2

VC-4 no. 1

VC-4 no. 0STM-1no. k

STM-1no. k+1


• cell – 53 octets

• routing/switching– based on VPI and VCI

• adaptation – processing of user data into ATM cells

• error control– cell header checking and discarding

• flow control – no flow control– input rate control

• congestion control– cell discarded (two priorities)

ATM concept in summary


Segmentation and reassembly (SAR)

Phys

ATM

AALConvergence sublayer (CS)

Generic flow control

VPI/VCI translation

Multiplexing and demultiplexing of cells

TimingPhysical medium

Cell rate decoupling

HEC header sequence generation/verification

Cell delineation

Transmission frame adaptation

Transmission frame generation/recovery

TCPM

ATM protocol reference model


EX

TEATM

network

NNI UNI

Reference interfaces

NNI - Network-to-Network InterfaceUNI - User Network InterfaceEX - Exchange EquipmentTE - Terminal Equipment


ATM cell structure

ATMheaderATM

header Cell payloadCell payload

5 octets 48 octets

GFCGFC VPIVPI

VPIVPI VCIVCI

VCIVCI

VCIVCI PTIPTI CPLCPL

HECHEC

ATM header for UNI

UNI - User Network InterfaceNNI - Network-to-Network InterfaceVPI - Virtual Path IdentifierVCI - Virtual Channel IdentifierGFC - Generic Flow ControlPTI - Payload Type IdentifierCPL - Cell Loss PriorityHEC - Header Error Control

VPIVPI

VPIVPI VCIVCI

VCIVCI


HECHEC

ATM header for NNI

HEC = 8 x (header octets 1 to 4) / (x8 + x2 + x + 1)


VCI 1

VCI 2

VCI 1

VCI 2VPI 1

VPI 2

Physical channel

VPI 1

VPI 2

VCI 1

VCI 2

VCI 1

VCI 2

ATM connection types

VCI k - Virtual Channel Identifier kVPI k - Virtual Path Identifier k


Physical layers for ATM

• SDH (Synchronous Digital Hierarchy)– STM-1 155 Mbit/s– STM-4 622 Mbit/s– STM-16 2.4 Gbit/s

• PDH (Plesiochronous Digital Hierarchy)– E1 2 Mbit/s– E3 34 Mbit/s– E4 140 Mbit/s

• TAXI 100 Mbit/s and IBM 25 Mbit/s• Cell based interface

– uses standard bit rates and physical level interfaces (e.g. E1, STM-1 or STM-4)

– HEC used for framing


Transport of data in ATM cells

Physical layer

ATM layer

ATMadaptationlayer (AAL)

Network layer IP packet

≤≤≤≤ 65 535

AAL 5 payload PUU/CPI/LEN

CRC

Pad 0 - 47 octets(1+1+ 2) octets

4 octets

P - Padding octetsUU - AAL layer user-to-user indicatorCPI - Common part indicatorLEN - Length indicator

5

H Cell payload H Cell payload H Cell payload H Cell payload

48


SOH

AU-4 PTR

SOH

9 octets 261 octets

3

1

5

STM-1frame

ATM cell

J1

B3

C2

G1

F2

H4

Z3

Z4

Z5

......

... ...

...

...

VC-4frame

VC-4 POH

ATM cell encapsulation / SDH


32 octets

TS0 TS16Header

TS0 TS16

TS0 TS16 Header

TS0 TS16Header

TS0 TS16 Head.

...

TS0• frame alignment• F3 OAM functions

• loss of frame alignment• performance monitoring• transmission of FERF and LOC• performance reporting

TS16• reserved for signaling

ATM cell encapsulation / PDH (E1)


Cell based interface

Frame structure for cell base interfaces:

IDLE orPL-OAM

PL ATM layerH H ... ATM layerH IDLE or

PL-OAMPLATM layer

1 2 26 2727

• PL cells processed on physical layer (not on ATM layer)• IDLE cell for cell rate adaptation• PL-OAM cells carry physical level OAM information

(regenerator (F1) and transmission path (F3) level messages)• PL cell identified by a pre-defined header

• 00000000 00000000 0000000 00000001 (IDLE cell)• 00000000 00000000 0000000 00001001 (phys. layer OAM)• xxxx0000 00000000 0000000 0000xxxx (reserved for phys. layer)

H = ATM cell Header, PL = Physical Layer, OAM = Operation Administration and Maintenance


ATM network elements

• Gross-connect – switching of virtual paths (VPs)– VP paths are statically connected

• Switch– switching of virtual channel (VCs)

– VC paths are dynamically or statically connected

• DSLAM (Digital Subscriber Line Access Multiplexer)– concentrates a larger number of sub-scriber lines to a common higher

capacity link

– aggregated capacity of subscriber lines surpasses that of the common link


Ethernet

• Originally a link layer protocol for LANs (10 and 100 MbE)

• Upgrade of link speeds => optical versions 1GbE and 10 GbE=> suggested for long haul transmission

• No connections - each data terminal (DTE) sends data when ready - MAC is based on CSMA/CD

• Synchronization– line coding, preamble pattern and start-of-frame delimiter

– Manchester code for 10 MbE, 8B6T for 100 MbE, 8B10B for GbE


Ethernet frame

PreambleSFD

DA SA T/L Payload CRC

7 1 6 6 2 46 - 1500 4

64 - 1518 octets

Preamble - AA AA AA AA AA AA AA (Hex)SFD - Start of Frame Delimiter AB (Hex)DA - Destination AddressSA - Source AddressT/L - Type (RFC894, Ethernet) or Length (RFC1042, IEEE 802.3) indicatorCRC - Cyclic Redundance CheckInter-frame gap 12 octets (9,6 µµµµs /10 MbE)


1GbE frame

PreambleSFD

DA SA L Payload

7 1 6 6 2 46 - 1500 4

512 - 1518 octets

CRC Extension

Preamble - AA AA AA AA AA AA AA (Hex)SFD - Start of Frame Delimiter AB (Hex)DA - Destination AddressSA - Source AddressT/L - Type (RFC894, Ethernet) or Length (RFC1042, IEEE 802.3) indicatorCRC - Cyclic Redundancy CheckInter-frame gap 12 octets (96 ns /1 GbE)Extension - for padding short frames to be 512 octets long


Ethernet network elements

• Repeater– interconnects LAN segments on physical layer

– regenerates all signals received from one segment and forwards them onto the next

• Bridge– interconnects LAN segments on link layer (MAC)– all received frames are buffered and error free ones are forwarded to another

segment (if they are addressed to it)

• Hub and switch– hub connects DTEs with two twisted pair links in a star topology and repeats

received signal from any input to all output links– switch is an intelligent hub, which learns MAC addresses of DTEs and is

capable of directing received frames only to addressed ports


Optical transport network

• Optical Transport Network (OTN), being developed by ITU-T (G.709), specifies interfaces for optical networks

• Goal to gather for the transmission needs of today’s wide range of digital services and to assist network evolution to higher bandwidths and improved network performance

• OTN builds on SDH and introduces some refinements:– management of optical channels in optical domain– FEC to improve error performance and allow longer link spans

– provides means to manage optical channels end-to-end in optical domain (i.e. no O/E/O conversions)

– interconnections scale from a single wavelength to multiple ones


OTN reference model

- OCh Optical Channel- OA Optical Amplifier- OMS Optical Multiplexing Section- OMPX Optical Multiplexer- OTS Optical Transport Section

Opt

ical

chan

nels OA OA

Opt

ical

chan

nels

OTSOTS OTS

OMS

OCh

OMPX OMPX


OTN layers and OCh sub-layers

Optical transport section(OTSn)

Optical multiplexing section(OMSn)

Optical channel

SONET/SDH ATM Ethernet IP

OTUOptical channel transport unit

ODUOptical channel data unit

OPUOptical channel payload unit


OTN frame structure

• Three main fields– Optical channel overhead– Payload – Forward error indication field

Och Payload FEC

Client

Digital wrapper

FR SONET/SDH ATM GbE IP

DWDM

SONET/SDH

ATM/FR

GbE IP


OTN frame structure (cont.)

Ochoverhead Payload FEC

4 ro

ws

4080 bytes

1 ..... 16 17 ................................... 3824 3825 ... 4080

ODUoverhead

Frame alignmt. OTU overhead

OPUoverh.

1 ..... 7 15 ... 168 ..... 14

1234

OTU - Optical transport unitODU - Optical data unitOPU - Optical payload unitFEC - Forward error correction

• Frame size remains the same (4x4080) regardless of line rate=> frame rate increases as line rate increases

• Three line rates defined:• OTU1 2.666 Gbit/s• OTU2 10.709 Gbit/s• OTU3 43.014 Gbit/s


Generation of OTN frame and signal

+ OPU-OH

OPUClient signal

ODU

+ OTU-OH+ FEC

OTU

OTN frame generation

OChClient signal

OMUX OMS OTS

…

OChClient signal

OTN signal generation


OTN network elements

• optical amplifier– amplifies optical line signal

• optical multiplexer– multiplexes optical wavelengths to OMS signal– add-drop multiplexer adds or drops wavelengths to/from a common OMS

• optical cross-connect– used to direct optical wavelengths (channels) from an OMS to another– connections set up and released by operator

• optical switches ?– when technology becomes available optical switches will be used for

switching of data packets in the optical domain


Generic Framing Procedure (GFP)

• Recently standardized traffic adaptation mechanism especially for transporting block-coded and packet-oriented data

• Standardized by ITU-T (G.7041) and ANSI (T1.105.02) (the only standard supported by both organizations)

• Developed to overcome data transport inefficiencies of existing ATM, POS, etc. technologies

• Operates over byte-synchronous communications channels (e.g. SDH/SONET and OTN)

• Supports both fixed and variable length data frames

• Generalizes error-control-based frame delineation scheme (successfully employed in ATM)

– relies on payload length and error control check for frame boundary delineation


GFP (cont.)

• Two frame types: client and control frames– client frames include client data frames and client management frames

– control frames used for OAM purposes

• Multiple transport modes (coexistent in the same channel) possible– Frame-mapped GFP for packet data, e.g. PPP, IP, MPLS and Ethernet)

– Transparent-mapped GFP for delay sensitive traffic (storage area networks), e.g. Fiber Channel, FICON and ESCON


GFP frame types

GFP frames

Clientdata frames

Clientmanagement frames

Idle frames OA&M frames

Client frames Control frames


GFP client data frame

• Composed of a frame header and payload

• Core header intended for data link management– payload length indicator (PLI, 2 octets), HEC (CRC-16, 2 octets)

• Payload field divided into payload header, payload and optional FCS (CRC-32) sub-fields

• Payload header includes:– payload type (2 octets) and type HEC (2 octets) sub-fields

– optional 0 - 60 octets of extension header

• Payload:– variable length (0 - 65 535 octets, including payload header and FCS) for

frame mapping mode (GFP-F) - frame multiplexing

– fixed size Nx[536, 520] for transparent mapping mode (GFP-T) - no frame multiplexing


0 – 60 bytesextension header

(optional)

Payload FCS

GFP frame structure

Payloadarea

Coreheader

Core HEC

Payload length indicator

Payload[N x 536, 520 bytesor variable length

packet]

Payload header

Type HEC

Payload type UPIPTI PFI EXI

Extension HEC LSBExtension HEC MSB

SpareCID

CID - Channel identifierFCS - Frame Check SequenceEXI - Extension Header IdentifierHEC - Header Error CheckPFI - Payload FCS IndicatorPTI - Payload Type IndicatorUPI - User payload Identifier

Source: IEEE Communications Magazine, May 2002


GFP relationship to client signals and transport paths

SDH/SONET path OTN ODUk path

GFPclient-independent

GFPclient-dependent

Ethe

rnet

IP/P

PP

MAP

OS

RPR

Fibe

rC

hann

el

FICO

N

ESC

ON

Oth

ercl

ient

sign

als

Framemapped

Transparentmapped

ESCON - Enterprise System CONnectionFICON - Fiber CONnectionIP/PPP - IP over Point-to-Point ProtocolMAPOS - Multiple Access Protocol over SONET/SDHRPR - Resilient Packet Ring

Source: IEEE Communications Magazine, May 2002


Adapting traffic via GFP-F and GFP-T

FCS - Frame Check SequencecHEC - Core Header Error ControlPDU - Packet Data UnitPLI - Payload Length Indicator

PLI2 bytes

cHEC2 bytes

Payloadheader4 bytes

Client PDU(PPP, IP, Ethernet, RPR, etc.)

FCS(optional)

4 bytes

PLI2 bytes

cHEC2 bytes

Payloadheader4 bytes

8x64B/65B superblock #1 #2 ... #N-1 #NFCS

(optional)4 bytes

GFP-F frame

GFP-T frame


GFP-T frame mapping

8B 8B 8B 8B 8B 8B 8B 8B

64B/65B code block

8 x 64B/65B code blocks

Superblock (8 x 64B/65B code blocks + CRC-16)

CRC-16

GFP-T frame with five superblocks

Core header and payload header FCS (optional)

1

3 - 1© P. Raatikainen Switching Technology / 2003

Switch Fabrics



Switch fabrics

• Basic concepts• Time and space switching

• Two stage switches• Three stage switches• Cost criteria• Multi-stage switches and path search

2


Switch fabrics

• Multi-point switching• Self-routing networks

• Sorting networks• Fabric implementation technologies• Fault tolerance and reliability


Basic concepts

• Accessibility• Blocking

• Complexity• Scalability• Reliability• Throughput

3


Accessibility

• A network has full accessibility when each inlet canbe connected to each outlet (in case there are noother I/O connections in the network)

• A network has a limited accessibility when theabove given property does not exist

• Interconnection networks applied in today’s switchfabrics usually have full accessibility


Blocking

• Blocking is defined as failure to satisfy a connection requirementand it depends strongly on the combinatorial properties of theswitching networks

Blocking Others

Network class Network type Network state

Non-blockingWith

blockingstate

Without blockingstates

Strict-sensenon-blocking

Wide-sensenon-blocking

Rearrangeablynon-blocking

4


Blocking (cont.)

• Non-blocking - a path between an arbitrary idle inlet and arbitrary idleoutlet can always be established independent of network state at set-uptime

• Blocking - a path between an arbitrary idle inlet and arbitrary idle outletcannot be established owing to internal congestion due to the alreadyestablished connections

• Strict-sense non-blocking - a path can always be set up between anyidle inlet and any idle outlet without disturbing paths already set up

• Wide-sense non-blocking - a path can be set up between any idleinlet and any idle outlet without disturbing existing connections,provided that certain rules are followed. These rules prevent networkfrom entering a state for which new connections cannot be made

• Rearrangeably non-blocking - when establishing a path between anidle inlet and an idle outlet, paths of existing connections may have tobe changed (rearranged) to set up that connection


Complexity

• Complexity of an interconnection network is expressed bycost index

• Traditional definition of cost index gives the number of cross-points in a network– used to be a reasonable measure of space division switching

systems

• Nowadays cost index alone does not characterize cost of aninterconnection network for broadband applications– VLSIs and their integration degree has changed the way how

cost of a switch fabric is formed (number of ICs, powerconsumption)

– management and control of a switching system has a significantcontribution to cost

5


Scalability

• Due to constant increase of transport links and data rates onlinks, scalability of a switching system has become a keyparameter in choosing a switch fabric architecture

• Scalability describes ability of a system to evolve withincreasing requirements

• Issues that are usually matter of scalability– number of switching nodes– number of interconnection links between nodes

– bandwidth of interconnection links and inlets/outlets– throughput of switch fabric– buffering requirements

– number of inlets/outlets supported by switch fabric


Reliability

• Reliability and fault tolerance are system measures that have animpact on all functions of a switching system

• Reliability defines probability that a system does not fail within agiven time interval provided that it functions correctly at the startof the interval

• Availability defines probability that a system will function at agiven time instant

• Fault tolerance is the capability of a system to continue itsintended function in spite of having a fault(s)

• Reliability measures:– MTTF (Mean Time To Failure)– MTTR (Mean Time To Repair)– MTB (Mean Time Between Failures)

6


Throughput

• Throughput gives forwarding/switching speed/efficiency of aswitch fabric

• It is measured in bits/s, octets/s, cells/s, packet/s, etc.

• Quite often throughput is given in the range (0 ... 1.0], i.e. theobtained forwarding speed is normalized to the theoreticalmaximum throughput


Switch fabrics

• Basic concepts• Time and space switching• Two stage switches• Three stage switches• Cost criteria• Multi-stage switches and path search

7


Switching mechanisms

• A switched connection requires a mechanism thatattaches the right information streams to each other

• Switching takes place in the switching fabric, thestructure of which depends on network’s mode ofoperation, available technology and required capacity

• Communicating terminals may use different physicallinks and different time-slots, so there is an obviousneed to switch both in time and in space domain

• Time and space switching are basic functions of aswitch fabric


Space division switching

12345678

123456

INPUTS OUTPUTS

m INPUT LINKS n OUTPUT LINKSINTERCONNECTIONNETWORK

• A space switch directs traffic from input links to output links• An input may set up one connection (1, 3, 6 and 7), multiple

connections (4) or no connection (2, 5 and 8)

8


Crossbar switch matrix

• Crossbar matrix introduces the basic structure of a space switch• Information flows are controlled (switched) by opening and closing

cross-points• m inputs and n outputs => mn cross-points (connection points)• Only one input can be connected to an output at a time, but an input

can be connected to multiple outputs (multi-cast) at a time

12345678

1 2 3 4 5 6

m I

NPU

T LI

NK

S

n OUTPUT LINKS

MULTI-CAST

A CLOSED CROSS-POINT


An example space switch

• m x1 -multiplexer used to implement a space switch• Every input is fed to every output mux and mux control signals

are used to select which input signal is connected througheach mux

mx1

12

m

1 2 m

mx1 mx1

mux/connection control

9


Time division multiplexing

• Time-slot interchanger is a device, which buffers m incoming time-slots, e.g. 30 time-slots of an E1 frame, arranges new transmitorder and transmits n time-slots

• Time-slots are stored in buffer memory usually in the order theyarrive or in the order they leave the switch - additional control logicis needed to decide respective output order or the memory slotwhere an input slot is stored

INPUT CHANNELS OUTPUT CHANNELS

123456

Time-slot 1

Time-slot 2

Time-slot 3

Time-slot 4

Time-slot 5

Time-slot 6

1 23 45 6

TIME-SLOT INTERCHANGER

BUFFER SPACE FOR TIME-SLOTS


Time-slot interchange

12345678 123456

1

2

3

4

5

6

7

8

BUFFER FOR mINPUT/OUTPUT SLOTS

m I

NPU

T LI

NK

S

n O

UTPU

T LI

NKS(3) (2) (4) (1,6) (5)

DESTINATION OUTPUT #

10


Time switch implementation example 1

• Incoming time-slots are written cyclically into switch memory• Output logic reads cyclically control memory, which contains a pointer for

each output time-slot• Pointer indicates which input time-slot to insert into each output time-slot

123

...

Time-slot counter & R/W control

...k

m

Switchmemory

123

n

Controlmemory

...

...j (k)

123m …

Incoming frame buffer

12jn … …

Outgoing frame buffer

readaddress (k)

Cyclic read

writ

ead

dres

s (3

)

Cyclic write

read

/writ

ead

dres

s (j)


Time switch implementation example 2

• Incoming time-slots are written into switch memory by using write-addressesread from control memory

• A write address points to an output slot to which the input slot is addressed• Output time-slots are read cyclically from switch memory

123

...


...k

n

Switchmemory

12

3 (k)

m

Controlmemory

...

123m …


12jn … …


writeaddress (k)

Cyclic read

read

addr

ess

(3)

Cyclic write

read

/writ

ead

dres

s (2

)

11


Properties of time switches

• Input and output frame buffers are read and written at wire-speed,i.e. m R/Ws for input and n R/Ws for output

• Interchange buffer (switch memory) serves all inputs and outputsand thus it is read and written at the aggregate speed of all inputsand outputs=> speed of an interchange buffer is a critical parameter in timeswitches and limits performance of a switch

• Utilizing parallel to serial conversion memory speed requirementcan be cut

• Speed requirement of control memory is half of that of switchmemory (in fact a little moor than that to allow new control data tobe updated)


Time-Space analogy

• A time switch can be logically converted into a space switch bysetting time-slot buffers into vertical position => time-slots can beconsidered to correspond to input/output links of a space switch

• But is this logical conversion fair ?

123m … 123n …

…

1

2

3

m

…

1

2

3

m

Time switch

Space switch

12


Space-Space analogy

• A space switch carrying time multiplexed input and output signals can belogically converted into a pure space switch (without cyclic control) bydistributing each time-slot into its own space switch

Inputs and outputs are time multiplexed signals

(K time-slots)

…

12

m

…

12

n

1

…

12

m

…

12

n

2

…

12

m

…

12

n

K…

12

m

…

12

n

…

To switch a time-slot, it is enoughto control one of the K boxes


An example conversion

nK m

ultip

lexe

din

put s

igna

lson

eac

h lin

k

2

112

m

…

12

m

…

1

2

K

1

2

n

mxn KxK

1

2

K

nxm12

m

12

m

12

m

12

m

12

m

12

m

…

…

…

13


Properties of space and time switches

• number of cross-points (e.g.AND-gates)- m input x n output = mn- when m=n => n2

• output bit rate determines thespeed requirement for theswitch components

• both input and output linesdeploy “bus” structure=> fault location difficult

• size of switch memory (SM)and control memory (CM)grows linearly as long asmemory speed is sufficient, i.e.- SM = 2 x number of time-slots- CM = 2 x number of time-slots

• a simple and cost effectivestructure when memory speedis sufficient

• speed of available memorydetermines the maximumswitching capacity

Space switches Time switches


Switch fabrics



14


A switch fabric as a combination ofspace and time switches

• Two stage switches• Time-Time (TT) switch• Time-Space (TS) switch• Space-Time (SP) switch• Space-Apace (SS) switch

• TT-switch gives no advantage compared to a singlestage T-switch

• SS-switch increases blocking probability


A switch fabric as a combination ofspace and time switches (cont.)

• ST-switch gives high blocking probability (S-switch candevelop blocking on an arbitrary bus, e.g. slots from twodifferent buses attempting to flow to a common output)

• TS-switch has low blocking probability, because T-switchallows rearrangement of time-slots so that S-switching canbe done blocking free

12

n

12

n

…

TS n

TS 1TS 2

…

TS n

TS 1TS 2

…

…

TS n

TS 1TS 2 1

2

n

12

n

…

TS n

TS 1TS 2

…

TS n

TS 1TS 2

…

…

TS n

TS 1TS 2

ST-switch TS-switch

15


Time multiplexed space (TMS) switch

• Space divided inputs and each of themcarry a frame of three time-slots

• Input frames on each link aresynchronized to the crossbar

• A switching plane for eachtime-slot to direct incomingslots to destined outputlinks of thecorrespondingtime-slot

Cross-point closed

1 2 3 4

Ti

me

Space

4x4 plane for slot 1



12

34

12

34

12

34

Incoming frames

Outputs

TS3 TS2 TS1

Output link address

4 1

2 3 2

3 2 1

1 4


Connection conflicts in a TMS switch

• Space divided inputs and each of themcarry a frame of three time-slots

• Input frames on each link aresynchronized to the crossbar

• A switching plane for eachtime-slot to direct incomingslots to destined outputlinks of thecorrespondingtime-slot

Cross-point closed

1 2 3 4

Ti

me

Space




12

34

12

34

12

34

Incoming frames

Outputs

TS3 TS2 TS14 1 4

2 3 2

3 2 1

1 4

Connectionconflict

Conflict solvedby time-slotinterchange

16


TS switch interconnecting TDM links

1

2

3

TIME

3x3 TSI

OUTPUTS OF 4x4 TMS

SPACE

PLANE FO

R SLO

T 2

PLANE FO

R SLO

T 3

PLANE FO

R SLO

T 1

• Time division switchingapplied prior to spaceswitching

• Incoming time-slots canalways be rearranged suchthat output requests becomeconflict free for each slot ofa frame, provided that thenumber of requests for eachoutput is no more than thenumber of slots in a frame


SS equivalent of a TS-switch

3 PLANES

3x3S-SWITCHPLANES

4 PLANES

4x4S-SWITCHPLANES

3 IN

PUTS

4 OUTP

UTS

17


Connections through SS-switch

Coordinate (X, Y, Z)

stageplaneinput/output port

Example connections:- (1, 3, 1) => (2, 1, 2)- (1, 4, 2) => (2, 3, 4)

3x3S-SWITCHPLANES

4 PLANES

4x4S-SWITCHPLANES

(1, 3, 1)

(2, 1, 2)

(1, 4, 2)

(2, 3, 4)


Switch fabrics


• Two stage switches

• Three stage switches• Cost criteria• Multi-stage switches and path search

18


Three stage switches

• Basic TS-switch sufficient for switching time-slots onto addressedoutputs, but slots can appear in any order in the output frame

• If a specific input slot is to carry data of a specific output slot then atime-slot interchanger is needed at each output=> any time-slot on any input can be connected to any time-slot on any output=> blocking probability minimized

• Such a 3-stage configuration is named TST-switching(equivalent to 3-stage SSS-switching)

…

TS n

TS 1TS 2

…

TS n

TS 1TS 2

…

…

TS n

TS 1TS 21

2

n

…

TS n

TS 1TS 2

…

TS n

TS 1TS 2

…

…

TS n

TS 1TS 2 1

2

n

TST-switch:


SSS presentation of TST-switch

INPUTS

3x3T- or S-SWITCH

PLANES

4 PLANES

4x4S-SWITCHPLANES

3x3T- or S-SWITCH

PLANES

OUTPUTS3 HORIZONTALPLANES

4 PLANES

19


Three stage switch combinations

• Possible three stage switch combinations:• Time-Time-Time (TTT) ( not significant, no connection from

PCM to PCM)• Time-Time-Space (TTS) (=TS)• Time-Space-Time (TST)• Time-Space-Space (TSS)• Space-Time-Time (STT) (=ST)• Space-Time-Space (STS)• Space-Space-Time (SST) (=ST)• Space-Space-Space (SSS) (not significant, high probability

of blocking)• Three interesting combinations TST, TSS and STS


Time-Space-Space switch

• Time-Space-Space switch can be applied to increase switchingcapacity

…

TS n

TS 1TS 2

…

TS n

TS 1TS 2

…

…

TS n

TS 1TS 21

2

n

12

n

…

TS n

TS 1TS 2

…

TS n

TS 1TS 2

…

…

TS n

TS 1TS 21

2

n

12

n

20


Space-Time-Space switch

• Space-Time-Space switch has a high blocking probability (likeST-switch) - not a desired feature in public networks

12

n

12

n

…

TS n

TS 1TS 2

…

TS n

TS 1TS 2

…

…

TS n

TS 1TS 2


Graph presentation of space switch

• A space division switch can be presented by a graph G = (V, E)- V is the set of switching nodes- E is the set of edges in the graph

• An edge e ∈∈E is an ordered pair (u,v) ∈∈V- more than one edge can exist between u and v- edges can be consider to be bi-directional

• V includes two special sets (T and R) of nodes not consideredpart of switching network- T is a set of transmitting nodes having only outgoing edges(input nodes to switch)- R is a set of receiving node having only incoming edges (outputnodes from switch)

21


Graph presentation of spaceswitch (cont.)

• A connection requirement is specified for each t ∈∈T by subset Rt∈∈Rto which t must be connected- subsets Rt are disjoint for different t- in case of multi-cast Rt contains more than one element for each t

• A path is a sequence of edges (t,a), (a,b), (b,c), … ,(f,g), (g,r) ∈∈E,t ∈∈T, r∈∈R and a,b,c,…,f,g are distinct elements of V - (T+R)

• Paths originating from different t may not use the same edge

• Paths originating from the same t may use the same edges


Graph presentation example

INPUT NODES t OUTPUT NODES r

t1t2t3

t15

. . .

r1r2r3

r15

. . .

s1

s2

s5

v1

v2

v5

u1

u2

u3

v3

v4

s3

s4

V = (t1, t2 ,... t15, s1, s2 ,... s5 , u1, u2 , u3 , v1, v2 ,... v5 , r1, r2 ,... r15)E = {(t1, s1), ...(t15 , s5), (s1, u1), (s1, u2) ,... (s5, u3), (u1, v1 ), (u1, v2 ), ... (u3, v5 ),

(v1, r1 ), (v1, r2 ),... (v5, r15)}

22


SSS-switch and its graph presentation

INPUTS

3x3S-SWITCHPLANES

5PLANE

S

5x5S-SWITCHPLANES

3x3S-SWITCHPLANES

OUTPUTS3 HORIZONTAL PLANES

5PLANES

INPUTS t OUTPUTS r


Graph presentation of connections

INPUTS t OUTPUTS r

A PATH

A TREE

1


Switch Fabrics



Switch fabrics



2


Cost criteria for switch fabrics

• Number of cross-points• Fan-out• Logical depth• Blocking probability• Complexity of switch control• Total number of connection states• Path search


Cross-points

• Number of cross-points gives the number of on-off gates(usually “and-gates”) in space switching equivalent of a fabric

• minimization of cross-point count is essential when cross-pointtechnology is expensive (e.g. electro-mechanical and opticalcross-points)

• Very Large Scale Integration (VLSI) technology implementscross-point complexity in Integrated Circuits (ICs)=> more relevant to minimize number of ICs than number ofcross-points

• Due to increasing switching speeds, large fabric constructionsand increased integration density of ICs, power consumption hasbecome a crucial design criteria- higher speed => more power- large fabrics => long buses, fan-out problem and more driving power- increased integration degree of ICs => heating problem

3


Fan-out and logical depth

• VLSI chips can hide cross-point complexity, but introducepin count and fan-out problem

• length of interconnections between ICs can be long loweringswitching speed and increasing power consumption

• parallel processing of switched signals may be limited by thenumber of available pins of ICs

• fan-out gives the driving capacity of a switching gate, i.e. numberof inputs (gates/cross-points) that can be connected to an output

• long buses connecting cross-points may lower the number of gatesthat can be connected to a bus

• Logical depth gives the number of cross-points a signaltraverses on its way through a switch

• large logical depth causes excessive delay and signal deterioration


Blocking probability

• Blocking probability of a multi-stage switching networkdifficult to determine

• Lee’s approximation gives a coarse measure of blocking• Assume uniformly distributed load

• equal load in each input• load distributed uniformly among

intermediate stages (and theiroutputs) and among outputsof the switch

• Probability that an input isengaged is a = = λλS where- λ = input rate on an input link- S = average holding time of a link

kxnnxk

2

1

...

k

1

n

1

n

4


Blocking probability (cont.)

• Under the assumption of uniformly distributed load,probability that a path between any two switching blocksis engaged is p = an/k (k≥≥n)

• Probability that a certain path from an input block to anoutput block is engaged is 1 - (1-p)2 where the last term isthe probability that both (input and output) links aredisengaged

• Probability that all k paths between an input switchingblock and an output switching block are engaged is

B = [1 - (1- an/k )2 ]k

which is known as Lee’s approximation


Control complexity

• Give a graph G , a control algorithm is needed to find and set uppaths in G to fulfill connection requirements

• Control complexity is defined by the hardware (computation andmemory) requirements and the run time of the algorithm

• Amount of computation depends on blocking category and degree ofblocking tolerated

• In general, computation complexity grows exponentially as a functionof the number of terminal

• There are interconnection networks that have a regular structure forwhich control complexity is substantially reduced

• There are also structures that can be distributed over a large numberof control units

5


Management complexity

• Network management involves adaptation and maintenance of aswitching network after the switching system has been put in place

• Network management deals with• failure events and growth in connectivity demand• changes of traffic patterns from day to day• overload situations• diagnosis of hardware failures in switching system, control system

as well as in access and trunk network- in case of failure, traffic is rerouted through redundant built-inhardware or via other switching facilities- diagnosis and failure maintenance constitute a significant part ofsoftware of a switching system

• In order for switching cost to grow linearly in respect to total traffic,switching functions (such as control, maintenance, call processing andinterconnection network) should be as modular as possible


Example 1

• A switch with• a capacity of N simultaneous calls

• average occupancy on lines during busy hour is X Erlangs• Y % requirement for internal use• notice that two (one-way) connections are needed for a call

requires a switch fabric with M = 2 x [(100+Y)/100] x(N/X) inputsand outputs.

• If N = 20 000, X = 0.72 and Y = 10%

=> M = 2 x 1.1 x 20 000/0.72 = 61 112=> corresponds to 2038 E1 links 1

2

M

12

M

6


Amount of traffic in Erlangs

• Erlang defines the amount of traffic flowing through acommunication system - it is given as the aggregate holding time ofall channels of a system divided by the observation time period

• Example 1:- During an hour period three calls are made (5 min, 15 min and 10min) using a single telephone channel => the amount of trafficcarried by this channel is (30 min/60 min) = 0.5 Erlang

• Example 2:- a telephone exchange supports 1000 channels and during a busyhour (10.00 - 11.00) each channel is occupied 45 minutes on theaverage => the amount of traffic carried through the switch duringthe busy hour is (1000x45 min / 60 min) = 75 Erlangs


Erlang’s first formula

• Erlang 1st formula applies to systems fulfilling conditions- a failed call is disconnected (loss system)- full accessibility- time between subsequent calls vary randomly- large number of sources

• E1(5, 2.7) implies that we have a system of 5 inlets and offeredload is 2.7 Erlangs - blocking calculated using the formula is 8.5 %

• Tables and diagrams (based on Erlang’s formula) have beenproduced to simplify blocking calculations

(( ))E n A

An

AA A

n

n

n1 2

12

, !

! !

==++ ++ ++ ++�

Erlang 1st formula

7


Example 2

• An exchange for 2000 subscribers is to be installed and it isrequired that the blocking probability should be below 10 %.If E2 links are used to carry the subscriber traffic totelephone network, how many E2 links are needed ?- average call lasts 6 min- a subscriber places one call during a 2-hour busy period(on the average)

• Amount of offered traffic is (2000x6 min /2x60 min) = 100 Erl.

• Erlang 1st formula gives for 10 % blocking and load of 100 Erl.that n = 97=> required number of E1 links is ceil(97/30) = 4


Example 3

• Suppose driving current of a switching gate (cross-point) is 100 mAand its maximum input current is 8 mA

• How many output gates can be connected to a bus, driven by oneinput gate, if the capacitive load of the bus is negligibly small ?

• Fan-out = floor[100/8] = 12 c

c c c

1…

2 M• How many output gates can be connected

to a bus driven by one input gate if load ofthe bus corresponds to 15 % of the load ofa gate input) ?

• Fan-out = floor[100/(1.15x8)] = 10

8


Switch fabrics


• Two stage switches• Three stage switches• Cost criteria

• Multi-stage switches and path search


Multi-stage switching

• Large switch fabrics could be constructed by using asingle NxN crossbar, interconnecting N inputs to Noutputs- such an array would require N2 cross-points- logical depth = 1- considering the limited driving power of electronic or opticalswitching gates, large N means problems with signal quality (e.g.delay, deterioration)

• Multi-stage structures can be used to avoid aboveproblems

• Major design problems with multi-stages- find a non-blocking structure- find non-conflicting paths through the switching network

9


Multi-stage switching (cont.)

• Let’s take a network of K stages• Stage k (1≤k≤K) has rk switch blocks (SB)• Switch block j (1≤j≤ rk) in stage k is denoted by S(j,k)• Switch j has mk inputs and nk outputs• Input i of S(j,k) is represented by e(i,j,k)• Output i of S(j,k) is represented by o(i,j,k)• Relation o(i,j,k)= e(i’,j’,k+1) gives interconnection between output i

and input i’ of switch blocks j and j’ in consecutive stages k and k+1• Special class of switches:

• nk = rk+1 and mk = rk-1

• each SB in each stage connected to each SB in the next stage


Clos network

• parameter m1, n3, r1, r2, r3chosen freely

• other parameters determineduniquely by n1 = r2, m2 = r1,n2 = r3, m3 = r2

mk = number of inputs in a SB at stage knk = number of outputs in a SB at stage krk = number of SBs at stage k

SB = Switch Block

m1 = 3

n1 = r2 = 5

m2 = r1 = 3 n2 = r3 = 4 m3 = r2 = 5

r1 = 3

r3 = 4r2 = 5

n3 = 2

10


Graph presentation of a Clos network

n3 = 2

r1 = 3

r2 = 5r3 = 4

n1 = r2 = 5

m2 = r1 = 3 n2 = r3 = 4m3 = r2 = 5

m1 = 3

Every SB in stage k is connected to all rk+1 SBs in the followingstage k+1 with a single link.

1234

1234

4x4 switch


Path connections in a 3-stage network

1ST STAGESBs

SB a

2ND STAGESBs

3RD STAGESBs

SB b

SB c

SB x SB y

• An input of SB x may be connected to an output of SB y via amiddle stage SB a

• Other inputs of SB x may be connected to other outputs of SB yvia other middle stage SBs (b, c, …)

• Paull’s connection matrix is usedto represent paths in threestage switches

11


Paull’s matrix

a, b, c

r3y1 2 . . . . . .1

2

. . .

x

r1

. . .

Stag

e 1

switc

h bl

ocks

Stage 3 switch blocks

• Middle stage switch blocks (a, b, c) connecting 1st stage SB x to3rd stage SB y are entered into entry (x,y) in r1 x r3 matrix

• Each entry of the matrix may have 0, 1 or several middle stage SBs• A symbol (a,b,..) appears as many times in the matrix as there are

connections through it


Paull’s matrix (cont.)

Conditions for a legitimate point-to-point connectionmatrix:

1 Each row has at most m1 symbols, since there can be as manypaths through a 1st stage SB as there are inputs to it

Columns

At most min(m1, r2) symbols in row x

r3y1 2 . . . . . .1

2

. . .

x

r1

. . .

At most min(n3, r2) distinct symbols in row y

Row

s

2 Each column has at most n3 symbols, since there can be asmany paths through a 3rd stage SB as there are outputs from it

12


Paull’s matrix (cont.)

Conditions of a legitimate point-to-point connectionmatrix (cont.):

In case of multi-casting, conditions 1 and 3 may not be valid,because a path from the 1st stage may be directed via several2nd stage switch blocks. Conditions 2 and 4 remain valid.

3 Symbols in each row must be distinct, since only one edgeconnects a 1st stage SB to a 2nd stage SB=> there can be at most r2 different symbols

4 Symbols in each column must be distinct, since only one edgeconnects a 2nd stage SB to a 3rd stage SB and an edge doesnot carry signals from several inputs => there can be at most r2 different symbols


Strict-sense non-blocking Clos

A network is strict sense non-blocking if any t ∈T- T’ can establisha legitimate multi-cast tree to any subset R - R’ without changes tothe previously established paths.

A rearrangeable network satisfies the same conditions, but allowschanges to be made to the previously established paths.

• T’ is a subset of set T of transmitting terminals

• R’ is a subset of set R of receiving terminals

• Each element of T’ is connected by a legitimate multi-cast tree toa non-empty and disjoint subset R’

• Each element of R’ is connected to one element of T’

Definitions:

13


Clos theorem

A Clos network is strict-sense non-blocking if and only if thenumber of 2nd stage switch blocks fulfills the condition

r2 ≥ m1 + n3 - 1

r2 ≥ 2n - 1

Clos theorem:

• A symmetric Clos network with m1 = n3 = n is strict-sense non-blocking if


Proof of Clos theorem

• Let’s take some SB x in the 1st stage and some SB y in the 3rdstage, which both have maximum number of connection minus one.=> x has m1 -1 and y has n3 -1 connections

• One additional connection should be established between x and y

• In the worst case, existing connections of x and y occupy distinct2nd stage SBs=> m1 -1 SBs for paths of x has and n3 -1 SBs for paths of y

• To have a connection between x and y an additional SB is neededin the 2nd stage=> required number of SBs is (m1 -1) + (n3 -1) + 1 = m1 + n3 -1

Proof 1:

14


Visualization of proof

y

x

m1-1

2

1

...

n3-1

2

1

...

1

n1

1

m3


Paull’s matrix and proof of Clos theorem

• A connection from an idle input of a 1st stage SB x to an idleoutput of a 3rd stage SB y should be established

• m1-1 symbols can exist already in row x, because there are m1

inputs to SB x.

• n3-1 symbols can exist already in row y, because there are n3

outputs to SB y.

• In the worst case, all the (m1-1 + n3-1) symbol are distinct

• To have an additional path between x and y, one more SB isneeded in the 2nd stage=> m1 + n3 -1 SBs are needed

Proof 2:

15


Procedure for making connections

• Keep track of symbols used by row x using an occupancy vector ux(which has r2 entries that represent SBs of the 2nd stage)

• Enter “1” for a symbol in ux if it has been used in row x, otherwiseenter “0”

• Likewise keep track of symbols used by column y using anoccupancy vector uy

• To set up a connection between SB x and SB y look for a position jin ux and uy which has “0” in both vectors

• Amount of required computationis proportional to r2

ux 0 1 1 0 0 11 2 3 j r2

1 1 0 0 1 01 2 3 j r2

uy

common “0”


Rearrangeable networks

A three stage network is rearrangeable if and only if

r2 ≥ max(m1, n3)

Slepian-Duguid theorem:

A symmetric Clos network with m1 = n3 = n is rearrangeably non-blocking if

r2 ≥ n

Paull’s theorem:The number of circuits that need to be rearranged is at most

min(r1, r3) -1

16


Connection rearrangement byPaull’s matrix

• If there is no common symbol (position j) found in ux and uy, we lookfor symbols in ux that are not in uy and symbols in uy not found in ux

=> a new connection can be set up only by rearrangement

• Let’s suppose there is symbol a in ux (not in uy) and symbol b in uy(not in ux) and let’s choose either one as a starting point

• Let it be a then b is searched from the column in which a resides (inrow x) - let it be column j1 in which b is found in row i1

• In row i1 search for a - let this position be column j2 n

• This procedure continues until symbol a or b cannot be found in thecolumn or row visited

1 1 0 1 11 2 b r2

uy 1a

ux 1 1 0 1 11 2 a r2

1b


Connection rearrangement by Paull’smatrix (cont.)

• At this point connections identified can be rearranged by replacingsymbol a (in rows x, i1, i2, ...) by b and symbol b (in columns y, j1,j2, ...) by a

• a and b still appear at most once in any row or column• 2nd stage SB a can be used to connect x and y

r3

b

1 j1

1

a

r1

y j3 j2

i1

x

i2 a

b

b a

r31 j1

1

r1

y j3 j2

i1

x

i2b

a

b

b

a b

a

17


Example of connection rearrangementby Paull’s matrix

• Let’s take a three-stage network 24x25 with r1=4 and r3=5• Rearrangeability condition requires that r2=6

- let these SBs be marked by a, b, c, d, e and f

=> m1 = 6, n1 = 6, m2 = 4, n2 = 5, m3 = 6, n3 = 5

1

2

4

1(a)

2(b)

6(f)

6x6 4x5

1

2

5

6x512

6

12

6

12

6

12

5

12

5

12

5

…

…

…


Example of connection rearrangementby Paull’s matrix (cont.)

1st s

tage

SB

s

1 2

1

2

3

4

3 4 53rd stage SBs

f a b,e c

a,b

e,f

b,fd c

d

d

a

c

c

• In the network state shown below, a new connection is to beestablished between SB1 of stage 1 and SB1 of stage 3

• No SBs available in stage 2 to allow a new connection• Slepian-Duguid theorem => a three stage network is rearrangeable

if and only if r2 ≥ max(m1, n3)- m1 = 6, n3 = 5, r2 = 6 => condition fulfilled

• SBs c and d are selected to operate rearrangement

u1-1

u3-1

1 1 1 10a b c

1d e f

1 1 0 01a b c

0d e f

Occupancy vectors of SB1/stage 1and SB1/stage 3

18



1st s

tage

SB

s

1 2

1

2

3

4

3 4 53rd stage SBs

c,f a b,e d

a,b

e,f

b,fd c

c

c

a

d

d

• Start rearrangement procedure from symbol c in row 1 andcolumn 5

• 5 connection rearrangements are needed to set up the requiredconnection - Paull’s theorem !!!

1st s

tage

SB

s

1 2

1

2

3

4

3 4 53rd stage SBs

f a b,e c

a,b

e,f

b,fd c

d

d

a

c

c



1st s

tage

SB

s

1 2

1

2

3

4

3 4 53rd stage SBs

f a b,e c

a,b

e,f

b,fd c

d

d

a

c

c

1st s

tage

SB

s

1 2

1

2

3

4

3 4 53rd stage SBs

c,f a b,e d

a,b

e,f

b,fc d

c

c

a

d

d

• Paull’s theorem states that the number of circuits that need to berearranged is at most min(r1, r3) -1 = 3=> there must be another solution

• Start rearrangement procedure from d in row 4 and column 1=> only one connection rearrangement is needed

19


Recursive construction of switchingnetworks

• To reduce cross-point complexity of three stage switches individualstages can be factored further

• Suppose we want to construct an NxN switching network and letN = pxq

• A rearrangeably non-blocking Clos network is constructedrecursively by connecting a pxp, qxq and pxp rearrangeably non-blocking switch together in respective order=> under certain conditions result may be a strict-sense non-blocking network

• A strict-sense non-blocking network is constructed recursively byconnecting a p(2p - 1), qxq and p(2p - 1) strict-sense non-blockingswitch together in respective order=> result may be a rearrangeable non-blocking network


3-dimensional construction of arearrangeably non-blocking network

q PLANES p PLANES q PLANES

qxq

pxp pxp

Number of cross-points for the rearrangable construction is

p2q + q2p + p2q = 2 p2q + q2p

20


3-dimensional construction of a strict-sense non-blocking network

px(2p-1)

q PLANES p PLANESq PLANES

qxq

(2p-1)xp

Number of cross-points for the strictly non-blocking construction is

p(2p - 1)q + q2 (2p - 1) + p (2p - 1)q = 2p(2p - 1) q + q2 (2p - 1)


Recursive factoring of switchingnetworks

• N can be factored into p and q in many ways and these can befactored further

• Which p to choose and how should the sub-networks be factoredfurther ?

• Doubling in the 1st and 3rd stages suggests to start with the smallestfactor and recursively factor q = N/p using the next smallest factor=> this strategy works well for rearrangeable networks=> for strict-sense non-blocking networks width of the network isdoubled=> not the best strategy for minimizing cross-point count

• Ideal solution: low complexity, minimum number of cross-points andeasy to construct => quite often conflicting goals

21


Recursive factoring of a rearrangeablynon-blocking network

N IN

PUTS

N O

UTP

UTS

N/2 x N/2SWITCH

N/2 x N/2SWITCH

• Special case N = 2n, n being a positive integer=> a rearrangeable network can be constructed by factoring N into p = 2 and q = N/2=> resulting network is a Benes network=> each stage consists of N/2 switch blocks of size 2x2

• Factor q relates to the multiplexing factor (number of time-slots on inputs)=> recursion continued until speed of signals low enough for realimplementations


Benes network

N IN

PUTS

N O

UTP

UTS

Number of stages in a Benes network

K = 2log2N - 1

Baseline network Inverse baseline network

22


Benes network (cont.)

• Benes network is recursively constructed of 2x2 switch blocks and itis rearrangeably non-blocking (see Clos theorem)

• First half of Benes network is called baseline network

• Second half of Benes network is a mirror image (inverse) of the firsthalf and is called inverse baseline network

• Number of switch stages is K = 2log2N - 1

• Each stage includes N/2 2x2 switching blocks (SBs) and thusnumber of SBs of a Benes network is

Nlog2N - (N/2) = N(log2N - ½)

• Each 2x2 SB has 4 cross-points and number of cross-points in aBenes network is

4(N/2)(2log2N-1) = 4Nlog2N - 2N ∼∼ 4Nlog2N


Illustration of recursively factoredBenes network

16 I

NPU

TS

16 O

UTP

UTS

1


Switch Fabrics



Recursive factoring of a strict-sensenon-blocking network

• A strict-sense non-blocking network can be constructed recursively,but the size of network (number of cross-points) crows fast as afunction of the number of inputs, namely CNlog2N

• Instead of starting with the smaller factor for p let’s use switchblocks of

• Let N = 2n and n = 2l then we are factoring square switches withnumber of inputs and outputs being power of 2=> condition for a strict-sense non-blocking network states thatthere are r2 ≥ 2x2n/2 - 1 second stage SBs

• Let choose r2 = 2x2n/2 then sizes of the- 1st stage switches are 2n/2 x 2n/2+1

- 3rd stage switches are 2n/2+1 x 2n/2

• Each of these can be made of two SBs each of size 2n/2 x 2n/2

NxN

2


Recursive factoring of a strict-sensenon-blocking network (cont.)

• 2nd stage switches are of size 2n/2 x 2n/2

• The three stages consist of 6x2n/2 SBs, each of size 2n/2 x 2n/2

• Let F(2n ) be the cross-point complexity of an NxN switch then

• F(2n) = 6x2n/2F(2n/2 )

= 6lx2n/2+n/4+…+1F(21) < 6lx2nF(2)

= N(log2N)2.58F(2)

= 4N(log2N)2.58

• The difference between rearrangeable and strict-sense non-blocking networks lies in the exponent for the log2N term


Strict-sense non-blocking network withsmaller number of cross-points

• Strict-sense non-blocking networks with smaller number of cross-points than F(2n) = 4N(log2N)2.58 can be constructed

• One alternative is to use Cantor network, which is constructedusing Benes networks, multiplexers and demultiplexers

• i-th input of Cantor network connected to j-th input of j-thBenes network using j-th output of a 1xm demultiplexer

• i-th output of j-th Benes network connected to i-th output ofCantor network using j-th input of a mx1 multiplexer

• When N is known, number of required Benes planes to have astrict-sense non-blocking Cantor network is m = log 2N

• Since a Benes network has a cross-point count of 4Nlog2N, numberof cross-points of a Cantor network is roughly 4N(log 2N)2 (whenignoring cross-points of the multiplexers and demultiplexers

3


Cantor network

N IN

PUTS

N O

UTP

UTS

1 TO LOG(N)DEMULTIPLEXERS

1 TO LOG(N)MULTIPLEXERS


Cantor network strict-sensenon-blocking

Proof:• Markings

• m number of parallel Benes networks• k number of stage in a Benes network

• A(k) number of reachable 2x2 SBs without rearrangements instage k (1≤k≤log2N) starting from an input of a Cantor network

• Reachable 2x2 SBs in consecutive stages• A(1) = m• A(2) = 2A(1) - 1• A(3) = 2A(2) - 2• A(k) = 2A(k-1) - 2k-2 = 22A(k-2) - 2x2k-2 = 2k-1A(1) - (k-1)x2k-2

• A(log2N) = 2log2N-1m - (log2N -1) 2log2N-2

= ½Nm - ¼ (log2N -1)N

4


Cantor network strict-sensenon-blocking (cont.)

• Cantor network is symmetrical at the middle=> the same number of center stage nodes are reachable by anoutput of a Cantor network

• Total number of SBs in center stages is Nm/2 (m Benes networks)

• If the number of center stage SBs reached by an input and anoutput exceeds Nm/2 then there must be a SB reachable from both

• Hence strict-sense non-blocking is achieved if

[ ]2

Nm1)N-N(log-Nm2 24

121 >

=> m > log2N - 1

Notice that a strict-sense non-blocking Cantor network isconstructed of log2N rearrangeably non-blocking Benes networks


Visualization of proof

N IN

PUTS

N O

UTP

UTS

5


Dimensioning example of Cantor network

• number of multiplexers = 64 000• number of demultiplexers = 64 000• number of Benes networks m = log2N = 16

=> number of outputs in demultiplexers = 16=> number of inputs in Multiplexers = 16

• number of stages in Benes networks = 2log2N - 1 = 2x16-1 = 31• number of 2x2 SBs in Benes networks = Nlog2N = 216 * 32

≈ 2N SBs in each Benes network

Number of inputs and outputs of a switching network should be N = 32 x 2048 = 216 ≈≈ 64 000


Control algorithms

• Control algorithms for networks, which are formed recursively bythree stage factorization

• Control algorithms can be applied recursively• works well for strict-sense non-blocking networks when setting up

connections one at a time• for rearrangeable networks adding just one connections may cause the

connection pattern to change dramatically=> adding a connection to a Benes network can be as complicated asreconnecting all input-output pairs

• Let’s examine control algorithm for a Benes network, formed byfactoring recursively

• N = 2m inputs and outputs• start with a totally disconnected network and establish requested

connection patterns

6


Looping algorithm

During the first factorization of an NxN switch each 2x2 input SB maybe connected to a 2x2 output SB either via upper (U) or lower (L)N/2xN/2 switch (see figure)

1) InitializationStart with 2x2 input SB 1 and mark it by S

2) Loop forwardConnect an unconnected input of S to desired output by upperswitch U. If no connection is required, go to 4.

3) Loop backwardConnect the adjacent output of the output just visited to the desiredinput by the lower switch L. If no connection is required, go to 4.Otherwise, the newly visited input SB becomes S. Go to 2.


Looping algorithm (cont.)

N IN

PUTS

N O

UTP

UTS

N/2 x N/2UPPERSWITCH

N/2 x N/2LOWERSWITCH

4) Start new loopChoose another SB, which has not been visited yet as S. Go to 2.If all connections for the NxN switch are made, the algorithmterminates at level m.

7


Looping algorithm (cont.)

• Looping algorithm is applied recursively to establish connections forthe upper switch U and lower switch L

• Computation of paths is complex and time consuming and it can beshown that the total run time of the algorithm to compute paths for allinputs and outputs is proportional to (log2N )2

• Looping algorithm• suits for circuit switching, because connections computed per call• not suitable for packet switching, because connections may have

to be recomputed for all N input-output pairs within duration of apacket

• dedicating a processor for each input and output SB connection=> computations become faster, but exchange of path informationbetween processors gets very complicated

=> Alternative switching architectures needed for packet switching


Switch fabrics



8


Graph presentation of connectionpatterns

Multi-cast switching I O I O

Point-to-point switching

One-to-one connections One-to-many connectionsC = {(i,o)| i∈∈I , o∈∈O}I f (i,o) ∈∈C and (i,o’)∈∈C => o=o’I f (i,o) ∈∈C and (i’,o) ∈∈C => i=i’

C = {(i,ni)| i∈∈I , ni⊂⊂O}

C - a logical mapping from inputs to outputs


Graph presentation of connectionpatterns (cont.)

I OConcentrator

One-to-one connections

A

C = {(i,o)| i∈∈A⊂⊂I , o∈∈O}I f (i,o)∈∈C and (i,o’)∈∈C => o=o’I f (i,o)∈∈C and (i’,o) ∈∈C => i=i’

I O

Super-concentrator(compact if B compact)

One-to-one connections

A

C = {(i,o)| i∈∈A⊂⊂I , o∈∈ΒΒ⊂⊂O}I f (i,o)∈∈C and (i,o’)∈∈C => o=o’I f (i,o)∈∈C and (i’,o)∈∈C => i=i’

ΒΒ

To any member in O To any

member in specific B

9


Graph presentation of connectionpatterns (cont.)

CopyI O

One-to-many connections

A

C = {(i,ni)| i∈∈A⊂⊂I, ΣΣni∈∈N}

Order and identity of outputsni ignored (output unspecific)

To any ni members in O


Combinatorial bound

• ζζ(G) is log2 of the number of distinct and legitimate C realized by G

• R is number of cross-points in a switch fabric

• ζζ measures combinatorial power of a graph, may bear no directrelationship to control complexity of finding a switch setting to realizea connection pattern

• R2 is the number of states in a switch fabric of R cross-points=> rough upper bound for the number of Cs in G is ζζ≤≤ R

• Better upper bound obtained by removing- all non-legitimate states, e.g., those in which two cross-points arefeeding one output- one of states for which another state produces the same C

• Such improvements not easily found

10


Combinatorial bound (cont.)

• For each connection function, which defines a set of legitimate C,we may compute the logarithm of the total number of distinct C,marked by ζζ

• A graph G is rearrangeably non-blocking if all such C can berealized by G => we must have ζζ≤≤ ζζ(G) for rearrangeably non-blocking G

Let us look at number of different C measured as ζζ realized bydifferent connection functions

It follows that by observing the number of distinct C realized bydifferent connection functions, we can find the lower bound ofcomplexity for any rearrangeably non-blocking fabric.


Lower combinatorial bound forpoint-to-point connections

• NxN switch with full connectivity (any element in I can be connected toany distinct element in O)

• Obviously network that can realize all maximal connection patterns canrealize less than maximal patterns

• Number of C we want to realize equals to N!

• Sterling’s approximation:

=> N! ≈≈ √ NN+½ e-N = √ exp2(Nlog2N - Nlog2e + ½log2N)

=> ζζpt-pt = log2N! ≈≈ Nlog2N - 1.44N + ½log2N = O(NlogN)

• If 2x2 SBs are used, at least Nlog2N such SBs are needed to realize

the N! possible maximal connection patterns

=> A poit-to-point interconnection network has a complexity of O(NlogN)

2ππ 2ππ

11


Visualization of point-to-point mappings

N = 2 => Lc= 2

N = 3 => Lc= 6

Construction of C: Enumerate inputs, mix them in an arbitrary order.

Number of connection patterns in point-to-point switching Lc= N!


Lower bound of Benes network

16 I

NPU

TS

16 O

UTP

UTS

• Number of 2x2 SBs in a Benes network:=> 2log2N - 1 stages and each stage has N/2 SBs of size 2x2=> total number of 2x2 SBs is Nlog2N - N/2 , which is close to ζζpt-pt

=> total number of cross-points 4(Nlog2N - N/2) ≈≈ 4Nlog2N

12


Lower combinatorial bound formulti-point connections

• Let’s suppose that any input can be connected to any output, i.e.,each element in O may choose any one of the N inputs=> total number of connection patterns C is NN = exp2(Nlog2N)=> ζζmcast = Nlog2N=> ζζmcast - ζζpt-pt = 1.44N

• A fabric architecture that would implement multi-casting and wouldbe close to the lower bound of complexity is not known yet

• It is known that Benes network implements multi-cast if the numberof 2x2 SBs is doubled compared to the pt-to-pt case


Visualization of multi-cast mappings

etc. …

Number of connection patterns in multi-cast switching Lc= NN

N = 3 => Lc= 27

13


Lower combinatorial bound forconcentrator

• A concentrator with M inputs and N outputs (M>N)

• Connection pattern C defined to be a set of any N of the M inputs

• Number of these sets =MN

ζζ concentrator = logM!

N!(M N)!2 −−

≈≈−− −−

logM!

2 N(M N)!M

N (M N)2

M

N M-Nππ

• Sterling’s approximation:

Entropy function: H(c) = -clog2c - (1-c)log2(1-c)

M-1+N

M-1

0

0,2

0,4

0,6

0,8

1

1,2

0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1≈ ≈ MH(c)


Lower combinatorial bound forconcentrator (cont.)

• For given C => ζζconcentrator = O(M)

• This lower bound is smaller by a factor of logM than that of point-to-point or multi-point networks

• Although concentrators with linear complexity (linear to number ofinputs) can be shown to exist, there are no known practicalsolutions - complicated control algorithms

• It can be shown that a strict-sense non-blocking concentrator is ascomplex as a point-to-point non-blocking concentrator - M logM

• => MlogM-fabrics are used for concentration

14


Visualization of concentrator mappings

Concentrator MxN = 4x2 => Lc = 6

Number of connection patterns in concentrator Lc= ( )=MN

M!N!(N-M)!


Lower combinatorial bound forsuper-concentrator

• A super-concentrator with M inputs, N outputs and K elements(K≤≤ M,N)

• Connection pattern C defined to be a legitimate set of C = (A, B)by all A and B with K elements

• Total number of these sets =M

K

N

K

ζζ super con−− ≈≈

M HKM

+ N HKN

• Super concentrators more complex than concentrators• Compact super-concentrator specifies output set B once the

starting position of the compact sequence is specified => there areN possible starting positions and hence

ζζ super con−− ≈≈

M H

KM

+ log N2

15


Visualization of super-concentratormappings

Super concentrator M=4, N=3 and K=2 => Lc = 18

Number of connection patterns in super-concentrator

Lc= ( )( )=MK

M!N!K!(M-K)!K!(N-K)!

NK


Lower combinatorial bound forcopy network

• A copy network with M inputs and N outputs

• Connection requests ni over all inputs i is equal to N

=> Number of connection patterns C equals to

=> => ζζcopy ≈≈ (( ))M - 1+ NM 1

M 1 NH −−

−− ++

Complexity lower bound is liner in M and N

16


Visualization of copy mappings

Number of connection patterns in copy network

Lc= ( )=(M-1+N)!(M-1)!N!

M-1+NM-1

Copy MxN = 4x2 => Lc= 10

Lc is the number of ways N objects can be put into M bins.


Compact super-concentrator example

Inverse Banyan network formed by recursive 2-stage factoring usingsuper-concentrators

16 I

NPU

TS

16 O

UTP

UTS

17


Two stage factoring

M/p x q superconcentrators

p h

oriz

onta

l pal

esCOMPACT

SUPER CONCENTRATOR

p x N/q superconcentrators

q verti

cal p

ales

2-stage factoring can be used to construct compact super-concentrators


Distribution network

• Mirror image of a compact super-concentrator is called adistribution network

• Provided that an input-output connection pattern C = { (i,oi) }satisfies: - Compactness condition - active inputs i for the pair in C arecompact in modulo fashion- Monotone condition - outputs oi to be connected to each activeinput are strictly increasing in i in modulo fashion

a 2-stage network can be made a non-blocking one if theconnection requests arrive in sorted order - one way to achieve thisis to put a sorting network in front of a 2-stage network

• All point-to-point connections satisfying the above two conditionscan be connected using the distribution network

18


Compact and monotone connectionpattern

A modulo-wise compact set

0 12

3

4

. . .

N-1N-2

N-3

. . .

012345

N-4N-3N-2N-1

012345

N-4N-3N-2N-1

Compact activeinputs

Cyclicallymonotone outputs

... ...


Construction of a distribution network

COMPACTSUPER CONCENTRATOR DISTRIBUTION NETWORK

MIRROR IMAGE

19


Example of a distribution network

Distribution network based on inverse Banyan network

00000001

00100011

01000101

01100111

10001001

10101011

11001101

11101111

00000001

00100011

01000101

01100111

10001001

10101011

11001101

11101111


Construction of copy networks

• Distribution network which allows multiple connections between aninput and outputs is called a copy distribution network

• An input can make extra connections to outputs if the outputsconnected remain monotonically increasing with respect to theinputs- Compactness condition - active inputs i for the pair in C arecompact in modulo fashion- Monotone condition - each element in Oi is greater than eachelement in Oi’ if i >i’ in modulo fashion

• Inverse of many-to-one concentrator performs the copy functions

20


Copy distribution network

DISTRIBUTION NETWORK

MULTI-COPY INPUT

MONOTONESET OF Oi


Compact and monotone connectionpattern

Many-to-one concentration One-to-many copying

012345

N-4N-3N-2N-1

...

012345

N-4N-3N-2N-1

...

Cyclically monotone input sets

Compactoutputs

Cyclically monotone output sets

Compact activeinputs

MIRROR IMAGE 012345

N-4N-3N-2N-1

...

012345

N-4N-3N-2N-1

...

21


Construction of multi-cast networks

• Multi-cast networks can be constructed, e.g. by concatenating acopy network and a point-to-point network- 3-stage factorization can be applied to get a point-to-point network- resulting network consists of a concentrator, copy distributionnetwork and Benes network=> number of stages increases=> total number of 2x2 SBs is 2Nlog2N

• There are alternative ways to construct multi-cast networks, butthey encounter the above mentioned problems- number of stages increases

• Difficult to calculate connections through the fabric

• Complicated fabric control algorithms

• One way to solve the control problem is to use self-routing


Switch fabrics

• Multi-point switching• Self-routing networks• Sorting networks• Fabric technologies• Fault tolerance and reliability

22


Self-routing

• Self-routing is a popular principle in fast packet switching• Header of each packet contains all information needed to route

a packet through a switch fabric

• One or more paths may exist from an input to an output

• Interconnection network has the unique path property - if thesequence of nodes connecting an input to an output is uniquefor all input-output pairs

• An important class of networks having the unique property isthe generic banyan network- NlogN complexity- only one path connecting each input-output pair


Examples of unique route network

Banyan network Baseline network

Shuffle exchange (Omega) network Flip network (inverse shuffle exchange)

23


Self-routing principle

Switch block S1

Self-routingaddress bK ... b1

Self-routingaddress bK ... b2

Self-routingaddress

bK

Switch block S2

Switch block SK

n1

12

b1

......

n2

12

b2

......

nK

12

bK

......

• S1, S2 , … SK is a sequence of switch blocks, which have n1, n2,… nK outputs respectively

• Route of a packet uses the bk-th output of switch block k => route given by the sequence b1 b2 … bk … bK

• At switch block k, packet routed to output bk and address bk isremoved from the self-routing header


Self-routing principle (cont.)

000001

010011

100101

110111

000001

010011

100101

110111

00

01

10

11

00

01

10

11

00

01

10

11

UP=0DOWN=1

Edge 011 Edge 110

• In a self-routing shuffle exchange (NxN) network- N = 2K inputs and outputs interconnected by K stages of 2K-1 nodes- nodes numbered in each stage from 0 to 2K-1-1 (binary K-1 format)- links (= edges) in each stage numbered from 0 to 2K-1 (binary K format)- outgoing links numbered by appending “0” (up going links) or “1” (downgoing links) to the node’s number

24


Self-routing in a shuffle exchangenetwork

000001

010011

100101

110111

000001

010011

100101

110111

00 00 00

01 01 01

10 10 10

11 11 11

Source

Edge 1

Edge 2

Edge 3

Edge 4

0 0 1 1 0 1Destination

001

011

110

Edge 1 Edge 2 Edge 3 Edge 4

• Self-routing shuffle exchange scheme- a packet at input a1a2 … aK is destined to output b1b2 … bK- b1b2 … bK is used as the self-routing address (up link chosen if bk=0 and downlink if bk=1)- packet visits first node a2…aK => travels along edge a2…aKb1 => visits nodea3…aKb1 =>… => finally after visiting node b1…bn-1 arrives at output edge b1…bn


Monotone and compact addresses

• Top-down numbering of nodes and links can be used also for otherself-routing networks having the unique property

• If self-routing addresses of packets at the inputs satisfy conditions:

• addresses are strictly monotone in the sense that destinationaddresses are strictly increasing in top-down manner at theinputs

• packets are compact in the sense that there is no idle inputbetween any two inputs with packets

=> self-routing paths used by these packets do not share any link within the shuffle exchange network

=> no need for buffering at inputs of the internal nodes

25


Limitations of banyan networks

• Banyan network can realize exp2(½Nlog2N) = (NN)½ input-outputpermutations (connection patterns)

• Full connectivity requires N! connection patterns=> Banyan network is a blocking one

• Combinatorial power of banyan network can be increasedsignificantly by implementing- multiple links between nodes- duplicated switch- appended switch with random routing (shuffle)- buffering at intermediate nodes (=> undesirable random delay)

1


Switch Fabrics



Switch fabrics



2


Sorting networks

• Types of blocking

• Internal blocking

• Output blocking

• Head of line blocking

• Sorting to remove internal blocking

• Resolving output conflicts

• Easing of HOL blocking


Internal blocking

• Internal blocking occurs at the internal links of a switch fabric

• In a switch fabric, which implements synchronous slot timing,internal blocking implies that some input (i) to output (j)connection cannot be established (even if both are idle ones)

• Internally non-blocking switch makes all requested connections(i, ji), provided that there are no multiple request to the sameoutput (ji ≠ ji’ if i ≠ i’, 1≤i,j≤N)

12

Inputi

34

12

Outputj

34

Connection pattern = {(2, 1), (3, 4), (4, 3)}

Dest.ji

1

4

3

3


Output blocking

• Internally non-blocking switch can block at an output of a switchfabric due to conflicting requests, i.e., ji = ji’ for some i ≠ i’

• When output conflict occurs, switch should connect one of theconflicting inputs to requested output => output conflict resolution

• Major distinction between a circuit and packet switching node• a packet switching node must solve output conflicts per time-slot (time-

slots are not assigned beforehand)

• a circuit switching node solvespossible output conflicts andassigns a time-slot for entireduration of a connectionbeforehand

12

Inputi

34

12

Outputj

34

Dest.ji

1

4

3

3

Conflicting output request


Head of line (HOL) blocking

• Packets not forwarded due to output conflict are buffered=> more delay experienced

• Buffered packets normally served in a FCFS (First Come FirstServed) manner=> HOL blocking introduced at the input queues

• Packet facing HOL blockingmay prevent the next packet inthe queue to be delivered toa non-contended output=> throughput of a switchreduced

12

Inputi

34

12

Outputj

34

Dest.ji

14

43

31

32

Conflicting output requestPacket blocked by HOL queuing

4


Sorting to remove internal blocking

• If connection requests at the inputs of a banyan network arecompact and in strictly increasing order=> input-output paths are link-disjoint=> banyan internally non-blocking

• A method for building an internally non-blocking network is to applya sorting network in front of a banyan network to generate a strictincreasing order of destination addresses for the banyan network

• A sorting network connects an input i, which has a connectionrequest to output ji, to an output of a sorting network according tothe position of ji in the sorted list of destination requests (see figure)

• Sorting networks can be formed by interconnecting nodes of smallersorting networks (such as 2x2)

• Self-routing should be applied in the sorting network


Internally non-blocking and self-routingswitch

12

Inputi

34

Outputj

4

Dest.ji

1

4

3

123

1

3

4

Sorting network(Batcher)

Routing network(Banyan)

Compact and monotone output addresses

5


Sorting to remove internal blocking

• A permuted list (a1, a2 , …, aN) can be restored to its original orderby sorting

• A switching network for a maximal connection pattern can beobtained from a sorting network by treating 2x2 sorting elementsas 2x2 switching elements

• Asymptotic lower bound for 2x2 sorting elements to build a NxNsorting network is Nlog 2N (as for a respective switching network)- no sorting network found so far to obtain this bound

• Sequential merge-sorting process can be used to obtain Nlog2Nbound for the number of binary sorts


Merge-sorting algorithm

Merge-sorting algorithm• Input : unsorted list AN = (a1, a2 , …, aN)

• Sort procedure:Sort (AN) = Merge {Sort(a1, …, a½N), Sort (a½N+1 , …, aN)}

• Merge procedure:Merge {(a1, …, am), (a’1, …, a’m’)}

= {a1, (Merge ((a2, …, am), (a’1, …, a’m’))} if a1≤ a’1= {a’1, (Merge ((a1, …, am), (a’2, …, a’m’))} if a1> a’1

• Procedure Merge, called by procedure Sort, takes two sorted listsand merges them by comparing the smallest elements in each ofthe two sorted lists

6


Merge-sorting algorithm (cont.)

• Merging of two sorted lists (N/2 numbers in each) requires Nbinary sorts

• Total complexity of sorting N numbers is given byC(N) = 2C(N/2) = N + 2(N/2 + 2C(N/4)) = … = Nlog2N

• Due to sequential nature of procedure Merge the sorting takes atleast O(N) time

146

1011151720

2579

12141624

Compare numbers at the top of lists

then merge


Odd-even merging

a0

a1

a2

a3

aN/2-2

aN/2-1

...

b0

b1

bN/2-4

bN/2-3

bN/2-2

bN/2-1

...

e0

e1

eN/2-4

eN/2-3

eN/2-2

eN/2-1

...

e2

e3

e4

eN/2-5

Evenmerger

N/2

Oddmerger

N/2

......

......

......

d0

d1

dN/2-3

dN/2-2

dN/2-1

...

➙➙

➙➙

c0

c1

cN/2-2

cN/2-1

...

c2

...

Recursive construction of an odd-even merger- number of sorting stages is log2N- number of sorting elements is 0.5N [log2N-1]+1

7


Bitonic list

• Bitonic list AN = (a1, a2 , …, aN) is a list for which it holds thata1 ≤ a2 ≤ … ≤ ak-1 ≤ ak and ak ≥ ak+1 ≥ … ≥ aN-1 ≥ aN (1≤ k ≤ N)

• Unique cross-over property - when comparing a monotonicallyincreasing list with a monotonically decreasing list, there is at most oneposition where the two lists cross-over in their values (see figures)

146

1011151720

241614129752

<

>

Bitonic list

Cross-over

17202416141297

52146

101115<

>

Circular bitonic list

Cross-over


Bitonic merging

a0

a1

aN/2-2

aN/2-1

...

aN/2

aN/2+1

aN-2

aN-1

...

Bitonicmerger

N/2

Bitonicmerger

N/2

......

......

d0

d1

dN/2-3

dN/2-2

dN/2-1

...

c0

c1

cN/2-2

cN/2-1

...

c2

➙➙

➙➙

...

e0

e1

eN/2-2

eN/2-1

...

eN/2

eN/2+1

eN-2

eN-1

...

Recursive construction of a bitonic merger- number of sorting stages is log2N- number of sorting elements is 0.5N log2N

8


Sorting by merging

a0

a1

aN/2-2

aN/2-1

...

aN/2

aN/2+1

aN-2

aN-1

...

...

➙

➙

...

e0

eN-1

➙

➙

...

MergerN

MergerN/2

MergerN/4

MergerN/4

➙

➙

➙

MergerN/2

MergerN/4

MergerN/4

➙

➙

➙

...

...

Recursive construction of a sorting by merging network- number of sorting stages is 0.5Nlog2N(log2N + 1)


Odd-even sorting network example

➙ 2x2 UP SORTER

➙

2x2 DOWN SORTER

2x2SORTER

4x4SORTER

➙➙

➙

➙➙ ➙

➙

➙

➙➙ ➙

➙

➙

➙➙

➙

➙➙

➙

8x8SORTER

• Number of sorting stages is 0.5log2N(log2N + 1)• Number of sorting elements is 0.25N[log2N(log2N - 1) + 4] - 1

9


Bitonic sorting network example

➙ 2x2 UP SORTER

➙

2x2 DOWN SORTER

2x2SORTER

➙

➙

➙

➙ ➙ ➙

➙ ➙

➙

➙

➙

➙

➙

➙

➙

➙

➙

➙

➙

➙ ➙ ➙

➙ ➙

4x4SORTER

8x8SORTER

• Number of sorting stages is 0.5log2N(log2N + 1)• Number of sorting elements is 0.25Nlog2N(log2N + 1)


Batcher-Banyan self-routing network

➙ 2x2 UP SORTER

➙

2x2 DOWN SORTER

2x2BITONICSORTER

➙

➙

➙

➙ ➙ ➙

➙ ➙

➙

➙

➙

➙

➙

➙

➙

➙

➙

➙

➙

➙ ➙ ➙

➙ ➙

4x4BITONICSORTER

8x8BITONICSORTER

8x8ROUTER

SORTING NETWORK ROUTING NETWORK

10


Resolving output blocking

• Packet switches do not maintain a scheduler for dedicating time-slotsfor packets (at the inputs)=> output conflicts possible=> output conflict resolution needed on slot by slot basis

• Output conflicts solved by

• polling (e.g. round robin, token circulation)- do not scale for large numbers of inputs- outputs just served have an unfair advantage in getting a new time-slot

• sorting networks (making a banyan network internally non-blocking)

• An example of sorting networks is sort-purge-concentrate network• when sorting self-routing addresses, duplicated output requests appear

adjacent to each other in the sorted order (see figure)- either one has to be purged (deleted)- successful delivery is acknowledged and purged packets are re-sent


Sort-purge-concatenate network

12

Inputi

34

Outputj

4

Dest.ji

123

Sortingnetwork

Concentration network

Compact and sorted output addresses

1

3

4

1

3

3

4

3

1

4

3

Purgenetwork

Routing network(Banyan)

Sorted destinationaddresses

• A sorting network can easily handle packet priority by- adding a priority field in the self-routing address- higher priority packets are placed in a favorable position before purging- support of priority is an essential feature when integrating circuit andpacket switching in a sort-banyan network

11


Resolving HOL blocking

• HOL blocking solved by

• allowing packets behind a HOL packet to contend for outputs

• allow multiple delivery of conflicting HOL packets to an outputbuffer - multiple rounds of arbitration for sort-banyan network - multiple planes of sort-banyan networks

• a good solution is to implement multiple input buffers (one foreach output if possible) and if the packet in turn cannot betransmitted due to HOL, transmit an other packet from anotherbuffer


Construction of a multipointpacket switch

In a self-routing multipoint switch- incoming packets destined to multiple outputs- packets carry all destination addresses in their headers

COMPACT SUPERCONCENTRATOR

COPY DISTRIBUTIONNETWORK

BANYAN SWITCH

COPY NETWORK ROUTING NETWORK

12


Batcher-Banyan example

➙ 2x2 UP SORTER

➙

2x2 DOWN SORTER

2x2BITONICSORTER

➙

➙

➙

➙ ➙ ➙

➙ ➙

➙

➙

➙

➙

➙

➙

➙

➙

➙

➙

➙

➙ ➙ ➙

➙ ➙

4x4BITONICSORTER

8x8BITONICSORTER

8x8ROUTER

SORTING NETWORK ROUTING NETWORK

000/110 (6)001/100 (4)

010/ *** (-)011/011 (3)

100/111 (7)101/010 (2)

110/ *** (-)111/001 (1)

Source/dest.

6

4

3

-

7

2

1

-

-

4

6

3

2

-

1

7

4

3

7

-

-

6

1

2

4

3

1

2

7

-

-

6

3

2

4

1

-

6

-

7

3

1

4

2

-

6

-

7

2

1

-

3

7

6

4

-

3

1

2

-

6

-

7

4

2

-

3

1

6

4

7

-


Switch fabrics

• Multipoint switching• Self-routing networks


13


Fabric implementation technologies

• Time division fabrics• Shared media• Shared memory

• Space division fabrics• Crossbar• Multi-stage constructions

• Buffering techniques


Time division fabrics

• Shared media• Bus architectures• Ring architectures

• Shared memory

14


Shared bus

Bus architecture• Switching in time domain, but time and space switching

implementations enabled• Easy to implement and low cost (cost index = N)

• One time-slot carried through the bus at a time=> limited throughput (multi-casting possible)=> low number of line interfaces=> limited scalability

Buscontrol

LineInterface #2

LineInterface #3

LineInterface #n...

LineInterface #1


Shared bus (cont.)

Bus architecture• Internally non-blocking implementations require high capacity

switching bus => throughput ≥ aggregate capacity of line interfaces

• Inherently a single stage switch, but TST-switching possible if line-cards support time-slot interchange

• Multiple-bus structures can be used to improve reliability andincrease throughput

LineInterface #2

LineInterface #3

LineInterface #n...Line

Interface #1Bus

control

Bus 2

Bus 1

15


Ring architectures

Ring architecture• Rings coarsely divided into source and destination release rings

– in source release (SR) rings only one switching operation inprogress at a time=> limited throughput (like a shared bus)

– destination release (DR) rings allow spatial reuse,i.e., multiple time-slots can be carried through the ring simultaneously=> improved throughput

• Switching in time domain, but time and spaceswitching implementations enabled

• Usually easy to implement and low cost(cost index = N)

• Scales better than a shared bus


Ring architectures (cont.)

Ring architecture• Internally non-blocking implementations

require that throughput of a ring bus ≥aggregate capacity of line interfaces

• Throughput can be improved by implementingparallel ring buses - control usually distributed=> MAC implementations may be difficult

• Multi-casting relatively easy to implement

• Inherently a single stage switch, but TST-switching possible if line-cards support time-slot interchange

• Multiple rings can be used to implementswitching networks

16


Ring architectures (cont.)

Dual ring architecture• Multiple rings used to improve throughput, decrease internal

blocking, improve scalability and increase reliability


Shared memory

Shared memory architecture• Switching in time domain, but time and space switching

implementations enabled

• Inherently a single stage switch, but allows TST-switching if line-cards support time-slot interchange

• Easy to implement and low cost (cost index = N)

BuffermemoryCPU

Bus

LineInterface #2

LineInterface #3

LineInterface #n...Line

Interface #1

17


Shared memory (cont.)

Shared memory architecture• Every time-slot carried twice through the bus

=> low throughput=> low number of line interfaces=> limited scalability

• Internally non-blocking if throughput of a switching bus andspeed of shared memory ≥ aggregate capacity of line interfaces

• Performance can be improved by dual bus architecture orreplacing the bus with a space switch (such as crossbar)


Shared memory (cont.)

Shared memory architecture• Dual-bus architecture improves throughput, decreases internal

blocking, improves scalability and increases reliability• Memory speed requirement equal to that of single bus solutions

LineInterface #2

LineInterface #3

LineInterface #n...

LineInterface #1

BuffermemoryCPU

Bus 1

Bus 2

18


Dimensioning example

A shared memory architecture, which uses a shared bus toconnect line interfaces to the memory, is used to implement aswitching equipment. The bus is 32 bits wide and bus clock is 150MHz. Three clock cycles are needed to transfer a 32 bit wordthrough the bus and 20 % of the bus capacity is used for otherthan switching purposes. How many E1 interfaces can besupported by the switch ? What is the required memory speed ?

Solution:

If the bus transfers an eight bit time-slot (of a 64 kbit/s PDH channel)across the bus at a time, a single bus solution can transfer0.8x(150/3) Mbytes/s = 40 Mbytes/s


Dimensioning example (cont.)

Solution (cont.):In a single bus solution, half of the bus capacity (20 Mbytes/s) is usedfor storing time-slots to memory and another half for reading time-slotsfrom memory => memory speed requirement is 1/(20 Mbytes/s) = 50 ns => during a 125 µs period (= duration of an E1 frame) the busswitches 125x20 bytes = 2500 time-slots and the number of supportedE1 links is 2500/32 ≈ 78

Throughput of the switching system can be increased by adding a 32 bitreceive-register to the shared switch memory block, which enables to transfer4 time-slots (in parallel) through the bus at a time. By doing so, the throughputof the bus gets four fold and the number of supported E1 links increases to312. Time-slots are still written one by one to the switch memory, and thus thememory speed requirement is 12.5 ns.

19


Space division fabrics

• Crossbar• Multi-stage constructions


Crossbar

Crossbar architecture• Inherently a space division switch

• Allows to build TST-switches if interfaces implement time-slotinterchange functionality

• Hard to implement large switches due to complicated controlschemes=> high cost (cost index = N2)

• Commercial high-speed NxN crossbar components enablemodular and relatively inexpensive fabric constructions, but stillcontrol of the switch is a problem

20


Crossbar (cont.)

Crossbar architecture• Inherently a strict-sense non-blocking fabric architecture• Possible to carry N time-slots through the switch at a time

=> high throughput=> possible to implement a large number of line interfaces=> scales well within the limits of available modular components=> scaling up means increase of cross-point count from NxN toto (N+k)x (N+k)

• Multi-casting easy to implementSwitch control


Crossbar (cont.)

C - connection control

Example implementation of a crossbar

c c c

c c c

c c c

AND

AND

AND

AND

AND

AND

AND

AND

AND

...

...

...

... ... ...

1

2

m

...

1 2 n...Outputs

Inpu

ts

21


Crossbar (cont.)

An 8x8 switch constructed of four 4x4 crossbar blocks

Notice that doubling of input/output count increases the number ofcrossbar components from one to four.


Multi-stage building blocks

• Multi-stage switches usually constructed of 2x2 switching blocks• Implemented usually in FPGAs (Field Programmable Gate Arrays)

and/or ASICs (Application Specific Integrated Circuit)• FPGA for experimental use and low volume production• ASICs for high volume production

• Batcher-banyan network most popular• Used to implement space division

switching

• Allows to build TST-switches ifinterfaces implement time-slotinterchange functionality

XIn1In2

Out1Out2

XIn3In4

Out1Out2

XIn5In6

Out1Out2

XIn7In8

Out1Out2

XIn1In2

Out1Out2

XIn1In2

Out3Out4

XIn1In2

Out5Out6

XIn1In2

Out7Out8

Switch networkcomposed of2x2 blocks

22


Multi-stage building blocks (cont.)

• Hard to implement large circuit switches due to complicated controlschemes (especially rearrangeable fabrics)=> high cost (cost index ∼∼ CNlog2N)

• Suitable for packet switching when self-routing functionality included

• Fixed duration time-slot implementations favored to obtain strict-sense non-blocking fabrics

• Possible to carry N time-slots through the switch at a time=> relatively high throughput=> scalable only if larger networks can be factored using smallerNxN components=> scaling up means increase of cross-point count from ∼∼ CNlog2Nto ∼∼ C(N+k)log2(N+k)

XIn1In2

Out1Out2


Problems with multi-stages

• Path search required

• Fast connection establishment implies need for fast control system => part of switching capacity is lost if control system is not fastenough

• Multi-cast is not self evident, because multi-cast complicates pathsearch and control scheme and increases blocking probability

• Multi-slot connections (i.e. several slots used for a particularconnection) complicate matters- especially if path delay is not constant, e.g., slots belonging to thesame connection may arrive to outputs in different order than theywere at the inputs- blocking increases

23


Trends in fabric technologies

• Memory technology getting faster and faster

• Current SRAM (Static Random Access Memory) technology allowseasy implementations of large PDH switches, e.g. full matrix for 8000E1 (2M) PDH circuits - bigger fabrics hardly needed in narrow bandnetworks=> in narrow band networks the trend over the last 10 years hasbeen to build full matrix fabrics based on shared memory

• However, when striving for broadband communications, memorybased switch fabrics do not scale to bandwidth needed=> multi-stage and crossbar switches have their change


Trends in fabric technologies (cont.)

• Multistage fabrics were “reinvented” at the advent of ATM- ATM suits perfectly for fixed length time-slot switching- self-routing and sorting applies for ATM cell routing- blocking and buffering causes headache=> in spite of huge research effort, there have been very few commercialmulti-stage fabrics available (mostly proprietary ASICs)

• Development of IC technologies, increased packing density (numberof gates/chip) and increased speed, have enabled crossbar fabricssuitable for high-speed switching applications (N = 2 … 64 and linerate 2.5 … 40 Gbit/s)- examples: Cx27399/Mindspeed, ETT1/Sierra, CE200/Internet Machinesand PI140xx/Agere

• Packet switching and advent of optical networking favors multi-stages and crossbars=> packet switching introduces a new problem - buffering

24


Technological tradeoffs in switch fabricdesign

• When trying to simplify path search and to speed up connectionestablishment=> bus speed increases (inside fabric)=> faster memory required => power consumption increases=> integration level of a cross-point product needs to be increased=> faster memory required, etc.

• If fast memory not available, use=> crossbar fabrics (for small switches)=> multistage fabrics (for large switches)- real switching capacity may be less than theoretical- minimization of cross-point count often pointless

Leve

l of c

ross

-po

int i

nteg

ratio

n

Memory speed

Bus

spe

ed

Complexity of path search


Electronic design problems

• Signal skew - caused by long signal lines with varying capacitive loadinside switch fabric and/or on circuit boards

• Mismatching line termination - caused by long signal lines combinedwith varying (high) bit rates

• Varying delay on bus lines - caused by differently routed bus lines (non-uniform capacitive load)

• Crosstalk - caused by electro-magnetic coupling of signals from adjacentsignal lines

• Power feeding and voltage-swing - incorrectly dimensioned powersource/lines cause non-uniform voltage and lack of adequate filtering causesfluctuation of voltage

• Mismatching timing signals - different line lengths from a centralizedtiming source cause phase shift and distributed timing may suffer from lack ofadequate synchronization

25


Some design limitations

• Speed of available components vs. required wire speed and slottime interval

• Component packing density and power consumption vs. heatingproblem

• Maximum practical fan-out vs. required size of fabric

• Required bus length inside switch fabric- long buses decrease internal speed of fabric- diagnostics get difficult

• IPR policy- whether company wants to use special components or moregeneral all-purpose components


Design optimization example

• An NxN switch fabric is to be designed and there are three alternativecrossbar components a, b and c available- a is an NaxNa fabric component- b is an NbxNb fabric component- c is an NcxNc fabric componentand Na<Nb<Nc≤N

• Component a has entered the market at time ta, b at time tb and c at time tc• Product development starts at tpd and the switch product should come in the

market at tm. Components are expected to be available when the productdevelopment starts => ta < tb < tc ≤ tpd < tm

• Price of a component develops with time and is generally given byP(t)=Cf(t) + D, where Cf(t) is a time dependent and D a constant part ofcomponent’s price

• Question: Which one of the three components to choose for constructing anNxN switch fabric ?

26


Design optimization example (cont.)

• As an example, let’s assume that price of each component is a function oftime and is given by P(t)=Ce-t/T+ D ,where C, D and T are component specific constants=> Pa(t)=Cae-t/Ta+ Da , Pb(t)=Cbe-t/Tb+ Db and Pc(t)=Cce-t/Tc+ Dc

• Number of alternative crossbar components needed to build an NxN switch=> Ka = ceil[N/Na]

2, Kb = ceil[N/Nb]2 , Kc = ceil[N/Nc]

2

• Alternative component costs as a function of time t=> Pa(t)=Cae-(t- ta)/Ta+ Ca

=> Pb(t)=Cbe-(t- tb)/Tb+ Cb

=> Pc(t)=Cce-(t- tc)/Tc+ Cc

• These functions can be used to draw price development curves to makecomparisons



Numerical example:• Let N = 64, Na = 16, Nb = 32, Nc = 64, Ta = Tb = Tc = 3 time units (years),

Ca = 20,Cb = 50, Cc = 100 and Da = 10, Db = 20, Dc = 40 price units (euros)

• Product development period is assumed to be 1 time unit (year) andtb = ta +1.5, tc = ta +3, tm = ta +4 => tpd = ta + 3

• Choosing that tpd = to = 0 => ta = t + 3, tb = t +1.5, tc = t, tm = t -1 (t ≥ tpd = 0 )

• Number of components needed Ka = 16, Kb = 4, Kc = 1

• Switch fabric component cost functions

=> Pa(t)=16[20e-(t+3)/3 + 10]=> Pb(t)=4[50e-(t+1.5)/3 + 20]=> Pc(t)=100e-(t)/3 + 40

27



• Although the price of component c is manifold compared to the price ofcomponent a or b, c turn out to be the cheapest alternative

• Another reason to choose c is that it probably stays longest in the marketgiving more time for the switch product

Numerical example (cont.) :

Component cost

0

20

40

60

80

100

120

140

160

0 1 2 3 4 5 6

Time

Cos

t

Pa(t) Pb(t) Pc(t)

Switch fabric cost

0

50

100

150

200

250

300

350

0 1 2 3 4 5 6

Time

Cos

t

Ta(t) Tb(t) Tc(t)

1


Switch Fabrics



Switch fabrics


• Sorting networks

• Fabric implementation technologies• Fault tolerance and reliability

2


Fabric implementation technologies

• Time division fabrics• Shared media• Shared memory

• Space division fabrics• Crossbar• Multi-stage constructions

• Buffering techniques


Buffering alternatives

• Input buffering

• Output buffering

• Central buffering

• Combinations

– input-output buffering

– central-output buffering

3


Input buffering

Buffer memories at the input interfaces

INPUTBUFFERING SWITCH

FABRIC


Input buffering (cont.)

• Pros• required memory access speed

- in FIFO and dual-port RAM solutions equal to incoming line rate- in one-port RAM solutions twice the incoming line rate

• Speed of switch fabric- multi-stages and crossbars operate at input wire speed- shared media fabrics operate at the aggregate speed of inputs

• low cost solution (due to low memory speed)

• Cons• FIFO type of buffering => HOL problem

• buffer size may be large (due to HOL)

• HOL avoided by having a buffer for each output at each input

4


Output buffering

Buffer memories at the output interfaces

OUTPUTBUFFERINGSWITCH

FABRIC


Output buffering (cont.)

• Pros• better throughput/delay performance than in input buffered

systems

• no HOL problem

• Cons• access speed of buffer memory

- in FIFO and dual-port RAM solutions N times the incoming line rate- in one-port RAM solutions N+1 times the incoming line rate

• high cost due to high memory speed requirement

• switch fabric operates at the aggregate speed of inputs(N x wire speed)

5


Central buffering

Buffer memory located between two switch fabrics- shared by all inputs/outputs- virtual buffer for each input or output

SWITCHFABRIC 1

CENTRALBUFFERING

SWITCHFABRIC 2


Central buffering (cont.)

• Pros• smaller buffer size requirement and lower average delay than in

input or output buffering

• HOL problem can be avoided

• Cons• speed of buffer memory

- in dual-port RAM solutions larger than N times the incoming line rate- in one-port RAM solutions larger than 2xN times the incoming line rate

• speed of switch fabric N x wire speed

• complicated buffer control

• high cost due to high memory speed requirement and controlcomplexity

6


Input-output buffering

Input-output buffering common in QoS aware switches/routers- inputs implement output specific buffers to avoid HOL- outputs implement dedicated buffers for different traffic classes- combined buffering distributes buffering complexity between inputs and outputs

INPUTBUFFERING

OUTPUTBUFFERINGSWITCH

FABRIC


Input-central buffering

INPUTBUFFERING

SWITCHFABRIC 1

CENTRALBUFFERING

SWITCHFABRIC 2

Input-central buffering used in QoS aware switches/routers- inputs implement output specific buffers to avoid HOL- central buffer implements dedicated buffers for different traffic classes foreach output

7


Summary of buffering techniques

Bufferingprinciple

Inputbuffering

Outputbuffering

Centralbuffering

Memoryspace

high

medium

low

Memoryspeed

slow(~input rate)

fast(~N x input rate)

fast(~N x input rate)

Memorycontrol

simple

simple

complicated

Queueingdelay

longest (due to HOL)

medium

shortest

Multi-castingcapabilities

extra logicneeded

supported

supportedbut complex


Priorities and buffering

• Separate buffer for each traffic class• A scheduler needed to control transmission data

• highest priority served first• longest queue served first• minimization of lost packets/cells

• Priority given to high quality traffic• low delay and delay variation traffic• low loss rate traffic• best customer traffic

• Scheduling principles• round robin• weighted round robin• fair queuing• weighted fair queuing• etc.

OUTPUT/CENTRALBUFFERING

CLASS 1

CLASS 2

CLASS 3

CLASS 4

8


Basic memory types for buffering

• FIFO (First-In-First-Out)• RAM (Random Access Memory)• Dual-port RAM


Basic memory types for buffering (cont.)

Read/WriteRAM

DUAL-PORT RAM

Write Read

FIFO

9


Switch fabrics




Fault tolerance and reliability

• Definitions• Fault tolerance of switching systems• Modeling of tolerance and reliability

10


Definitions

• Failure, malfunction - is deviation from theintended/specified performance of a system

• Fault - is such a state of a device or a programwhich can lead to a failure

• Error - is an incorrect response of a program ormodule. An error is a indication that the module inquestion may be faulty, the module has receivedwrong input or it has been misused. An error canlead to a failure if the system is not tolerant to thissort of an error. A fault can exist without any errortaking place.


Fault tolerance

• Fault tolerance is the ability of a system to continueits intended performance in spite of a fault or faults

• A switching system is an example of a faulttolerant system

• Fault tolerance always requires redundancy of somesort

11


Categorization of faults

• Duration based• permanent or stuck-at (stuck at zero or stuck at one)• intermittent - fault requires repair actions, but its impact is not

always observable

• transient - fault can be observed for a short period of time anddisappears without repair

• Observable or latent (hidden)• Based on the scope of the impact (serious - less

serious)


Graceful degradation

• Capability of a system to continue its functionsunder one or more faults, but on a reduced level ofperformance

• For example• in some RAID (Redundant Array Inexpensive Disks)

configurations, write speed drops in case of a disk fault, butcontinues on a lower level of performance even while the faulthas not been repaired

12


Reliability and availability

• Reliability R(t) - probability that a system does not failwithin time t under the condition that it was functioningcorrectly at t = 0

• for all known man-made systems R(t) → → 0 when t → → ∞∞• Availability A(t) - probability that a system will function

correctly at time t• for a system that can be repaired A(t) approaches some value

asymptotically during the useful lifetime of the system


Repairable system

• Maintainability M(t) - probability that a system isreturned to its correct functioning state during time tunder the condition that it was faulty at time t = 0

13


MTTF, MTTR and MTBF

• MTTF (Mean-Time-To-Failure) - expected value of thetime duration from the present to the next failure

• MTTR (Mean-Time-To-Repair) - expected value of thetime duration from a fault until the system has beenrestored into a correct functioning state

• MTBF (Mean-Time-Between-Failures) - expected valueof the time duration from occurrence of a fault until thenext occurrence of a fault

• MTBF = MTTR + MTTR


High availability of a switching system

• High availability of a switching system is obtained bymaintenance software

Detection of errors and

faults

Supervision

Fault analysis and

pinpointing

Alarm system

Recovery - elimination of faults

Recovery

Faultlocation

Diagnostics

• In a unit under normal working load

• HW implementation => fast

• SW implementation => detection delay

• Often a rulebased system

Utilizes• redundancy• switch-overs

- active <=> standby• restarts

- a single program- a preprocessor- a single main processor- whole system- fall back to previous SW package

• In a unit temporarilywithout normalload

Maintenance software is one of themost important software sub-systemsin a switching system in parallel withcall/connection control and charging

14


Main types of redundancy

• Hardware redundancy• duplication (1+1) - need for “self-checking”-recovery blocks that

detect their own faults• n+r -principle (n active units and r standby units)

• Software redundancy• required always in telecom systems

• Information redundancy• parity bits, block codes, etc.

• Time redundancy• delayed re-execution of transactions


Modeling of reliability

• Combinatorial models• Markov analysis• Other modeling techniques (not covered here)

- Fault tree analysis- Reliability block diagrams- Monte Carlo simulation

15


Combinatorial reliability

S1 S2 Sn

S

S1

S2

Sn

S

• A serial system S functions if and only if allits parts Si (1≤i≤n) function

=> Rs = ΠΠ Ri and Fs = (1- Rs)

• Failures in sub-systems are supposed to beindependent

n

i=1

• A parallel (replicated) system fails if all its sub-systems fail

=> Fs = ΠΠ (1-Ri) and Rs = 1- Fs = 1- ΠΠ (1-Ri)

• Reliability of a duplicated system (Ri = R) isRs = 1- (1-R)2

n

i=1

n

i=1


Combinatorial reliability example 1

• Calculate reliability Rs and failure probability Fs of system Sgiven that failures in sub-systems Si are independent and forsome time interval it holds thatR1 = 0.90, R2 = 0.95 and R3 = R4 = 0.80

=> Rs = ΠΠ Ri = R1 x R2 x R3-4

=> R3-4 = 1- ΠΠ (1-Ri) = 1- (1- R3)(1- R4)

=> Rs = R1 x R2 x [1- (1- R3)(1- R4)]

=> Fs = 1- Rs = 1 - R1 x R2 x [1- (1- R3)(1- R4)]

=> Rs = 0.82 and Fs = 0.18

S1 S2

SS3

S4

S3-4

16


Combinatorial reliability (cont.)

S1

S2

Sn

S

m/n

• A load sharing system functions if m of the total ofn sub-systems function

• If failures in sub-systems Si are independent thenprobability that the system fails is

P(fails) = P(k<<m)and probability that it functions is

P(functioning) = P(k≥≥m) = 1- P(k<<m)where k is the number of functioning sub-systems

P(k≥≥m) = Σ Σ P(k==i) and P(k<<m) = Σ Σ P(k==i)n

i=m

m-1

i=0


Combinatorial reliability example 2

• As an example, suppose we have a system having m=2 and n=4and each of the four sub-systems have a different R, i.e. R1, R2, R3and R4, and failures in sub-systems Si are independent

• Probability that the system fails is

P(fails) = P(k<<2) = ΣΣ P(k==i) = P(k==0) + P(k==1)

• P(k=0) and P(k=1) can be derived to beP(k==0) = (1- R1)(1- R2)(1- R3)(1- R4)P(k==1) = R1(1- R2)(1- R3)(1- R4) + (1- R1)R2(1- R3)(1- R4) + (1- R1)(1- R2) R3(1- R4) + (1- R1) (1- R2)(1- R3) R4

• If R1=0.9 ,R2,=0.95 ,R3 =0.85 and R4 =0.8 then Rs = 0.994 and Fs = 0.0058

1

i=0

S1

S2

S4

S

2/4S3

17


Combinatorial reliability (cont.)

• If failures in sub-systems Si of an m/n systemare independent and Ri = R for all i∈[1,n]then the system is a Bernoulli system andbinomial distribution applies

=> Rs = ΣΣ ( )Rk(1-R)n-k

• For a system of m/n = 2/3

=> R2/3 = ΣΣ −−−− Rk(1-R)3-k = 3R2 - 2R3

If for example R = 0.9 => R2/3 = 0.972

S1

S2

Sn

S

m/n

nk

3!k!(3-k)!

3

k=2

n

k=m


Computing MTTF

• MTTF = ∫ ∫ R(t)dt - valid for any reliability distribution

• Single component with a constant failure rate (CFR) λλ- R(t) = e-λλt

- MTTF = 1/λλ• Serial systems with n CFR components

- Rs(t) = R1(t) x R2(t) x ... x Rn(t) = e- (λλ1 + λλ2 + ... + λλn)t = e- λλst

- λλs= λλ1 + λλ2 + ... + λλn

• MTTFs = 1/ λλs

• 1/MTTFs = 1/MTTF1 + 1/MTTF2 + ... + 1/MTTFn

∞∞

0

18


Telecom exchange reliability fromsubscriber’s point of view

Line-card

n-1/n

Subscribermodulecontrol

CentralizedfunctionsSubscriber

callcontrol

Exchangeterminal

CCS7 signaling processors• (n-1)/n operational processors

for call setup• chosen processor functions

during a call

Premature release requirement P ≤ 2x10-5 applied


Failure intensity

• Unit of failure intensity λλ is defined to be[λλ]] = fit = number of faults /109 h

• Failure intensities for replaceable plug-in-units varies in therange 0.1 - 10 kfit

• Example:• if failure intensity of a line-card in an exchange is 2 kfit, what

is its MTTF ?

MTTF = 1/λλ = = = 58 years109 h2000

1 000 000 h2x24x360

19


Reliability modeling using Markov chains

Markov chains• A system is modeled as a set of states of transitions

• Each state corresponds to fulfillment of a set of conditions and eachtransition corresponds to an event in a system that changes fromone state to another

• By using this method it is possible to find reliability behavior of acomplex system having a number of states and non-independentfailure modes

State 1 State 2


Markov chain modeling

• A set of states of transitions leads to a group of linear differentialequations

• For a given modeling goal it is essential to choose a minimal set ofstates for equations to be easily solved

• By setting the derivatives of the probabilities to zero an asymptoticstate is obtained if such exists

λλ = failure intensityµµ = repair intensity (repair time is exponentially distributed)

Pi = probability of state i, e.g. P0 = R(t) and P1 = F(t),

P0 P1

λλ

µµ

20


Markov chain modeling (cont.)

• Probabilities (πi) of the states and transition rates (λij) between thestates are tied together with the following formula

0==ΛΛππ

[[ ]]nππππππππ �21==

(( ))(( ))

(( ))

++++−−++++−−

++++−−

==ΛΛ��

��

��

��

32313231

23232121

13121312

λλλλλλλλλλλλλλλλλλλλλλλλ

where



Example

0==ΛΛππ [[ ]]nππππππππ �21==S3

λλ12

S2S1 λλ21

λλ13

λλ31

λλ32λλ23

(( ))(( ))

(( ))

++−−++−−

++−−==ΛΛ

32313231

23232121

13121312


(( ))(( ))

(( ))

==++−−++==++++−−==++++++−−

0

0

0

33231232131

32322321121

31321211312

ππλλλλππλλππλλππλλππλλλλππλλππλλππλλππλλλλ

and

21


Birth-death process

Birth-death process is a special case of continuous-time Markovchain, which models the size of population that increases by 1 (birth)or decreases by one (death).

S0

λλ0

µµ1

S1

λλ1

µµ2

S2

λλ2

µµ3

S3

λλ3

µµ4

...

=>

Balance equations:

- State S0

- State S1

- State Sk

=>

=>

λλ ππ λλ ππ0 0 1 1==

(( ))λλ µµ ππ λλ ππ λλ ππ1 1 1 0 0 2 2++ == ++

(( ))λλ µµ ππ λλ ππ λλ ππk k k k k k k−− −− −− −− −−++ == ++

1 1 1 2 2

ππ λλµµ

ππ1

0

1

0==

ππ λλ λλµµ µµ

ππ21 0

2 1

0==

ππ λλ λλ λλµµ µµ µµ

ππk

k

k

== −−1 1 0

2 1

0

�

�


Birth-death process (cont.)

Sk

λλk

µµk+1

Sk+1

=>

ππ λλµµ

λλµµ

λλµµ

ππ ρρ ρρ ρρ ππk

k

k

k==

==−−

−−1 1

2

0

1

0 1 1 1 0� � ρρ λλ

µµkk

k

==++1

ππ kk ==

∞∞

∑∑ ==0

1

(k=1, 2, 3, …)where

Substituting these expressions for ππk into yields


ππ01 1 0

2 10

11++ ==−−

==

∞∞

∑∑ k

kk

�

�=> ππ λλ λλ λλ

µµ µµ µµ01 1 0

2 11

1 1++

==−−

==

∞∞

∑∑ k

kk

�

�

11

0

1 1 0

2 11ππλλ λλ λλµµ µµ µµ

== ++

−−

==

∞∞

∑∑ k

kk

�

�


ππkk

k

== −−1 1 0

2 10

�

�

=>

(k=1, 2, 3, …)

22


Example of birth-death process

A switching system has two control computer, one on-line and onestandby. The time interval between computer failures is exponentiallydistributed with mean tf . In case of a failure, the standby computerreplaces the failed one.A single repair facility exist and repair times are exponentiallydistributed with mean tr .What fraction of time the system is out of use, i.e., both computershaving failed?

The problem can be solved by using a three state birth-death model.

S0

λλ0

µµ1

S1

λλ1

µµ2

S2 S0

11//tr

11//tf

S1

11//tr

11//tf

S2=>


Example of birth-death process (cont.)

If tr/tf = 10 , i.e. the average repair time is 10 % of the averagetime between failures, then ππ0 =0.009009 and both computer willbe out of service 0.9 % of the time.

S0 - both computer operableS1 - one computer failedS2 - both computer failed

11

1

1

1

10

2

ππ== ++ ++

t

t

t

t

r

f

r

f

ππ 0

2

2 2==

++ ++t

t t t tr

r r f f

=>

(probability that bothcomputers have failed)

23


Additional reading of Markov chainmodeling



Markov chain modeling

A continuous-time Markov Chain is a stochastic process {X(t): t ≥≥0}

• X(t) can have values is S={0,1,2,3,...}• Each time the process enters a state i, the amount of time it spends

in that state before making a transition to another state has anexponential distribution with mean 1/λλi

• When leaving state i, the process moves to a state j with probabilitypij where pii=0

• The next state to be visited after i is independent of the length oftime spend in state i

S0

λλ0

µµ1

S1

λλ1

µµ2

S2

λλ2

µµ3

S3

λλ3

µµ4

...

24



Transition probabilities

Continuous at t=0, with

Transition matrix is a function of time

{{ }}isXjstXPtpij ====++== )()()(

≠≠==

==→→ jiif

jiiftpij

t 0

1)(lim

0

==

��

� �)(

)()(

)( 21

1211

tp

tptp

tP



Transition intensity:(rate at which the process leavesstate j when it is in state j)

(transition rate into state j whenthe process in is state i)

)0()( jjj pdtd

t −−==λλ

ijiijij ppdt

dt λλλλ ==== )0()(

The process, starting in state i, spends an amount of time in thatstate having exponential distribution with rate λλi . It then moves tostate j with probability

jipi

ijij ,∀∀==

λλλλ ∑∑

∑∑∑∑∑∑

==

==

====

==⇒⇒======n

jiji

i

n

jijn

j i

ijn

jijp

1

1

11

1 λλλλλλ

λλ

λλλλ

25



Chapman-Kolmogorov equations:

Since p(t) is a continuous function

)()0()0()( 2totpdtd

ptp ijijij ∆∆++∆∆++==∆∆

0,

,)()()(

≥≥∀∀∈∈∀∀

==++ ∑∑∈∈ ts

Sjisptpstp

Skkjikij

We have defined => )0()( ijij pdt

dt ==λλ

For i≠≠j:

For i=j:

ttotptp ijijijij ∆∆≈≈∆∆++∆∆++==∆∆ λλλλ )()0()( 2

ttotptp iiiiiiii ∆∆++≈≈∆∆++∆∆++==∆∆ λλλλ 1)()0()( 2

(for small ∆t)

(for small ∆t)



From Chapman-Kolmogorov equations:

∑∑∑∑≠≠

∆∆++∆∆==∆∆==∆∆++jk

kjikjjijk

kjikij tptptptptptpttp )()()()()()()(

Taking the limit as ∆t → 0

[[ ]] [[ ]]∑∑≠≠

∆∆++∆∆++∆∆++∆∆++==jk

kjikjjij tottptottp )()()(1)( 22 λλλλ

)()()()()( 2totpttptpttpk

ikk

kjikijij ∆∆

++∆∆

++==∆∆++ ∑∑∑∑ λλ

tto

tptpt

tpttp

kik

kkjik

ijij

∆∆∆∆

++==

∆∆−−∆∆++ ∑∑∑∑ )(

)()()()( 2

λλ

jitptpdtd

kjk

ikij ,)()( ∀∀== ∑∑ λλ

26



The process is described by the system of differential equations:

jitptpdtd

kjk

ikij ,)()( ∀∀== ∑∑ λλ

which can be given in the form

jitPtPdt

d,)()( ∀∀ΛΛ== titp

jij ,1)( ∀∀==∑∑

0)1()( ====∑∑ dtd

tpdtd

jij

0)( ==∑∑j

ij tpdtd

0==∑∑j

ijλλ The sum of of each row of ΛΛ is zero !



Example

(( ))(( ))

(( ))

++−−++−−

++−−==ΛΛ

32313231

23232121

13121312


The sum of of each row of ΛΛ must be zero !

S3

λλ12

S2S1 λλ21

λλ13

λλ31

λλ32λλ23

27



Steady state probabilities

Must be non-negative and must satisfy 11

==∑∑==

n

iiππ

jijttp ππ==

∞∞→→)(lim (Independent of initial state i)

In case of continuous-time Markov chains balance equationused to determine ππ.For each state i, the rate at which the system leaves the statemust equal to the rate at which the system enters the state

=> llikkijjiii ππλλππλλππλλππλλ ++++==k

j

i

l



Balance equation

Steady state distribution is computed by solving this systemof equations

iik

kkiiij

ij ∀∀==

∑∑∑∑≠≠≠≠

ππλλππλλ

iik

kkiiij

ij ∀∀==

∑∑∑∑≠≠≠≠

ππλλππλλ

11

==∑∑==

n

iiππ

28



An alternative derivation of the steady-state conditions begins withthe differential equation describing the process:

Suppose that we take the limit of each side as t →→ ∞∞

jitptpdtd

kjk

ikij ,)()( ∀∀== ∑∑ λλ

(( )) (( ))∑∑∞∞→→∞∞→→==

kkjik

tij

ttptp

dtd λλlimlim

(( )) (( ))∑∑ ∞∞→→∞∞→→==

kkjik

tij

ttptp

dtd λλlimlim

0==∑∑k

kjkλλππ

=>

=>

=> i.e. ππΛΛ=0



Example

0==ΛΛππ [[ ]]nππππππππ �21==S3

λλ12

S2S1 λλ21

λλ13

λλ31

λλ32λλ23

(( ))(( ))

(( ))

++−−++−−

++−−==ΛΛ

32313231

23232121

13121312


and

(( ))(( ))

(( ))

==++−−++==++++−−==++++++−−

0

0

0

33231223113

33222321112

33122111312

ππλλλλππλλππλλππλλππλλλλππλλππλλππλλππλλλλ

1


PDH Switches



PDH switches

• General structure of telecom exchange• Timing and synchronization• Dimensioning example

2


PDH exchange

• Digital telephone exchanges are called SPC (Stored ProgramControl) exchanges

• controlled by software, which is stored in a computer or agroup of computers (microprocessors)

• programs contain the actual intelligence to perform controlfunctions

• software divided into well-defined blocks - modularity makesthe system less complicated to maintain and expand

• Main building blocks

• subscriber interfaces and trunk interfaces• switch fabric

• switch/call control


Basic blocks of a PDH exchange

…

LOCALLOOP

SUB

SCR

IBER

INTE

RFA

CE

SWITCHFABRIC

TRU

NK

INTE

RFA

CE

SWITCH CONTROL

…

3


Switch control

• Centralized• all control actions needed to set up/tear down a connection

are executed in a central processing unit

• processing work normally shared by a number of processors

• hierarchical or non-hierarchical processor architecture• Distributed

• control functions are shared by a number of processing unitsthat are more or less independent of one another

• switching device divided into a number of switching parts andeach of them has a control processor


Switch control (cont.)

… …

ControlprocessorControl

processor

RP

Centralprocessor

RP…

……

Centralized non-hierarchicalprocessor system

Centralized hierarchicalprocessor system

Control units usually doubled or tripledRP - Regional Processor

4



Distributed controlwith independent switching parts

Switching partwith controlprocessor…

Switching partwith controlprocessor…

Switching partwith controlprocessor …

Switching partwith controlprocessor …


Example construction of a PDHexchange

…

NT

SWITCHFABRIC

CONTROLPROCESSOR

…

ET

TRUNKINTERFACES

ET

AUX

SUBSCRIBERINTERFACES

NT

…

AUX - Auxiliary equipmentAT - Exchange TerminalNT - Network Terminal

ADMINISTRATIONCOMPUTER

SWITCHING &CALL CONTROL

5


Example of call control processing

DX200 / Nokia

CCSUCCSULSULSURURUSSUSSU RU LSU CCSUSSU

STUSTUCMCMMMM CM STU

CCSU - Common Channel Signaling UnitCM - Central MemoryLSU - Line Signaling UnitM - Marker

RU - Registering UnitSSU - Subscriber Stage UnitSTU - Statistics Unit


Hierarchical control software

Administrationprograms

Call controlprograms

Signaling messageprocessing

Software systems in the control part:- signaling and call control- charging and statistics- maintenance software

Control of connections:- calls should not be directed to faulty destinations- faulty connections should be cleared- detected faulty connections must be reported to far-end if possible

6


Switching part

• Main task of switching part is to connect an incoming time-slot toan outgoing one - unit responsible for this function is called agroup switch

• Control system assigns incoming and outgoing time-slot, whichare reserved by signaling, on associated physical links=> need for time and space switching

Group switch

2

2

1

1

A

B


Group switch implementations

• Group switch can be based on a space or time switch fabric• Memory based time switch fabrics are the most common ones

- flexible constructions- due to advances in IC technology suitable also for large switch fabrics

123

...


...k

m

Switchmemory

123

n

Controlmemory

...

...j (k)

123m …


12jn … …


Cyclic read

writ

ead

dres

s (3

)

read

/writ

ead

dres

s (j)read

address (k)

Cyclic write

7


Subscriber connections

…

Remotesubscriber

switch

……

Subscribermux

Groupswitch

Local exchange

…

Subscriberswitch


Subscriber and trunk interface

• Subscriber interface• on-hook/off-hook detection, reception of dialed digits• check of subscriber line, power supply for subscriber line

• physical signal reception/transmission, A/D-conversion

• concentration• Trunk interface

• timing and synchronization (bit and octet level) to line/clocksignal coming from an exchange of higher level of hierarchy

• frame alignment/frame generation

• multiplexing/demultiplexing

8


Example of telephone network hierarchy

Localexchange

Tandemlevel

Regionaltransit level

Nationaltransit level

Internationaltransit level


Network synchronization

Need for synchronization• Today’s digital telecom networks are combination of PDH and

SDH technologies, i.e. TDM and TDMA utilized

• These techniques require that time and timing in the network canbe controlled, e.g., when traffic is added or dropped from a bitstream in an optical fiber or to/from a radio-transmitted signal

• The purpose of network synchronization is to enable the networknodes to operate with the same frequency stability and/orabsolute time

• Network synchronism is normally obtained by applying themaster-slave timing principle

9


Network synchronization

Methods for network synchronization• Distribute the clock over special synchronization links

- offers best integrity, independent of technological development andarchitecture of the network

• Distribute the clock by utilizing traffic links- most frequently used (master-slave network superimposed on the trafficnetwork)

• Use an independent clock in each node- expensive method, but standard solution in international exchanges

• Use an international navigation system in each node- GPS (Global Positioning System) deployed increasingly- independent of technological development and architecture of network

• Combine some of the above methods


Master-slave synchronization overtransport network

Localexchange level

Transit level

International level

Remotesubscriber switch

∼∼∼∼

High-stabilityreference clocks

ITU-T Recommendations G.810, G.811, G.812, G.812, G.823

10


SDH synchronization networkreference chain

• As the number of clocks in tandem increases, synchronization signal isincreasingly degraded

• To maintain clock quality it is important to specify limit to the number ofcascaded clocks and set limit on degradation of the synchronization signal

• Reference chain consists of K SSUs each linked with N SECs• Provisionally K and N have been set to be K=10 and N=20

- total number of SECs has been limited to 60

PRC SSU SSU

N x SEC N x SEC N x SEC1st

SSU

N x SEC2nd K-th

PRC - Primary Reference Clock (accuracy 10-11)SEC - SDH Equipment Clock (accuracy 10-9)SSU - Synchronization Supply Unit (accuracy 10-6)


PDH synchronization referenceconnection

• End-to-end timing requirements are set for the reference connection• Link timing errors are additive on the end-to-end connection• By synchronizing the national network at both ends, timing errors can be

reduced compared to totally plesiochronous (separate clock in eachswitch) operation

• International connections mostly plesiochronous

LE - Local ExchangePC - Primary ExchangeSC - Secondary Exchange

X

LEX

PCX

SCX

TCX

ISC... X

ISCX

ISCX

TCX

SCX

PCX

LE

Nation network Nation networkInternationalnetworkLocal Local

27 500 km

TC - Tertiary ExchangeISC - International Switching Center

X Digital exchange Digital link

11


Types of timing variation

• Frequency offset- steady-state timing difference - causes buffer overflows

• Periodic timing differences- jitter (periodic variation > 10 Hz)- wander (periodic variation < 10 Hz)

• Random frequency variation cased byelectronic noise in phase-locked loops of timing devices andrecovery systems- transients caused by switching from one clock source to another

• Timing variation causes- slips (= loss of a frame or duplication of a frame) in PDH systems- pointer adjustments in SDH systems => payload jitter=> data errors


Visualization of jitter and wander

Jitte

r am

plitu

de

t

12


Timing variation measures

• Time interval error (TIE)- difference between the phase of a timing signal and phase of areference (master clock) timing signal (given in ns)

• Maximum time interval error (MTIE)- maximum value of TIE during a measurement period

• Maximum relative time interval error (MRTIE)- underlying frequency offset subtracted from MTIE

• Time deviation (TDEV)- average standard deviation calculated from TIE for varying windowsizes


Maximum time interval error

• the maximum of peak-to-peak difference in timing signal delayduring a measurement period as compared to an ideal timing signal

Measurement period ( S )

MTIE

timin

g de

lay

com

pare

d to

idea

l sig

nal

t

13


MTIE limits for PRC, SSU and SEC

Clocksource

PRC

SSU

SEC

Time-slotinterval [ns]

25 ns0.3t ns300 ns

0.01t ns

25 ns10t ns

2000 ns433t0.2 + 0.01t ns

250 ns100t ns2000 ns

433t0.2 + 0.01t ns


0.1 < t < 83 s83 < t < 1000 s

1000 < t < 30 000 st > 30 000 s

0.1 < t < 2.5 s2.5 < t < 200 s

200 < t < 2 000 st > 2 000 s

0.1 < t < 2.5 s2.5 < t < 20 s

20 < t < 2 000 st > 2 000 s

ETS 300 462-3


Occurrence of slips

Average frequency of slips

≤≤ 5 slips / 24h

5 slips/ 24 h …. 30 slips/ 1h

≤≤ 10 slips / 1h

Share of time during one year

98.90 %

< 1 %

< 0.1 %

• Slips occur on connections whose timing differs from the timing signal used bythe exchange

• If both ends of a connection are internally synchronized to a PRC signal,theoretically slips occur no more frequently than once in 72 days

• In a reference connection a slip occurs theoretically once in 72/12 = 6 daysor if national segments are synchronized once in 720/4 = 18 days

• Slip requirement on an end-to-end connection is looser:

14


Slip calculation example

Solution:• Timing accuracy of a PRC clock is 10-11

• Let the frequencies of the two ends be f1 and f2• In the worst case, these frequencies deviate from the reference

clock fo by 10-11x fo and those deviations are to different directions

• Let the frequencies be f1 = (1+ 10-11) fo and f2 = (1- 10-11) fo• Duration of bits in these networks are T1= 1/ f1 and T2= 1/ f2

Show that two networks with single frame buffers and timed fromseparate PRCs would see a maximum slip rate of one slip every72 days


Slip calculation example (cont.)

Solution (cont.):• During one bit interval, the timing difference is T1- T2 and after

some N bits the difference exceeds a frame length of 125 µs and aslip occurs => NT1- T2 = 125x10-9

=> N = 125x10-9 /[(1/ f1 -1/ f2) ]

• Inserting f1 = (1+ 10-11) fo and f2 = (1- 10-11) fo into the above equation,we get => N = 125x10-9 fo (1- 10-22)/(2x 10-11)

• Multiplying N by the duration (Tb) of one bit , we get the time (Tslip)between slips

• In case of E1 links, fo= 2.048x106/s and Tb = 488 ns. Dividing theobtained Tslip by 60 (s), then by 60 (min) and finally by 24 (h) we getthe average time interval between successive slips to be 72.3 days

15


Synchronization of a switch

Synchronization sub-system in an exchange• Supports both plesiochronous and slave mode• Clock accuracy is chosen based on the location of the exchange in

the synchronization hierarchy- accuracy decreases towards the leaves of the synchronization tree

• Synchronizes itself automatically to several PCM signals andchooses the most suitable of them (primary, secondary, etc.)

• Implements a timing control algorithm to eliminate- instantaneous timing differences caused by the transmissionnetwork (e.g. switchovers - automatic replacement of faultyequipment with redundant ones)- jitter

• Follows smoothly incoming synchronization signal


Synchronization of a switch (cont.)

Exchange follows the synchronization signal• Relative error used to set requirements

- maximum relative time interval error MRTIE≤1000 ns (S≥ 100s)• Requirement implies how well the exchange must follow the

synchronization signal when the input is practically error free

• When none of the synchronization inputs is good enough, theexchange clock automatically switches over to plesiochronousoperation

• In plesiochronous mode MRTIE≤ (aS +0.5bS2 + c) ns

• Timing system monitors all incoming clock signals and when aquality signal is detected, the system switches over back to slavemode (either manually by an operator command or automatically)

16


Stability of an exchange clock

• Clock stability is measured by aging (=b)- temperature stabilized aging in the order of n x 10-10/day

• MRTIE ≤ (aS +0.5bS2 + c) ns- S = measurement period- a = accuracy of the initial setting of the clock- b = clock stability (measured by aging)- c = constant

a

b

c

Transit node clock0.5 - corresponds to an initial

frequency shift of 5x10-10

1.16x10-5 - corresponds

to aging of 10-9/days

1000

Local node clock10.0 - corresponds to an

initial frequency shift of 1x10-8

2.3x10 -4 - corresponds to aging of 2x10-8

1000


MRTIE in an exchange(plesiochronous mode)

Duration of a time-slot in a PCM-signal is 3.9 µs and duration of a bit is 488 ns

1E+0

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

1E+8

1E+9

1E+10

1E+2 1E+3 1E+4 1E+5 1E+6 1E+7

MR

TIE

ns

Observation time (S)

Transit exchange

Local exchange

17


Example of SRAM based PDHswitch fabric

Time-interchangebased 64 PCM switch

4xE1

2M 8M

4xE2 4xE3

34M 140M

…E4

=>

64 x

E1

dem

ux

64 x

E1

=> E

4 m

ux…


Example of SRAM based PDHswitch fabric (cont.)

Memory size and speed requirement:• Switch memory (SM) and control memory (CM) both are single chip

solutions• Size of both SM and CM ≥ 64x32 octets = 2048 octets

• Number of SM write and read cycles during a frame interval (125 µs)is 2x64x32 = 4096

• Access cycle of SM should be ≤ 125 µs/4096 = 30,5 ns

• Number of CM write and read cycles during a frame interval (125 µs)is 1x64x32 = 2048

• Access cycle of CM should be ≤ 125 µs/2048 = 61 ns

18


PDH bit rates and related bit/octet times

Hierarchylevel

E1/2M

E2/8M

E3/34M


3906

947

233

Bit interval[ns]

488

118

29

E4/140M 57.4 7.2

• When time-slots turn into parallel form (8 bits in parallel) memoryspeed requirement decreased by a factor of 8

• Present day memory technology enables up to 256 PDH E1 signalsto be written to and read from a SRAM memory on wire speed


Properties of full matrix switches

Pros• strict-sense non-blocking• no path search - a connection can always be written into the

control memory if requested output is idle• multi-cast capability• constant delay• multi-slot connections possible

Cons• switch and control memory both increase in square of the number

of input/outputs• broadband - required memory speed may not be available

19


Make full use of available memory speed

• At the time of design, select components that- give adequate performance- will stay on the market long enough- are not too expensive (often price limits the use of the fastest components)

• To make full use of available memory speed, buses must be fast enough• When increasing required memory speed, practical bus length decreases

(proportional to inverse of speed)

Length of a bus

Bus bit-rate

5 ns 20 ns

$/SRAM

DRAM: 40 ... 70 ns

Bus Bit-rate

Memory speed


Power consumption - avoid heatingproblem

• Power consumption of an output gate is a function ofinputs connected to it (increased number of inputs => increased powerconsumption)- bit rate/clock frequency (higher bit rate => increased power consumption- bus length (long buses inside switch fabric => increased power consumptionand decreased fan-out)

• Increase in power consumption => heating problem• Power consumption and heating problem can be reduced, e.g. by using lower

voltage components (higher resolution receivers)

Receiver’s resolution

Pow

er

Bus length

Fan-

out

Pow

er

Fan-out

20


Logical structure of a full matrix switch

1

2

3

N

1

2

3

N

. . .

. . .

Feasible SMwith availablecomponents



. . .

Replication of inputs Multiplexed inputs

N = 2n


Example of a matrix switch (DX200)

Read32x64=2k

Address

8

0

7 ...

16Wr

Fan-out=32

Control & switching memory card

...

0 63

S/P

Bus buffer

0 63

S/P

0 63

S/P

0 63

S/P

P/S

0

63

CMSM SM SMSM

P/S

0

63

CMSM SM SMSM

P/S

0

63

CMSM SM SMSM

P/S

0

63

CMSM SM SMSM

21


Example of a matrix switch (cont.)

• S/P (Serial/Parallel conversion) - incoming time-slots are turned intoparallel form to reduce the speed on internal buses

• P/S (Parallel/Serial conversion) - parallel form output signals convertedback to serial form

• 64 PCM S/P-P/S pairs implemented on one card, which is practicalbecause PCMs are bi-directional

• One switch block can serve max 4 S/P-P/S pairs - which is chosenbased on required capacity (64, 128, 192 or 256 E1/PCMs)

• One S/P+P/S pair feeds max 8 parallel switch blocks - chosen based onthe required capacity in the installation (n * 256 E1/PCM’s)

• Max size of the example DX200-system fabric is 2048 E1/PCM’s

• Currently, a bigger matrix ( 8K E1/PCM’s) is available, slightly differentSRAMs are needed, but principle is similar



• A time-slot is forwarded from an S/P to all parallel switch blocksand in each switch block it is written to all SMs along the verticalbus

• A single time-slot replicated into max 4x8=32 locations

• Data in CMs used to store a time-slot in correct positions in SMs

• CM also includes data to read a correct time-slot to be forwardedto each output time-slot on each output E1 link

• CM includes a 16-bit pointer to a time-slot to be read– 2 bits of CM content point to an SM chip and– 5 + 6 = 11 bits point to a memory location on an SM chip– remaining 3 bits point to (source) switch block

22



• Number of time-slots to be switched during a frame (125 µs): - 8x4x64x32 = 65 536 time-slots (= 64 kbytes)

• Each time-slot stored in 4 SMs in each of the 8 switch blocks=> max size of switch memory 8x4x65 536 = 2097152 (= 2 Mbytes)

• Every 32nd memory location is read from SM in a max size switch=> average memory speed requirement < 31 ns (less than theworst case requirement 64x32 write and 64x32 read operationsduring a 125 µs period)

• Control memory is composed of 4x4 control memory banks in eachof the 8 switch blocks and each memory bank includes 2.048kwords (word= 2 bytes) for write and 2.048 kwords for read control,i.e. max CM size is 8x4x4x8kbytes = 1048576 bytes (= 1 Mbytes)


Growth of matrix

256 PCM

512 PCM


ATM Switches



ATM switches

• General of ATM switching• Structure of an ATM switch• Example switch implementations

• Knockout switch• Abacus

• Dimensioning example


General of ATM switching

• ATM switches correspond to layer 2 in the OSI reference model and this layer can roughly be divided into a higher and lower layer:

– higher layer = ATM Adaptation Layer (AAL)

– lower layer = ATM layer

Layer 1


Layer 1


Layer 1

Layer 2 (L)

Layer 2 (H)






Layer 2 (H)

Layer 1


Layer 1


Layer 1

Layer 2 (L)

Layer 2 (H)






Layer 2 (H)


ATM Adaptation Layer

• AAL offers different service classes for user data – delay, bit rate and connection type (connectionless or circuit

emulation) are the basic attributes of the service classes

• SAR (Segmentation and Reassembly) sub-layer for segmentation of variable length user data packets into fixed-size ATM cell payloads and at reception reassembly of ATM cell payload into user packets

• CS (Convergence Sub-layer) maps specific user data requirements onto ATM transport network

AAL maps higher-layer information into ATM cells to be transported over an ATM network. At reception, AAL collects information fromATM cells for delivery to higher layers.


ATM service classes

Connec-tionlessConnection- orientedConnection mode

VariableConstantBit rate

AAL3/4 or ALL5

AAL3/4 or ALL5AAL2AAL1ALL (s)

IP, SMDSFrame RelayX.25

Packet video, audio

E1,nx64 kbit/semulation

Examples

Not requiredRequiredTiming relation between source and destination

Class DClass CClass BClass AAttribute

Service class


ATM cell payloadATM header

ATM Adaptation layer 1 (AAL1)

SAR-PDU header User informationStructurepointer

SAR-PDU header User information

P format

Non-P format

CS ParitySequencecount CRC control

Seq. number field Seq. number protection

1 octet 1 octet 46 octets

SAR-PDU - Segmentation and Reassembly Packet Data UnitCS - Convergence Sub-layerCRC - Cyclic Redundancy Check



CID - Connection IdentificationHEC - Header Error CheckLI - Length IndicatorLLC - Logical Link ControlRES - Reserved

LLC packetheader CID=1

User information

3 octets < 61 octets

CID8 bits

LI6 bits

RES5 bits

HEC5 bits

LLC packetheader CID=2

User information . . .

ATM cell payloadATM

headerSTF ATM cell payload

ATMheader

STFATM

headerSTF

OSF6 bits

SN1 bit

Parity1 bit OSF - Offset

SN - Sequence NumberSTF - Start Field


ATM header ATM cell payload

ATM Adaptation layer 3/4 (AAL3/4)

SAR-PDU header

SAR-PDU payload Pad

2 octets 2 octets

SAR-PDU trailer

4 - 44 octets

48 octets

SARtype MIDSAR-

SNSAR-PDU

CRC

SAR-PDUUser info.

length

2 bits 4 bits 10 bits 6 bits 10 bits

AAL3/4 SAR PDU

CS-PDU header

CS-PDU user information Pad

CS-PDUtype

BASize

4 octets < 65 535 octets 4 octets

CS-PDU trailer

0-3octets

Btag Protocolcontrol

CS UserInfo. lengthETag

AAL3/4 CPCS PDU

CS - Convergence Sub-layerCPCS - Common Part CSCRC - Cyclic Redundancy CheckMID - Message IdentifierSAR - Segmentation and ReassemblyPDU - Packet data UnitBtag - Beginning tagBAsize - Buffer Allocation tagEtag - Ending tag



CS-PDU payload Pad

4 octets

CRC

0 -

47 o

ctet

s

UU CPI LEN

< 65 535 octets 2 oc

tets

1 oc

tet

1 oc

tet

Pad - Padding octetsUU - AAL layer user-to-user indicatorCPI - Common part indicatorLEN - Length indicatorCRC - Cyclic redundancy Check

ATM header

ATM cell payloadATM

headerATM cell payload . . .


ATM layer

• multiplexing/demultiplexing of cells belonging to different virtual connections

• translations of inbound VPIs/VCIs to outbound VPIs/VCIs

• cell header generation for data received from AAL and cell header extraction when a cell is delivered to AAL

• flow control

ATM layer (common to all services) offers transport of data in fixed-size cells and also defines the use of virtual connections (VPs and VCs)


General of ATM switching (cont.)

• ATM is a connection-oriented transport concept• an end-to-end connection (virtual channel) established prior to

transfer of cells

• signaling used for connection set up and release• data transferred in fixed 53 octets long cells (5 octets for

header and 48 octets for payload)

• Cells routed based on two header fields • virtual path identifier (VPI) - 8 bits for UNI and 12 bits for NNI• virtual channel identifier (VCI) - 16 bits for UNI and NNI• combination of VPI and VCI determines a specific virtual

connection between two end-points


ATM cell structure

ATMheaderATM

header Cell payloadCell payload

5 octets 48 octets

GFCGFC VPIVPI

VPIVPI VCIVCI

VCIVCI


HECHEC

ATM header for UNI

UNI - User Network InterfaceNNI - Network-to-Network InterfaceVPI - Virtual Path IdentifierVCI - Virtual Channel IdentifierGFC - Generic Flow ControlPTI - Payload Type IdentifierCPL - Cell Loss PriorityHEC - Header Error Control

VPIVPI

VPIVPI VCIVCI

VCIVCI


HECHEC

ATM header for NNI

HEC = 8 x (header octets 1 to 4) / (x8 + x2 + x + 1)



• VPI/VCI is determined on a per-link basis => VPI/VCI on an incoming link is replaced (at the ATM switch) with another VPI/VCI for an outgoing link => number of possible paths in an ATM network increased substantially (compared to having end-to-end VPI/VCIs)

• Each ATM switch includes a Routing Information Table (RIT), which is used in mapping incoming VPI/VCIs to outgoing VPI/VCIs

• RIT includes:• old VPI/VCI

• new VPI/VCI• output port address• priority



• When an ATM cell arrives to an ATM switch, VPI/VCI in the 5-octet cell header is used to point to a RIT location, which includes

• new VPI/VCI to be added to an outgoing cell• output port address indicating to which port the cell should be routed• priority field allowing the switch to selectively send cells to output

ports or discard them (in case of buffer overflow)• Three routing modes:

• unicast - log2N bits needed to address a destination output port• multi-cast - N bits needed to address destined output ports• broadcast - N bits needed to address destined output ports

• In multi-cast/broadcast case, a cell is replicated into multiple copies and each copy is routed to its intended output port/outbound VC



• ATM connections are either • pre-established - permanent virtual connections (PVCs)• dynamically set up - switched virtual connections (SVCs)

• Signaling (UNI or PNNI) messages carry call set up requests to ATM switches

• Each ATM switch includes a call processor, which• processes call requests and decides whether the requested

connection can be established• updates RIT based on established and released call connections

- ensuring that VPIs/VCIs of cells, which are coming from several inputs and directed to a common output are different

• finds an appropriate routing path between source and destinationports


VPI/VCI translation along transport path

ATM switch ATM switch ATM switch

15 10 8

X

Y Z

W

RIT - Routing Information Table

Old VPI/VCINew VPI/VCIOutput portPriority field

X Y 15 P

RIT

Y Z 10 P

RIT

Z W 8 P

RIT


VPI/VCI translation (cont.)

• VPI/VCI replacement usually takes place at the output ports=> RIT split into two parts

• input RIT - includes old VPI/VCI and N-bit output port address• output RIT - includes log2N-bit input port address, old VPI/VCI

and new VPI/VCI

• Since cells from different input ports can arrive to the same output port and have the same old VPI/VCI, the input port address is needed to identify uniquely different connections


ATM switches





Functional blocks of an ATM switch

Main blocks• Line interface cards (LICs), which implement input and output

port controllers (IPCs and OPCs)

• Switch fabric provides interconnections between input and output ports

• Switch controller, which includes - a call processor for RIT manipulations- control processor to perform operations, administration and maintenance (OAM ) functions for switch fabric and LICs


Main functional blocks of an ATM switch

…

IPC

SWITCHFABRIC

SWITCHCONTROLLER

…

OPC

LIC

SWITCHING &CONNECTION

CONTROL

IPC OPC

LIC

LIC - Line Interface CardIPC - Input Port ControllerOPC - Output Port Controller


Functions of input port controller

• Line termination and reception of incoming line signal

• Conversion of optical signal to electronic form if needed• Decoding/descrambling of line/block coded or scrambled line signal• Transport frame, e.g. SDH or PDH frame, processing• Extraction of cell header for processing• Storing of cell payload (or whole cells) to buffer memory• HEC processing

=> discard corrupted cells=> forward headers of uncorrupted cells to routing process

• Generation of a new cell header (if RIT only at input) and routing tag to be used inside switch fabric

• Cell stream is slotted and a cell is forwarded through switch fabric in a time-slot


Functions of output port controller

• Cells received from switch fabric are stored into output buffer• Generation of a new cell header (if RIT also at output)• One cell at a time is transferred to the outgoing line interface

• If no buffering available then contention resolution => one cell transmitted and others discarded

• If buffering available and priorities supported then higher priority cells forwarded first to transport frame processing

• Cell encapsulation into transport frames, e.g. SDH or PDH frame• Line/block encoding or scrambling of outgoing bit stream• Conversion of electronic signal to optical form (if needed)• Transmission of outgoing line signal


Input and output controller blocks

Input controller blocks:48

SDH

W Z 10

RIT

… … …

+

W5

Z

Old VPI/VCINew VPI/VCIOutput port

Fromnetwork

To switchfabric

Buffer10

Z 10

STM-1 frame

W. . . . . .

O/E

SDH E/OZFrom

switchfabric To network

BufferZ

Output controller blocks:STM-1 frame

Z. . . . . .


Switch control

• Switch controller implements functions of ATM management and control layer

• Control plane• responsible for establishment and release of connections, which

are either pre-established (PVCs) using management functions or set up dynamically (SVCs) on demand using signaling, such as UNI and PNNI signaling

• signaling/management used to update routing tables (RITs) in theswitches

• implements ILMI (Integrated Local Management Interface), UNI signaling and PNNI routing protocols

• processes OAM cells



• ILMI protocol uses SNMP (Simple Network Management Protocol) to provide ATM network devices with status and configuration information related to VPCs, SVCs, registered ATM addresses and capabilities of ATM interfaces

• UNI signaling specifies the procedures to dynamically establish, maintain and clear ATM connections at UNI

• PNNI protocol provides the functions to establish and clear connections, manage network resources and allow network to be easily configurable

• Management plane• provides management functions and capabilities to exchange

information between the user plane and control plane


ATM protocol reference model

Terminal TerminalNode Node

Physical layer

ATM layer

Management plane

ATM adaptation layer

Higher layer protocols Higher layer protocols

Control plane User plane Layer managem

entPlane m

anagement


Switch fabric

• Provides interconnections between input and output interfaces• ATM specific requirements

• switching of fixed length cells• no regular switching pattern between an input-output port pair,

i.e., time cap between consecutive cells to be switched from an input to a specific output varies with time

• Early implementations used time switching principle (mostly based on shared media fabrics) - easy to use, but limited scalability

• Increased input rates forced to consider alternative solutions=> small crossbar fabrics were developed => multi-stage constructions with self-routing reinvented


Cell routing through switch fabric

• Cells usually carried through switch fabric in fabric specific frames• Carrier frames include, e.g. header, payload and trailer fields• Header field sub-divided into

• source port address• destination port address• flow control sub-field (single/multi-cast cell, copy indication, etc.)

• Payload field carries an ATM cell (with or without cell header)• Trailer is usually optional and implements an error indication/

correction sub-field, e.g. parity or CRC

Frameheader Frame payload Frame

trailer

General structure of a cell carrier frame


ATM switching and buffering

• Due to asynchronous nature of ATM traffic, buffering is an important part of an ATM switch fabric design

• A number of different buffering strategies have been developed• input buffering• output buffering• input-output buffering• internal buffering• shared buffering

• cross-point buffering• recirculation buffering• multi-stage shared buffering• virtual output queuing buffering


Buffering strategies

Switchfabric

... ...

Input buffered

Switchfabric ......

Output buffered

Switchfabric ......

Input-output buffered

Internally buffered

Sharedmemory

Switchfabric... Switch

fabric ...

Shared buffer


Buffering strategies (cont.)

Cross-point buffered

Switchfabric

... ......

Recirculation buffered

......

...

......

... ...

Multi-stage shared buffer

Switchfabric... ...

......

Virtual output queuing


ATM switching and buffering (cont.)

Input buffered switches• Suffers from HOL blocking => throughput limited to 58.6 % of the

maximum capacity of a switch (under uniform load)

• Windowing technique can be used to increase throughput, i.e. multiple cells in each input buffer are examined and considered for transmission to output ports (however only one cell transmitted in a time-slot)=> window size of two gives throughput of 70 %=> windowing increases implementation complexity

Switchfabric... ...

Input buffered



Output buffered switches• No HOL blocking problem

• Theoretically 100 % throughput possible

• High memory speed requirement, which can be alleviated by concentrator => output port count reduced => reduced memory speed requirement => increased cell loss rate (CLR)

• Output buffered systems largely used in ATM switching

Switchfabric ......

Output buffered



Input-output buffered switches• Intended to combine advantages of input and output buffering

- in input buffering, memory speed comparable to input line rate- in output buffering, each output accepts up to L cells (1≤L≤N) => if there are more than L cells destined for the same output, excess cells are stored in input buffers

• Desired throughput can be obtained by engineering the speed up factor L, based on the input traffic distribution

• Output buffer memory needs to operate at L times the line rate=> large-scale switches can be realized by applying input-output buffering

• Complicated arbitration mechanism required to determine, which L cells among the N possible HOL cells go to output port



Internally buffered switch• Buffer implemented within switch blocks

• Example is a buffered banyan switch

• Buffers used to store internally blocked cells => reduced cell loss rate

• Suffers from low throughput and high transfer delay

• Support of QoS requires scheduling and buffer management schemes => increased implementation cost

Internally buffered



Shared-buffer switches• All inputs and outputs have access to a common buffer memory• All inputs store a cell and all outputs retrieve a cell in a time-slot

=> high memory access speed • Works effectively like an output buffered switch

=> optimal delay and throughput performance• For a given CLR shared-buffer switches need less memory than

other buffering schemes => smaller memory size reduces cost when switching speed is high (∼ Gbits/s)

• Switch size is limited by the memory access speed (read/write time)• Cells destined for congested outputs can occupy shared memory

leaving less room for cells destined for other outputs (solved by assigning minimum and maximum buffer capacity for each output)

Sharedmemory

Switchfabric... Switch

fabric ...

Shared buffer



Cross-point buffered switches• A crossbar switch with buffers at cross-points• Buffers used to avoid output blocking• Each cross-point implements a buffer and an address filter• Cells addressed to an output are accepted to a corresponding buffer• Cells waiting in buffers on the same column are arbitrated to the

output port one per time-slot• No performance limitation as with input buffering• Similar to output queuing, but the queue for each output is distributed

over a number (N) of buffers => total memory space for a certainCLR > CLR for an output buffered system

• Including cross-point memory in a crossbar chip, limits the number of cross-points

Cross-point buffered



Recirculation buffered switches• Proposed to overcome output port contention problem• Cells that have lost output contention are stored in

circulation buffers and they content again in the next time-slot • Out-of-sequence errors avoided by assigning priority value to cells • Priority level increased by one each time a cell loses contention

=> a cell with the highest priority is discarded if it loses contention

• Number of recirculation ports can be engineered to fulfill required cell loss rate (CLR = 10-6 at 80 % load and Poisson arrivals => recirculation port count divided by input port count = 2.5)

• Example implementations Starlite switch and Sunshine switch - Sunshine allows several cells to arrive to an output in a time-slot => dramatic reduction of recirculation ports

Switchfabric

... ......

Recirculation buffered



Multi-stage shared buffer switches• Shared buffer switches largely used in implementing small-scale

switches - due to sufficiently high throughput, low delay and high memory utilization

• Large-scale switches can be realized by interconnecting multiple shared buffer switch modules => system performance degraded due to internal blocking

• In multi-stage switches, queue lengths may be different in the 1st and 2nd stage buffers and thus maintenance of cell sequence at the output module may be very complex and expensive

......

...

......

... ...

Multi-stage shared buffer



Virtual output queuing switches• A technique to solve HOL blocking problem in input buffered

switches

• Each input implements a logical buffer for each output (in a common buffer memory)

• HOL blocking reduced and throughput increased

• Fast and intelligent arbitration mechanism required, because allHOL cells need to be arbitrated in each time-slot=> arbitration may become the system bottleneck

Switchfabric... ...

......

Virtual output queuing


Design criteria for ATM switches

• Several criteria need to be considered when designing an ATM switch architecture

• A switch should provide bounded delay and small cell loss probability while achieving a maximum throughput (close to 100%)

• Capacity to support high-speed input lines (which possibly deploy different transport technologies, e.g. PDH or SDH)

• Self-routing and distributed control essential to implement large-scale switches

• Maintenance of correct cell sequence at outputs


Performance criteria for ATM switches

• Performance defined for different quality of service (QoS) classes• Performance parameters:

• cell loss ratio (CLR)• cell transfer delay (CTD)• two-point cell transfer delay variation (CDV)

Performance parameter CLP QoS1 QoS3 QoS4

Cell loss ratio 0 < 10-10 <10-7 <10-7

Cell loss ratio 1 N/S N/S N/SCell transfer delay (99th percentile) 1/0 150 µµµµs 150 µµµµs 150 µµµµsCell delay variation (10-10 quantile) 1/0 250 µµµµs N/S N/SCell delay variation (10-7 quantile) 1/0 N/S 250 µµµµs 250 µµµµs

N/S - not specified

Bellcore recommended performance requirements


Distribution of cell transfer delay

• Figure below shows a typical cell transfer delay distribution through a switch node

• Fixed delay is attributed to table lookup delay and other cell header processing (e.g. HEC processing)

• For example:- Prob(CTD > 150 µs) < 1 - 0.99 => a = 0.01 and x = 150 µs (QoS1, 3 and 4)- Prob(CTD > 250 µs) < 10-10 => a = 10-10 and x = 250 µs (QoS1)

fixed density peak- to- peak CDV

maximum CDV

Probabilitydensity

Cell transferdelay

1 - a x a


Cell processing times at different transmission speeds

100 ns

1 us

10 us

100 us

1 ms

10 ms

100 ms

9.6 64 384 2 10 34 100 155 622 2.5

kbit/s Mbit/s Gbit/s

Link speed

Proc

essi

ng ti

me

221 µµµµs/E1 2.83 µµµµs/STM-1

708 ns/STM-4

177 ns/STM-16


Delay and jitter components

1

2

3

4

Encapsulation/decapsulation delay

Admission control (smoothing)

Queuing delay

Switching delay

5

6

7

Transmission delay

Propagation delay

Reassembly (playtime) delay

No contribution to jitter

Contribution to jitter

UserA

Node1

Node2

Noden

UserB

1 2 3 45

6

751

6 6 6

2 3 4 513 311 2 3 4 51 1 1


ATM switches





ATM switching fabric implementations

A lot of different switching network architectures have been experimented in ATM switch fabrics :

• Batcher-banyan based switches, e.g. Sunshine

• Clos network based switches, e.g. Atlanta

• Crossbar/crosspoint switches, e.g. TDXP (Tandem-Crosspoint)

• Ring and single/dual bus based switches

Most advanced ATM switching concepts are switching network independent, e.g. Knockout and Abacus


Knockout switch

• Output buffered switches largely used in ATM networks

• Capacity of output buffered switches limited by memory speed

• Problem solved by limiting the number of cells allowed to an output during each time-slot and excess cells discarded=> knockout principle

• How many cells to deliver to an output port during each time-slot=> this number can be determined for a given cell loss rate (CLR), e.g. 12 time-slots for CLR=10-10, independent of switch size

• Memory speed seemed to be no more a bottleneck, however no commercial switch implementations appeared- inputs are supposed to be uncorrelated (not the case in real networks) - idea of discarding cells not an appealing one

• Knockout principle has been basis for various switch architectures


Knockout principle

• N input lines each implement a broadcast input bus, which is connected to every output block

• An output block is composed of cell filters that are connected to an N-to-L concentrator, which is further connected to a shared buffer

• No congestion between inputs and output blocks

• Congestion occurs at the interfaces of outputs (inside concentrator)

• k cells passing through cell filters enter the concentrator and- if k≤≤≤≤L then all cells go to shared buffer- if k>L then L cells go to shared buffer and k-L cells are discarded

• Shared buffer includes a barrel shifter and L output (FIFO) buffers- barrel shifter stores cells coming from concentrator to FIFO memories in round robin fashion => complete sharing of output FIFO buffers


Knockout switch interconnection architecture

12

N

...

1 2

...

N

Inpu

ts

Outputs

Broadcast buses

Bus interfaces


Knockout switch bus interface

Barrel shifter

Cellbuffers

Output

Concentrator

Sharedbuffer

...

1 2 3 4 N-1 N

... Cellfilters

1 2 L

...1 2 L

Inputs


Operation of barrel shifter

A

Barrel shifter

B

C

...

...A

B

C..................

Buffer At time T

D

E

F

G

H

I

J

...

...I

J

A

B

C

D

E

F

G

H

...

...

...

...

...

...

Barrel shifter Buffer At time T+1


Example construction of concentrator

Outputs

Input

D

D

D

D

D

D

D

D

D

D

D

D

D

D

1 2 3 4

An 8-to-4 concentrator


Cell loss probability

• In every time-slot there is a probability ρρρρ that a cell arrives at an input• Every cell is equally likely destined for any output• Pk denotes probability of k cells arriving in a time-slot to the same

output, which is a binomial distribution

, k = 0,1, …, N

• Probability of a cell being dropped in N-to-L concentrator is given by

• Taking the limit as N →→→→ ∞∞∞∞ and with some manipulation

P Nk N

1Nk

k N k

====

−−−−

−−−−ρρρρ ρρρρ

(((( ))))P(cell loss) k - L Nk N Nk L 1

N k N-k

====

−−−−

==== ++++∑∑∑∑

1 1ρρρρ

ρρρρ ρρρρ

P(cell loss) L ek!

eL!

k -

k=0

L L -

==== −−−−

−−−−

++++∑∑∑∑1 1

ρρρρρρρρ ρρρρρρρρ ρρρρ


Cell loss probability (cont.)

Cell loss probability for some switch sizes(90% load)

Number of concentrator outputs, L1 2 3 4 5 6 7 8 9 10 11

Cel

l los

s p

roba

bilit

y

10-2

10-4

10-6

10-8

10-10

10-12

100

N = 16N = 32N = 64N = ∞∞∞∞

Load = 100 %Load = 90 %Load = 80 %Load = 70 %Load = 60 %

Number of concentrator outputs, L1 2 3 4 5 6 7 8 9 10 11

Cel

l los

s p

roba

bilit

y

10-2

10-4

10-6

10-8

10-10

10-12

100

Cell loss probability for some load values(N = ∞∞∞∞)


Channel grouping

Channel grouping principle used in modular two-stage networks

• A group of outputs treated identically in the first stage

• A cell destined for an output of a group is routed to any output (at the first stage), which is connected to that group at the second stage

• First stage switch routes cells to proper output groups and second stage switches route cells to destined output ports

Cell to 6

1st stage

Cell to 1

Cell to 3

2nd stage

0123

4567

Cell to 4


Channel grouping (cont.)

Asymmetric switch with line extension ratio of KM/N• Output group of M output ports corresponds to a single output

address for the 1st stage switch

• At any given time-slot, M cells at most can be cleared from a particular output group (one cell on each output port)

NxKMswitch

12

NMxM

switch

MxMswitch

... ...

M M

M M

1

K



Maximum throughput per input• increases with K/N for a given M (because load per output group

decreases)• increases with M for given K/N (because each output group has

more ports for clearing cells)

M K/N = 1/16 1/8 1/4 1/2 1 2 4 8 161 0,061 0,117 0,219 0,382 0,586 0,764 0,877 0,938 0,9692 0,121 0,233 0,426 0,686 0,885 0,966 0,991 0,998 0,9994 0,241 0,457 0,768 0,959 0,996 1 1 18 0,476 0,831 0,991 1 116 0,878 0,999 1

Maximum throughput per input for some values of M and K/N



• Maximum throughput per input increases with M for given KM/N• Channel grouping has a strong effect on throughput for smaller

KM/N than for larger ones

M KM/N = 1 2 4 8 16 321 0,586 0,764 0,877 0,938 0,969 0,9842 0,686 0,885 0,966 0,991 0,998 0,9994 0,768 0,959 0,966 1 1 18 0,831 0,991 1

16 0,878 0,99932 0,912 164 0,937

128 0,955256 0.968512 0,978

1024 0,984

Maximum throughput as a function of line expansion ratio KM/N


Multicast output buffered ATM switch (MOBAS)

• Channel grouping extends to the general Knockout principle• MOBAS adopts the general Knockout principle• MOBAS consists of

• input port controllers (IPCs)• multi-cast grouping networks (MGN1 and MGN2)• multi-cast translation tables (MTTs)• output port controllers (OPCs)

NxLNswitch

12

NLMxMswitch

LMxMswitch

... ...

LxM M

LxM M

1

KN-M+1

N

1

M

NxN switch withgroup extension ratio L


MOBAS switch performance

• IPCs terminate incoming cells, look up necessary information in translation tables and attach information in front of cells so that the cells can properly be routed in MGNs

• MGNs replicate multi-cast cells based on their multi-cast patterns and send one copy to each addressed output group

• MTTs facilitate the multi-cast cell routing MGN2

• OPCs store temporarily multiple arriving cells (destined for their output ports) in an output buffer, generate multiple copies for multi-cast cells with a cell duplicator (CD), assign a new VCI obtained from a translation table to each copy, convert internal cell format to standard ATM cell format and finally send the cell to the next switching node

• CD reduces output buffer size by storing only one copy of a multi-cast cell - each copy is updated with a new VCI upon transmission


MOBAS architecture

IPC - Input Port ControllerMGN - Multi-cast Grouping Network MTT - Multi-cast Translation Table

OPC - Output Port ControllerSM - Switching ModuleSSM - Small Switch Module

1

N

IPC

...

IPC

...

SM 1

SM K

...

MGN 1

...

L1xM

...

L1xM

Group 1

Group K

MTT

MTT

SM 1

SM M

... ...

M

1

OPC

Outputbuffer

L2

... CD

Outputbuffer

L2

... CD

MGN2

MTT

MTT

SM 1

SM M

... ...

N

N-M+1

OPC

Outputbuffer

L2

... CD

Outputbuffer

L2

... CD

MGN2

CD - Cell Duplicator


Abacus switch

• Knockout switches suffer from cell loss due to concentration/channel grouping (i.e. lack of routing links inside switch fabric)

• In order to reduce CLR, excess cells are stored in input buffers=> result is an input-output buffered switch

• Abacus switch is an example of such a switch

• basic structure similar to MOBAS, but it does not discard cells in switch fabric

• switching elements resolve contention for routing links based onpriority level of cells

• input ports store temporarily cells that have lost contention

• extra feedback lines and logic added to input ports

• distributed arbitration scheme allows switch to grow to a large size


Abacus switch (cont.)

IPC - Input Port ControllerMGM - Multi-cast Grouping Network MTT - Multi-cast Translation Table

OPC - Output Port ControllerRM - Routing ModuleSSM - Small Switch Module

1

N

IPC

...

IPC

IPC

2

...

RM 1

RM K

...

MGM

SSM 1...

LxM

M

MTT

MTT

OPC

OPC

...

M1

SSM K...

LxM

N

MTT

MTT

OPC

OPC

...

MN-M+1

......


ATM switches





Dimensioning example

• An ATM-switch is to be designed to support 20 STM-4 interfaces. RIT will be implemented at the input interfaces. How fast should RIT lookup process be ?

• Cells are encapsulated into frames for delivery through the switch fabric. A frame includes a 53-octet payload field and 3 octets of overhead for routing and control inside the switch fabric. What is the required throughput of the switch fabric ?

Solution• ATM cells are encapsulated into VC-4 containers, which include 9

octets of overhead and 9x260 octets of payload. One VC-4 container is carried in one STM-1 frame and each STM-1 frame contains 9x261 octets of payload and 9x9 octets of overhead. (See figure on the next slide)


SOH

AU-4 PTR

SOH

9 octets 261 octets

3

1

5

STM-1frame

ATM cell

J1

B3

C2

G1

F2

H4

Z3

Z4

Z5

......

... ...

...

...

VC-4frame

VC-4 POH

ATM cell encapsulation / SDH


Dimensioning example (cont.)

Solution (cont.)• STM-4 frame carries 4 STM-1 frames and thus there will be

4x9x260 / 53 = 176.6 cells arriving in one STM-4 frame

• One STM-4 frame is transported in 125 µs => 176.6/125 µs = 1412830.2 cells will arrive to an input in 1 sec=> one RIT lookup should last no more than 707,8 ns

• Total throughput of the switch fabric is 20x1412830.2 cells/s

• Since each cell is carried through the switch fabric in a container of 56 octets, the total load introduced by the inputs to the switch fabric is 20x1412830.2x56 octets/s ≈ 1.582 109 octets/s ≈ 12,7 Gbits/s


Routers implementations



Router implementations

• General of routers• Functions of an IP router• Router architectures• Introduction to routing table lookup


General of routers

• Router is a network equipment, which• performs packet switching operations• operates at network layer of the OSI protocol reference model• switches/routes variable length packets • routing decisions based on address information carried in packets

• Router is used to connect two or more networks that may or may not be similar

• Routers communicate with each other by means of routing messages to

• exchange routing information• resolve next hop addresses• maintain network topology to make routing decisions


IPv4 packet structure

Data field

Options + padding Destination address (32 bits)

Source address (32 bits)Time to live Protocol

Identifier Ver. IHL TOS

4 4 168 3

Header checksum Flag Fragment offset

Length

20 o

ctet

s

Flag - used in connection with fragmentation: more bit indicates whether this fragment is the last one of a fragmented packet and don’t fragment bit inhibits/prohibits packet fragmentationFragment offset - indicates where in the original user data message this fragment belongs, measured in 64-bit units (all but last the fragment has a data field that contains a multiple of 64-bit payload)Time-to-live - defines the maximum time in seconds a packet can be in transit across the Internet (decremented by each visited router by a defined amount)Protocol - indicates the type of protocol (TCP, UDP, etc.) carried by the IP packet Header checksum - carries a checksum calculated over the header bits

Version - IP version numberIHL - Internet header length in 32-bit words (min. size = 5)TOS - type of service (guidance to end-system IP modules and router along transport path)Length - total length (header + payload) of IP packet in octetsIdentifier - sequence number, which together with address and protocol fields identify each IP packet uniquely


IPv6 packet structure

Data field

Destination address (128 bits)

Source address (128 bits)

Payload length (16)Version Traffic class

4 8 20

Next header (8)

40 o

ctet

s

Hop limit (8) Flow label

Payload length - indicates the number of octets in the payload fieldNext header - indicates the type of additional (extension) header following the main headerHop limit - value for the maximum number of hops the packet is allowed to travel in a network

Version - version number of IP protocolTraffic class - Class-of-service (CoS) priority of the packetFlow label - identifies all packets belonging to a specific flow (requiring a specific CoS), and routers can identify these packets and handle them in a similar fashion. A flow is uniquely identified by the combination of a source address and a non-zero flow label.



• General of routing• Functions of an IP router• Router architectures• Introduction to routing table lookup


Major tasks of a router

C - Classify (classification, filtering and routing)F - Forward (transfer of packets from input interfaces to addressed

output interfaces)S - Scheduling (transmission of data packets based, e.g. on priority)

In_port

...C

...

F

F

F

SOut_port


Main functional blocks of a router

Networkprocessor


InterfaceCard #1Input port #1

Switchfabric


InterfaceCard #1Output port #1

Generic router architecture


Input port functionality

• Layer 1 termination of incoming physical links (e.g. SDH, Ethernet)• Layer 2 frame decapsulation to inter-operate with data-link

protocols of connected networks (e.g. AAL5/ATM/SDH and PPP/SDH)

• Forwarding of control packets, e.g. routing information packets (RIP, OSPF, IGMP), to network processor to update routing table and network topology

• Some implementations distribute a copy of routing table and table lookup to each input port, while some other implementations forward all incoming packets to a centralized routing processor

Input port functionality

Layer 1 func.Line

termination

Layer 2 func.Protocol

decapsulation

Lookup/forwarding/

queuing


Output port functionality

• Buffering of outbound packets

• Scheduling of buffered packets to guarantee required QoS

• Layer 2 frame generation and encapsulation of packets into frames (e.g. AAL5/ATM/SDH, PPP/SDH and Ethernet)

• Layer 1 physical signal generation

Output port functionality

Buffermanagement/

queuing

Layer 2 func.Protocol

encapsulation

Layer 1 func.Line

termination


Switch fabric functionality

• Main function is to route data packets from input ports to addressed output ports

• Depending on the switch fabric implementation, packets are transported through the fabric either as uniform variable lengthpackets or they are fragmented to fixed size data units

• In either case, extra information is added in front of the packets to direct them through the fabric

• switching of whole packets is usually applied in low-speed routers

• switching of fragments is normally used in high-speed routers

• Majority of switch fabrics are based on three basic architectures: bus based, memory based and interconnection network based


Network processor functionality

• Maintenance of routing table

• Execution of routing protocols

• Maintenance of routing topology

• Performance of network management

• Wire-speed operation obtained by implementing key functions in hardware

• Processing of packets- classification- order management- acceleration of lookup- queue management- QoS engine

Network processor functionality

Classifier Classifier Classifier

Order management

Embeddedprocessor

Embeddedprocessor

Embeddedprocessor

Lookup Lookup Lookup

Queue management

QoS QoS QoS

Incoming packets

Outgoing packets


Router classification

• Access routers• link homes and small business to ISPs (Internet Service Provider)• need to support a variety of access technologies, e.g. high-speed

modems, cable modems and xDSL

• Enterprise/metropolitan routers• used as campus and office interconnects• QoS guarantees for local traffic• support of several network layer protocols (e.g. IP and IPX)• support of additional features, such as firewalls, security policies and

virtual LANs

• Backbone/long haul routers• interconnect enterprise routers• huge number of packets per second => very-high-speed requirement• critical components for interworking => reliability of utmost concern





Basic types of router architecture…

ForwardingEngine

ForwardingEngine

ForwardingEngine

…

LineInterface

LineInterface

LineInterface

Networkprocessor

Router with forwarding engines

…

Line Int. +Forwarding



Networkprocessor

…




Router with added processingpower in interfaces


First generation router architecture

• Network layer protocols were constantly changing=> adaptable solution was needed=> a single and common purpose processor structure was a reasonable one in which operating system in central role

• Low throughput (packets transferred twice through the bus)

did not scale well with increasing line speeds

CPU

Interfacecard #1Interface

card #1Interfacecard #1

Shared bus, a single processor card and line interface cards


Second generation router architecture

• Each line card implemented a processor => distributed and parallel routing became available

• Main processing unit took care of delivery of routing information to line interface cards

• Operating system still in central role

• Cache memories were introduced to speed up routing decisions (most recently used routing entries kept in cache)

• Increased throughput, but shared bus still a bottleneck

• Solution did not scale with increasing line speeds


card #1Interfacecard #1+ CPU

MainCPU

Shared bus and a processoron each line interface card


Third generation router architecture

• Shared bus replaced with more powerful switch fabrics (e.g. multi-stage and crossbar)

• Parallel processing units (based on general purpose processors)

• Cache memories to enhance routing decision making

• Operating system still played an important role

• Communication between line interfaces no more a problem

• QoS increases processing power requirement (IP/TCP/application)

• Did not scale well enough withthe most advanced line speeds

Switch fabric andmore processing power


card #1Interfacecard #1+ CPU

+ cache

CPUCPU #1


Support of differentiated services

• Packet classification - distinguish packets and group them according to their different requirements

• Buffer management - determine how much buffer space should be given to certain kinds of network traffic and which packets should be discarded in case of congestion

• Packet scheduling - decide that the packet servicing order meets the bandwidth and delay requirements of different types of traffic

Traditional routers are limited in terms of their quality of service and differentiation features. Advances in research and hardware capabilities have provided mechanisms to overcome these limitations. Following operations, possible today to carry out in high speed, allow provisioning of differentiated services:


DiffServ routing

Router 1 Router 2

Host 1 Host 2

Phys. (twisted pair) Phys. (optical) Phys. (twisted pair)

100 MbE

Eth. MAC

IP

TCP/UDP

Appl.

100 MbE

Eth. MAC

1 GbE

Eth. MAC

IP

1 GbE

Eth. MAC

100 MbE

Eth. MAC

IP

100 MbE

Eth. MAC

IP

TCP/UDP

Appl.

TCP/UDP TCP/UDP


DiffServ routing (cont.)

Router 1 Router 2

Host 1 Host 2

Phys. (twisted pair) Phys. (optical) Phys. (twisted pair)

100 MbE

Eth. MAC

IP

TCP/UDP

Appl.

100 MbE

Eth. MAC

1 GbE

Eth. MAC

IP

1 GbE

Eth. MAC

100 MbE

Eth. MAC

IP

100 MbE

Eth. MAC

IP

TCP/UDP

Appl.

TCP/UDP TCP/UDPAppl. Appl.


Sharing of processing resources and pipelining

DiffServ-optimized router architecture

Interface card #1+ multiple special

purpose CPUsInterface card #1+ multiple special



purpose CPUsConcentrator

Filtering

Scheduler

RouteLookup Buffering


Sharing of processing resources and pipelining (cont.)

• Packet processing divided into a number of consecutive processes -each process has a dedicated processing unit (buffering, filtering, routing, etc.)

• Pipelined processes shared by several interfaces to increase number of line interfaces - concentrator schedules packets for processes

• QoS-based scheduler takes care of packet transmission from buffers to outbound interfaces


Packet processing capacity

• Packet processing capacity of a router is given as the number offorwarded packets/second and/or forwarded bits/second

• Tasks affecting forwarding speed- link protocol processing delay (input and output)- address lookup time- switching of packets from input ports to outputs ports - queuing at output ports and possibly at input ports

• Other tasks that may have an impact on forwarding speed- routing table management/updates- network and router management

• In high capacity routers, routing table lookups are a major problem

• Queuing is the main component of routing latency

• Routing capacity requirement determined by the shortest packets


Future challenges

• Increase of line speeds- 100 Mbit/s => 1 Gbit/s => 10 Gbit/S => 40/100 Gbit/s

• QoS-support => increased processing need- DiffServ, IntServ, MPLS, ...

• From “best effort” service to controlled use of network resources=> programmable network nodes

• Different needs in the core and edge networks- huge routing capacity in the core network ( > 10 million packets/s)- a lot of functionality and intelligence in the edge routers


Speedup mechanisms for routing table lookup

• Caching– routing table entries of most lately arrived packets or entries

most frequently accessed are stored in cache memory• Pipelining

– different phases of routing table lookup are executed by different pipelined processing units

• Distribution of lookup to interfaces or to several routing engines

– network processor takes care of routing table updates and distributes updated tables to separate interface/routing engines

• In centralized routing solutions only packet headers are sent to a routing processor

• Implementation of lookup functionality in hardware (at the expense of flexibility)


Caching to speedup packet processing and forwarding

• When a packet with a new destination address arrives to an inputport, it passes through the conventional routing process (slow path) and its routing entry is stored in cache memory

• Subsequent packets carrying the same destination address are routed using the routing entry in the cache memory (fast path)

• A routing entry is removed from cache when predefinedconditions to keep it in cacheexpire, e.g. packet arrivalrate declines or time sincethe last packet becomes too long

……

…

Fast path

Slow path

Fast path

Slow path

…

1

N

1

N


High speed router examples

• GSR /Cisco - first gigabit router on the market- switching capacity of 27.5 Gbits/s- equipped with POS (Packet Over Sonet) and ATM interfaces

• 12000 Terabit System /Cisco - initial switching capacity of 150 Gbits/s, but scalable up to 5 Tbits/s- can be equipped with OC192/STM-64 (10 Gbits/s) interfaces

• NX64000 /Lucent (Nexabit)- one of the highest capacity routers (6.4 Tbits/s)- supports interface rates up to OC192/STM-64- distributed programmable hardware based forwarding engine- 1 million routing entries on each line card- 40 ms delay guarantee for variable size packets


High speed router examples (cont.)

• MGR (Multi-Gigabit Router) /BBN Technologies - forwarding rate up to 21 million packets per second- switching backplane capacity of 50 Gbits/s- multiple line cards and separate forwarding engine cards plugged into a high-speed switch- only packet headers are directed to forwarding engines - payloads queued on line cards

• TSR (Terabit Switch-Router) / Avici- designed to be scalable from 600 Mbit/s to several Tbits/s- hardware based routing, forwarding, multi-casting and QoS service- each line card implements a 70 Gbit/s router and 20 such line cards fit into a dual-shelf chassis => total switching capacity is 1.4 Tbits/s


Example of routing table lookup speed determination

In a distributed routing table lookup solution, each input port implements a routing table. What is the maximum allowed routing decision delay if the input link is a 100 Mbit/s Ethernet link or 1 Gbit/slink and the router should operate at wire-speed ?

Solution:• In both example cases, the routing decision delay requirement

corresponds to maximum packet arrival rate at these interfaces

• The maximum packet arrival rate is encountered when there is a constant stream of minimum size Ethernet frames

• The minimum size 100 MbE frame is 64 octets and there are 8 octets of preamble and SFD information in front of each frame and additionally there is always a 0.96 µs time gap between successive frames


Example of routing table lookup determination (cont.)

Solution (cont.):• Time required to transmit 72 octets (64+8) at the speed of 100

Mbit/s is 5.76 µs => minimum time interval between successive frames is 5.76 µs + 0.96 µs = 6,72 µs, which is also the maximum allowed routing decision delay for a 100 MbE input port=> forwarding capacity is about 149 000 packets/s

• The minimum size 1 GbE frame is 512 octets and there are 8 octets of preamble and SFD information in front of each frame and there is a 96 ns time gap between successive frames

• Time required to transmit 520 octets (512+8) at the speed of 1 Gbit/sis 4.16 µs => minimum time interval between successive frames is 4.16 + 0.096 µs = 4.256 µs, which is also the maximum allowed routing decision delay for a 1 GbE input port (frame bursting excluded)=> forwarding capacity is about 235 000 packets/s


10/100 MbE frame

PreambleSFD

DA SA T/L Payload CRC

7 1 6 6 2 46 - 1500 4

64 - 1518 octets

Preamble - AA AA AA AA AA AA AA (Hex)SFD - Start of Frame Delimiter AB (Hex)DA - Destination AddressSA - Source AddressT/L - Type (RFC894, Ethernet) or Length (RFC1042, IEEE 802.3) indicatorCRC - Cyclic Redundancy CheckInter-frame gap 12 octets (9,6 µµµµs /10 MbE)


1GbE frame

PreambleSFD

DA SA L Payload

7 1 6 6 2 46 - 1500 4

512 - 1518 octets

CRC Extension

Preamble - AA AA AA AA AA AA AA (Hex)SFD - Start of Frame Delimiter AB (Hex)DA - Destination AddressSA - Source AddressT/L - Type (RFC894, Ethernet) or Length (RFC1042, IEEE 802.3) indicatorCRC - Cyclic Redundancy CheckInter- frame gap 12 octets (96 ns /1 GbE)Extension - for padding short frames to be 512 octets long





Classful addressing scheme

• In IPv4, addresses are 32 bits long - broken up into 4 groups of 8 bits and represented usually as four decimal numbers separated by dots, e.g., 10000010 01010110 00010000 01000010 = 130.86.16.66

• IP intended for interconnecting networks => routing based on network is a natural choice (rather than based on host)

• IP address scheme initially used a simple two level hierarchy -networks at the top level and hosts at the bottom level

• Network part (i.e. address prefix) corresponds to the fist bits

• Prefixes written as bit strings up to 32 bits in IPv4 followed by “*”- e.g. 1000001001010110* represents all the 216 addresses that begin with bit pattern 1000001001010110- an alternative way is to use dotted-decimal expression, i.e., 130.86/16 (number after the slash indicates length of prefix)


Classful addressing scheme

• With the two level hierarchy, IP routers forwarded packets based on the network part, until packets reached their destination network

• Forwarding table only needed to store a single entry to forward packets to all hosts attached to the same network - technique is called address aggregation and allows prefixes to represent a group of addresses

• Three different network sizes were defined: A, B and C (see figure)

0

10

110

7 24

14 16

21 8

Class A

Class B

Class C


Classful addresses

• Classful addressing scheme worked well in the early days of the Internet

• Two basic problems appeared when the number of hosts and networks grew

• address space was not efficiently used (only three possible network sizes available) and was getting exhausted very rapidly

• forwarding tables in the backbone routers grew rapidly, because routers maintain an entry in the forwarding table for every allocated network address => larger memory requirement => long lookup times


Classless InterDomain Routing (CIDR)

• CIDR was introduced to allow more efficient use of IP address space and to slow down growth of backbone routing tables

• CIDR allows prefixes to be of arbitrary length, not just 8, 16 or 24 bits as in classful address scheme

• A network that has identical routing information for all sub-nets, except for a single one, requires only two entries in the routing table

• In CIDR, each IP route is represented by a route_prefix / prefix_length pair

– prefix length indicates the number of significant bits in a route prefix – e.g. a routing table may have prefixes 12.0.54.8/32, 12.0.54.0/24

and 12.0.0.0/16. If a packet is destined for address 12.0.54.2, the second prefix matches


Difficulties with longest match prefix search

• In classful addressing scheme, prefix length is coded in the most significant bits of an IP address => address lookup is a relatively simple operation

- prefixes are organized in three separate tables (A, B and C)=> an exact prefix match could be found using standard search algorithms based on hashing or binary search

• CIDR allows reduced size of forwarding tables, but address lookup problem becomes more complex=> prefixes are of arbitrary length and no longer correspond to the network part=> search in the forwarding table can no longer be performed by exact matching, because the length of the prefix cannot be derived from the address itself=> searching in two dimensions: bit pattern value and length


Route lookup

• Primary goal in designing a data structure to be used in a forwarding table is to minimize lookup time, i.e.- minimize number of memory accesses required during lookups- minimize size of data structure (to fit partly or entirely into a cache)

• Secondary goals of a data structure- as few instructions during lookup as possible- keep the entities naturally aligned as much as possible to avoid expensive instructions and cumbersome bit-extraction operations

• A binary tree, spanning the entire IPv4 addressspace has a height of 32 and numberof leaves is 232

232 leaves (IP addresses)

Dep

th 3

2


Route lookup (cont.)

• A prefix of a routing table entry defines a path in the tree ending in some point and all IP addresses (leaves) in a sub-tree, rooted at that node, should be routed according to that routing entry, i.e. each routing table entry defines a range of IP addresses with identical routing information

• If several routing entries cover an IP address, the longest matching rule is applied, i.e. the longest applicable prefix should be used

• In the figure below, e2 represents a longermatch than e1 for addressesin range r e1

e2

r


Route lookup based on binary trie

• A trie is a tree-based structure allowing to organize prefixes on a digital basis by using the bits of prefixes to direct the branching

• In a trie, a node on level k represents the set of all addresses that begin with the same k bits that label the path from the root to that node, e.g. node c in the figure on the next slide is at level 3 and represents all addresses beginning with the sequence 011

• Nodes that correspond to prefixes are shown in a darker shade -these nodes contain the forwarding information or a pointer to it

• Some addresses may match several prefixes, e.g. addresses beginning with 011 will match prefixes c and a => prefix c is preferred because it is more specific (longest match rule)


A binary trie for a set of prefixes

Prefixes:a - 0*b - 01000*c - 011*d - 1*e - 100*f - 1100*

g - 1101*h - 1110*I - 1111*

0 1

a

b

c

0

0

0

1

d

e

0

0

0

11

f g h i

0

0

1

11

Next-hop pointer (if prefix)

Left-ptr Right-ptr

Information stored by a node:


Address space of 5-bit long addresses

a

aa aa aa aa ab aa cc

c

cc

d

ee

e

ee dd dd

f

ff

g

gg

h

hh

i

ii

Prefixes:a - 0*b - 01000*c - 011*d - 1*e - 100*

f - 1100*g - 1101*h - 1110*i - 1111*


Route lookup based on binary trie

• Tries allow finding the longest prefix that matches a given destination address and the search is guided by the bits of the destination address

• While traversing the trie and visiting a node marked as a prefix, this prefix is marked as the longest match found so far

• The search ends when no more branches to take exist and the longest match is the prefix of the latest visited prefix node

• An example address 10110– from root move to the right (1st bit value = 1) to node d marked as a prefix,

i.e. 1st found prefix is 1*

– then move to the left (2nd bit value = 0) to a node not marked as a prefix => prefix d still valid

– 3rd address bit = 1, but at this point there is no branch to the right => search stops => d is the last visited prefix node and prefix of d is the longest match


Route lookup based on binary trie (cont.)

• Going trough a trie is a sequential prefix search by length when trying to find a better match

– begin looking in the set of length-1 prefixes, located at level 1– then proceed in the set of length-2 prefixes at level 2,

– then proceed to level 3 and so on

• While stepping through a trie, the search space reduces hierarchically

– at each step, the set of potential prefixes reduces and the search ends when this set is reduces to one

• Update operations are straightforward– inserting a new prefix proceeds as a normal search and when arriving to

a node with no branch to take, insert the necessary node

– deleting a prefix proceeds also as a search and when finding therequired node, unmark it as a prefix node and delete it if necessary


Path-compressed tries

• In binary tries, long sequences of one-child nodes may exist and these bits need to be inspected even though the actual branchingdecision has been made => search time can be longer than necessary=> one-child nodes consume additional memory

• Lookup time of a binary trie is O(W) and memory requirement O(NW)

– W is the address length in bits and N the number of entries in a table

• Path-compression technique can be used to remove unnecessary one-way branch nodes and reduce search time and memory consumption


Path-compressed tries (cont.)

• Path-compression was first introduced in a scheme called Patricia, which is an improvement of the binary trie structure

• it is based on the observation that an internal node, which does not contain a prefix and has only one child, can be removed

• removal of internal nodes requires information of missing nodes to be added in remaining nodes so that search operations can be performed correctly, e.g. a simple mechanism is to store a number, which indicates how many nodes have been skipped (skip value) or the number of the next address bit to be inspected

• There are many ways to exploit path-compression technique, an example is shown on the next slide

• Lookup time is O(W) and worst case storage requirement O(NW)


A path-compressed trie example

Prefixes:a - 0*b - 01000*c - 011*d - 1*e - 100*f - 1100*

g - 1101*h - 1110*I - 1111*

Uncompressed binary trie

0 1

a

b

c0

0

0

1

d

e

0

0

0

11

f g h i

0

0

1

11

Compressed binary trie

0 1a

b c0 1

3d

f g h i

e

1

0

0

0 0

1

1

1

2

36 4

1

4

4 4

5

Information stored by a node:Next-hop ptr

(if prefix)

Left-ptr Right-ptr

Bit string Bit position


A path-compressed trie example (cont.)

• Two nodes preceding b have been removed

• Since prefix a was located at one child node, it was moved to the nearest descendant, which is not a one-child node

• If several one-child nodes, in a path to be compressed, contain prefixes, a list of prefixes must be maintained in some of the nodes

• Due to removal of one-child nodes, search jumps directly to an address bit where a significant decision is to be made => bit position of the next address bit to be inspected must be stored=> bit strings of prefixes must be explicitly stored


Search in a path-compressed trie

Search goes as follows:• Start from the root and descent in the trie under the guidance of the

address bits, but this time only inspect bit positions indicated by the bit position number in the nodes traversed

• When a node marked as a prefix is encountered, comparison with the actual prefix is performed - this is needed, because during the descent in the trie, we may skip some bits

• If a match is found, we proceed traversing the trie and keep the prefix as the best match prefix (BMP) so far

• Search ends when a leaf is encountered or a mismatch found

• BMP is the last matching prefix encountered


A path-compressed trie example (cont.)

In the previous example case, take an address beginning with 010110

• start from root and since its bit position number is 1, inspect the first bit of the address => 1st bit is 0 => go to the left => since this node is marked as a prefix, compare prefix a (“0”) with the corresponding part of the address => they match => keep a as the BMP so far => bit position number of the new node is 3 so skip the 2nd address bit and inspect the 3rd one, which is 0 => proceed left => next node includes a prefix so compare prefix b with the corresponding part of address => no match => stop search => the last recorded BMP is a


Multibit trie

• Drawback of binary (1-bit) trie is that one bit at a time is inspected and the number of memory accesses (in the worst case) can be 32 for IPv4

• Number of lookups can be substantially decreased by using the multibit trie structure, i.e. several bits are inspected at a time

• for example, inspecting four bits at a time would lead to only 8 memory accesses in the worst case for an IPv4 address

• Number of bits (K) to be inspected is called a stride and the stride can be constant or variable

• In a K-bit trie, each node has 2K pointers (children)

• If a route prefix is not a multiple of K, it needs to be expanded to K or its multiples

• Lookup time is O(W/K) and storage requirement O(2 (K-1) NW/K)


Multibit trie example 1

• Prefixes a and d are expanded to length 2 and prefix c has been expanded to length 4 (rest of the prefixes remain unchanged)

• Height of the trie has been decreased and so has the number of memory accesses when doing a search

0 1

a

b

c0

0

0

1

d

e

0

0

0

11

f g h i

0

0

1

11

Uncompressed binary trie

0 1b

00cc

01 10 11e0 1

f g h i00 01 10 11

d

00 11

a a

01 10

d

Variable stride multibit trie

Information stored by a node:Next-hop pointer (if prefix)

Ptr00 Ptr01 Ptr10 Ptr11


Multibit trie example 2

• An alternative multibit trie of the previous example case- prefixes a and d have been expanded to length 3- rest of the prefixes remain the same as before expansion

• When an expanded prefix collides with an existing one, forwarding information of the existing one must be maintained (to respect the longest match)

h h i i00 01 10 11

b00 01 10 11 00 01 10 11

f f g g

e

000 011

a c

001 010

d da da

100 111101 110

Fixed stride multibit trie


Search in a multibit trie

• Search in a multibit trie is essentially the same as search in a binary (1-bit) trie - successively look for longer prefixes that match and the last one found is the longest match prefix for a given address

• Multibit tries do linear search on length as do the binary tries, but the search is faster because the trie is traversed using larger strides

• A multibit trie is a fixed stride system, if all nodes at the same level have the same stride size, otherwise it a variable stride system

• Fixed strides are simpler to implement than variable strides, but usually consume more memory


Choice of stride size and update of tries

• Choice of stride size is a trade-off between search speed and memory consumption

• in the extreme case, a trie with a single level could be made (stride size = 32) and search would take only one memory access, but a huge amount of memory would be required (232 entries for IPv4)

• a natural way to choose stride size and memory consumption is tolet the binary trie structure determine this

• Update bounds determined by stride size

• a multibit trie with several levels allows, by varying stride K, an interesting trade-off between search time, memory consumption and update time - larger strides make faster search => memory consumption increases and updates will require more entries to be modified (due to expansion)


Level compression (LC) trie

• Path-compressed trie is an effective way to compress a trie when nodes are sparsely populated

• LC-tries were developed to compress densely populated tries

• LC-tries combine the path-compression and multibit trie compression to optimize binary trie structures

• first, a binary trie is developed to a “compact” path-compressed trie• second, the largest full binary sub-trie with multilevels is

transformed into a corresponding one-level multibit sub-trie – this process starts from the root node and repeats recursively on each child node of the obtained multibit sub-trie

• all bit strings that are proper prefixes of other ones are removed from the LC-trie meaning that only leaf nodes contain prefixes


LC-trie example

Uncompressedbinary trie 0 1

a

b

c0

0

0

1

d

e

0

0

0

11

f g h i

0

0

1

11Compressedbinary trie

0 1a

b c0 1

3d

f g h i

e

1

0

0

0 0

1

1

1

2

3

14 4

b c

f g h i

eb c

f g h i

e

LC-trie

Prefixes:a - 0*b - 01000*c - 011*d - 1*e - 100*

f - 1100*g - 1101*h - 1110*I - 1111*


Level compression trie (cont.)

• To save memory, all nodes in LC-trie are stored in a single node array • first root, then all nodes at the second level, then all nodes at third level,

and so on

• all the descendants of an internal nodes are stored in consecutive memory locations => an internal node only needs to point to its first descendant

b001 /b1020 /root

i008 /ih007 /hg006 /gf005 /f5324e003 /ec002 /c

PointerSkipBranchIndex• Information stored in each node • branch – number of descendants of a node

(always power of 2)

• skip number – number of bits to be skipped at this node during search operation

• pointer – an internal node points to its first descendant (given as the index value of the first child node) and leaf node points to one entry of another base vector table, where the real prefix and next-hop information are stored


Level compression trie (cont.)

• Each entry of the base vector table includes • complete string of the prefix

• next-hop information• special prefix vector, which

• contains information of strings that are proper prefixes of other strings

• is needed because internal nodes of an LC-trie do not contain pointers to the base vector table

• this information implies whether there exists a longer prefix matching the IPaddress and gives the next-hop information in case of a match

• Lookup time is O(W/K) and memory requirement is O(2 K NW/K)

d=1/ptr_dptr_i1111i

d=1/ptr_dptr_h1110h

Special prefix vector

Next hop

Prefix bit string

Index

a=0/ptr_aptr_b01000b

d=1/ptr_dptr_g1101g

d=1/ptr_dptr_f1100f

d=1/ptr_dptr_e100e

a=0/ptr_aptr_c011c


Multibit tries in hardware

• In core network routers, lookup times are very short and lookup algorithms are implemented in hardware to obtain required speed

• Basic scheme uses two level multibit trie with fixed strides- 24 bits at the first level and 8 at the second level

• In backbone routers, most of the entries have a prefix length of 24 bits or less => longest match prefix found in one memory access in the majority of cases

• Only a small number of sub-entries at the 2nd level

• To save memory, internal nodes not allowed to store prefixes => prefixes corresponding to internal nodes expanded to 2nd level=> result is a multibit trie with disjoint expanded prefixes - 1st level has 224 nodes and is implemented as a table with the same number of entries


Multibit tries in hardware (cont.)

• An entry at the 1st level contains either the forwarding information or a pointer to the corresponding sub-trie at the 2nd level - two bytes needed to store a pointer/forwarding information => a memory bank of 32 Mbytes is needed to store 224 entries

1st memorybank

0

23

31

0

1

Destinationaddress

2nd memorybank

24

8220 entries

224 entries

Forwardinginformation


Multibit tries in hardware (cont.)

• Number of sub-tries at the 2nd level depends on the number of prefixes longer than 24 bits

• 2nd level stride is 8 bits => a sub-trie at the 2nd level has 28=256 leaves

• Size of 2nd memory bank depends on the expected worst case prefix length distribution, e.g. 220 one byte entries (a memory bank of 1 Mbytes) supports a maximum of 212= 4096 sub-tries at the 2nd level

• Lookup requires a maximum of two memory accesses- memory accesses can be pipelined or parallelized to speed up performance

• Since the first stride is 24 bits and leaf pushing is used, updates may take a long time in some cases


New directions in IP lookup

• More efficient lookup schemes have been developed to improve theaverage lookup performance and storage complexity

• Examples of new methods are • Binary search on trie levels, which decomposes the longest prefix

operation into W exact matching operations, each performed on prefixes of equal length

• Multiway or K-way range search, which applies a binary search to best matching prefixes by using two routing entries per prefix and with some precomputation

• Ternary CAM uses a special CAM (Content Addressable Memory), which performs parallel comparisons internally. TCAM stores each W-bit field as a [val, mask] pair and when a bit string is presented to the input, TCAM outputs the location (or address) where a match is found.


New directions in IP lookup (cont.)

• Conventional routers offer the best-effort service by processing each incoming packet in the same way. New applications require different QoS levels and to meet these requirements new mechanisms, such as admission control, resource reservation and per-flow queuing, need to be implemented in routers.

• Routers are required to distinguish and classify incoming traffic into different flows

• Flows are specified by rules and each rule consists of operations for comparing packet fields with certain values

• Packet fields to be inspected are collected from different protocols => packet classification


Comparison of some lookup schemes

Source: Proceedings of the IEEE, vol. 90, No. 9, 2002

W - length of address in bits, N - number of prefixes in a prefix set,K - stride size

-O(N)O(1)TCAM

O(N)O(N)O(log2W)K-way rang search

O(log2W)O(Nlog2W)O(log2W)Binary search on tries level

-O(2KNW/K)O(W/K)LC-trie

O(W/K+2K)O(2KNW/K)O(W/K)K-stride multibit trie

O(W)O(N)O(W)Path compressed trie

O(W)O(NW)O(W)Binary trie

UpdateMemoryWorst caselookupScheme


Lookup scalability and IPv6

• On scalability point of view, important aspects are the number of entries in a lookup table and the prefix length

• Multibit tries improve lookup speed with respect to binary tries, but only by a constant factor on the length dimension=> multibit tries scale badly to longer addresses (128 bit in IPv6)

• Binary search on tries level has logarithmic complexity with respect to prefix length => scalability very good for IPv6

• Range search has logarithmic lookup complexity with respect to the number of entries, but independent of prefix length => if the number of entries does not grow excessively, range search is scalable for IPv6

1

11 - 1P. Raatikainen Switching Technology / 2003

Introduction to MultiwavelengthOptical Networks


Source: Stern-Bala (1999), Multiwavelength Optical Networks


Contents

• The Big Picture• Network Resources

• Network Connections

2


Optical network

• Why optical networks?– “The information superhighway is still a dirt road; more accurately, it is a

set of isolated multilane highways with cow paths for entrance.”

• Definition: An optical network is a telecommunications network– with transmission links that are optical fibers, and

– with an architecture designed to exploit the unique features of fibers

• Thus, the term optical network (as used here)– does not necessarily imply a purely optical network,

– but it does imply something more than a set of fibers terminated byelectronic switches

• The “glue” that holds the purely optical network together consists of– optical network nodes (ONN) connecting the fibers within the network– network access stations (NAS) interfacing user terminals and other

nonoptical end-systems to the network


Network categories

Multiwavelength optical network= WDM network= optical network utilizing wavelength division multiplexing (WDM)

– Transparent optical network = purely optical network

• Static network = broadcast-and-select network

• Wavelength Routed Network (WRN)

• Linear Lightwave Network (LLN) = waveband routed network

– Hybrid optical network = layered optical network

• Logically Routed Network (LRN)

3


Physical picture of the network

NAS

NAS

NAS

NAS

NAS

NAS

Work-station

Multimediaterminal

Super-computer

Multimediaterminal

LAN

ONN

LANLAN

ATM

ATM

ATM

ATM

ONN - Optical Network NodeNAS - Network Access StationLAN - Local Area Network


Wide area optical networks - a wish list

•Connectivity– support of a very large number of stations

and end systems

– support of a very large number ofconcurrent connections including multipleconnections per station

– efficient support of multi-cast connections

•Performance– high aggregate network throughput

(hundreds of Tbps)

– high user bit rates (few Gbps)

– small end-to-end delay

– low error rate / high SNR

– low processing load in nodes and stations

– adaptability to changing and unbalancedloads

– efficient and rapid means of faultidentification and recovery

•Structural features– scalability

– modularity

– survivability (fault tolerance)

•Technology/cost issues– access stations: small number of

optical transceivers per station andlimited complexity of opticaltransceivers

– network: limited complexity of theoptical network nodes, limitednumber and length of cables andfibers, and efficient use (and reuse)of optical spectrum

4


Optics vs. electronics

Optical domain•photonic technology is well suited tocertain simple (linear) signal-routing andswitching functions

•optical power combining, dividing andfiltering

•wavelength multiplexing,demultiplexing and routing

•channelizing needed to make efficientuse of enormous bandwidth of the fiber

•by wavelength division multiplexing(WDM)

•many signals operating on differentwavelengths share each fiber

=> optics is fast but dumb - connectivity bottleneck

Electrical domain• electronics is needed to perform morecomplex (nonlinear) functions

•signal detection, regeneration andbuffering

•logic functions (e.g. reading andwriting packet headers)

• however, these complex functions limitthe throughput

• electronics also gives a possibility toinclude in-band control information (e.g.in packet headers)

•enabling a high degree of virtualconnectivity

• easier to control

=> electronics is slow but smart - electronic bottleneck


Optics and electronics

Hybrid approach:– a multiwavelength purely optical network as a physical foundation

– one or more logical networks (LN) superimposed on the physical layer, each

• designed to serve some subset of user requirements and• implemented as an electronic overlay

– electronic switching equipment in the logical layer acts as a middleman

• taking the high-bandwidth transparent channels provided by the physical layerand organizing them into an acceptable and cost-effective form

Why this hybrid approach ?– purely optical wavelength selective switches:

• huge aggregate throughput of few connections

– electronic packet switches:

• large number of relatively low bit rate virtual connections

– hybrid approach exploits the unique capabilities of optical and electronic switchingwhile circumventing their limitations

5


Example LAN interconnection

• Consider a future WAN serving as a backbone that interconnects a largenumber of high-speed LANs (say 10,000), accessing the WAN throughLAN gateways (with aggregate traffic of tens of Tbps)

• Purely optical approach

– each NAS connects its LAN to the other LAN’s through individualoptical connections ⇒ 9,999 connections per NAS

– this is far too much for current optical technology

• Purely electronic approach

– electronics easily supports required connectivity via virtual connections

– however, the electronic processing bottleneck in the core network doesnot allow such traffic

• Hybrid approach: both objectives achieved, since

– LN composed of ATM switches provides the necessary connectivity

– optical backbone at the physical layer supports the required throughput


Contents

• The Big Picture

• Network Resources– Network Links: Spectrum Partitioning– Layers and Sublayers

– Optical Network Nodes

– Network Access Stations

– Electrical domain resources


6


Network links

A large number of concurrent connections can be supported on each networklink through successive levels of multiplexing

– Space division multiplexing in the fiber layer:

• a cable consists of several (sometimes more than 100) fibers, whichare used as bi-directional pairs

– Wavelength division multiplexing (WDM) in the optical layer:

• a fiber carries connections on many distinct wavelengths (λ-channels)

• assigned wavelengths must be spaced sufficiently apart to keepneighboring signal spectra from overlapping (to avoid interference)

– Time division multiplexing (TDM) in the transmission channel sublayer:

• a λ-channel is divided (in time) into frames and time-slots

• each time-slot in a frame corresponds to a transmission channel,which is capable of carrying a logical connection

• location of a time-slot in a frame identifies a transmission channel


Fiber resources

{ Transmission channel out

λ-channels out

......

......

Cable Fibers Wavebands

{ Transmission channel in

λ-channelsin

Space Wavelength Time

7


Optical spectrum

• Since wavelength λλ and frequency f are related by f λ λ = = c, where c is thevelocity of light in the medium, we have the relation

• Thus, 10 GHz ≈ 0.08 nm and 100 GHz ≈ 0.8 nm in the range of 1,550 nm,where most modern lightwave networks operate

• The 10-GHz channel spacing is sufficient to accommodate λ-channelscarrying aggregate digital bit rates on the order of 1 Gbps- modulation efficiency of 0.1 bps/Hz typical for optical systems

• The 10-GHz channel spacing is suitable for optical receivers, but much toodense to permit independent wavelength routing at the network nodes- for this, 100-GHz channel spacing is needed.

• In a waveband routing network, several λ-channels (with 10-GHz channelspacing) comprise an independently routed waveband (with 100-GHzspacing between wavebands).

2 λ

λ∆−≈∆ cf


Wavelength partitioning of the opticalspectrum

λλ-channel spacing for separability at receivers

λλ-channel spacing for separability at network nodes

λλ1 λλ2 λλm

...

10 GHz0.08 nm

Unusable spectrum

f/λ λ [GHz/nm]

λλ1 λλ2 λλm

...

100 GHz/0.8 nm

f/λλ

8


Wavelength and waveband partitioningof the optical spectrum

λλ1,1 λλ2,1 λλ10,1

...

10 GHz

100 GHz/0.8 nm

w1 wmw2

100 GHz/0.08 nm

...f/λλ


Network based on spectrum partitioning

λλ1, λλ2 ,..., λλm

Single waveband

λλm

λλ2

λλ1

w1

w2

wm

Wavelength-routed

...

λλ1,m -λλ10,m

λλ1,10 -λλ10,2

λλ1,1 -λλ10,1

w1

w2

wm

Waveband-routed

...

9


Contents

• The Big Picture

• Network Resources– Network Links: Spectrum Partitioning

– Layers and Sublayers– Optical Network Nodes





Layered view of optical network (1)

FIBERLAYER

OPTICALLAYER

FIBER SECTION

FIBER LINK

OPTICAL/WAVEBAND PATH

λλ-CHANNEL

OPTICAL CONNECTION

TRANSMISSION CHANNEL

LOGICAL CONNECTION

LOGICAL PATH

VIRTUAL CONNECTION

Logical layer

Physical layer

Sub- layers

10


Layered view of optical network (2)

NAS NAS

TP

RP

OT

ORONN

OA OA

ONNTP

RP

OT

ORE O E O

Fiber Section

Fiber Link

Optical/Wavelength Path

λλ-channel

Transmission Channel

Logical Connection

Optical Connection

NetworkLink

AccessLink

- E Electronic - OR Optical Receiver- O Optical - OT Optical Transmitter- OA Optical Amplifier - RP Reception Processor- ONN Optical Network Node - TR Transmission Processor


Layers and sublayers

• Main consideration in breaking down optical layer into sublayers is toaccount for

– multiplexing

– multiple access (at several layers)

– switching

• Using multiplexing– several logical connections may be combined on a λ-channel originating

from a station

• Using multiple access– λ-channels originating from several stations may carry multiple logical

connections to the same station

• Through switching– many distinct optical paths may be created on different fibers in the

network, using (and reusing) λ-channels on the same wavelength

11


Typical connection

ES = End SystemLSN = Logical Switching NodeNAS = Network Access NodeONN = Optical Network NodeOA = Optical Amplifier

ONN

ONN

Virtual Connection

Logical Path

Logical Connection

Optical Connection

ONN ONN ONN

LSN

NAS

ES

LSN

NAS

LSN

NAS

ES

Logical Connection

Optical Connection

ONN

OA

OA


Contents

• The Big Picture


– Layers and Sublayers

– Optical Network Nodes– Network Access Stations



12


Optical network nodes (1)

• Optical Network Node (ONN) operates in the optical pathsublayer connecting N input fibers to N outgoing fibers

• ONNs are in the optical domain

• Basic building blocks:

– wavelength multiplexer (WMUX)

– wavelength demultiplexer (WDMUX)

– directional coupler (2x2 switch)

• static

• dynamic

– wavelength converter (WC)

12

1′′2′′

N N′′

input fibers output fibers



• Static nodes– without wavelength selectivity

• NxN broadcast star (= star coupler)• Nx1 combiner• 1xN divider

– with wavelength selectivity

• NxN wavelength router (= Latin router)• Nx1 wavelength multiplexer (WMUX)

• 1xN wavelength demultiplexer (WDMUX)

13



• Dynamic nodes

– without wavelength selectivity (optical crossconnect (OXC))

• NxN permutation switch• RxN generalized switch• RxN linear divider-combiner (LDC)

– with wavelength selectivity

• NxN wavelength selective crossconnect (WSXC) with Mwavelengths

• NxN wavelength interchanging crossconnect (WIXC)with M wavelengths

• RxN waveband selective LDC with M wavebands


Wavelength multiplexer anddemultiplexer

WDMUX

λλ1,…,λλ4

λλ1

λλ2

λλ3

λλ4

WMUX

λλ1,…,λλ4

λλ1

λλ2

λλ3

λλ4

14


Directional Coupler (1)

• Directional coupler (= 2x2 switch) is an optical four-port– ports 1 and 2 designated as input ports

– ports 1’ and 2’ designated as output ports

• Optical power– enters a coupler through fibers attached to input ports,

– divided and combined linearly– leaves via fibers attached to output ports

• Power relations for input signal powers P1 and P2 and outputpowers P1′ and P2′ are given by

• Denote the power transfer matrix by A = [aij]2221212

2121111

PaPaP

PaPaP

+=+=

′

′ 1

2

1′′

2′′

a11

a21

a22

a12


Directional Coupler (2)

• Ideally, the power transfer matrix A is of the form

• If parameter α is fixed, the device is static, e.g. with α = 1/2 andsignals present at both inputs, the device acts as a 2x2 star coupler

• If α can be varied through some external control, the device isdynamic or controllable, e.g. add-drop switch

• If only input port 1 is used (i.e., P2 = 0),the device acts as a 1x2 divider

• If only output port 1’ is used (and port 2’ isterminated), the device acts as a 2x1 combiner

10 ,1

1≤≤

−−

= ααα

ααA

1

2

1′′

2′′

11−−αααααα11−−αα

15


Add-drop switch

OT OR

Add-drop state

OT OR

Bar state


Broadcast star

• Static NxN broadcast star with Nwavelengths can carry

– N simultaneous multi-cast opticalconnections (= full multipoint opticalconnectivity)

• Power is divided uniformly

• To avoid collisions each input signalmust use different wavelength

• Directional coupler realization– (N/2) log2N couplers needed

1

2 2′′

3

4

λλ1

λλ2

λλ3

λλ4

3′′

4′′

1′′λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

11//N11//N

11//N11//N

1

2

3

4

2′′

3′′

4′′

1′′11//211//2

11//211//2

11//211//2

broadcast star realizedby directional couplers

16


Wavelength router

• Static NxN wavelength routerwith N wavelengths can carry

– N2 simultaneous unicastoptical connections (= fullpoint-to-point opticalconnectivity)

• Requires

– N 1xN WDMUX’s

– N Nx1 WMUX’s

1

2 2′′

3

4

3′′

4′′

1′′λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

WDMUX’s WMUX’s


Crossbar switch

• Dynamic RxN crossbar switch consists of

– R input lines

– N output lines

– RN crosspoints

• Crosspoints implemented bycontrollable optical couplers

– RN couplers needed

• A crossbar can be used as

– a NxN permutation switch(then R = N) or

– a RXN generalized switch

1

2

2′

3

4

3′ 4′1′crossbar used as

a permutation switch

17


Permutation switch

• Dynamic NxN permutation switch(e.g. crossbar switch)

– unicast optical connectionsbetween input and output ports

– N! connection states (ifnonblocking)

– each connection state can carry Nsimultaneous unicast opticalconnections

– representation of a connection stateby a NxN connection matrix

1

2

3

4

2′ 3′ 4′1′

inpu

t por

ts

output ports

1

1

1

1

1

2 2′

3

4

3′

4′

1′


Generalized switch

=otherwise ,0

on is )(switch if ,1 i,ja NR

ij

• Dynamic RxN generalized switch (e.g.crossbar switch)

– any input/output pattern possible

– 2NR connection states– each connection state can carry (at most)

R simultaneous multicast opticalconnections

– a connection state represented by a RxNconnection matrix

• Input/output power relation P’ = AP withNxR power transfer matrix A = [aij], where

1

2

3

4

2′ 3′ 4′1′

inpu

t por

ts

output ports

1

1

1

1

1

1

1 1

1

2 2′′

3

4

3′′

4′′

1′′11//N11//N

11//N11//N

11//R11//R11//R

11//R

18


Linear Divider-Combiner (LDC)

• Linear Divider-Combiner (LDC) isa generalized switch that

– controls power-dividing andpower-combining ratios

– less inherent loss than in crossbar

• Power-dividing and power-combining ratios

– δδij = fraction of power from input port j directed to output port i’– σσij = fraction of power from input port j combined onto output port i

• In an ideal case of lossless couplers, we have constraints

• The resulting power transfer matrix A = [aij] is such that

1 and 1 == ∑∑j

iji

ij σδ

ijijija σδ=

1

2 2′′

3

4

3′′

4′′

1′′δδ1111δδ2121δδ3131δδ4141

σσ4141σσ4242σσ4343σσ4444


LDC and generalized switch realizations

directional couplers

δ δ - σσ linear divider-combiner

Generalized optical switch

1xnsplitter

...

1 2 rn1 n2 nr

21 22 2r

11 12 1r

1

2

n

...

...

rx1combiner

19


Wavelength selective cross-connect(WSXC)

• Dynamic NxN wavelength selective crossconnect(WSXC) with M wavelengths

– includes N 1xM WDMUXs,M NxN permutation switches,and N Mx1 WMUXs

– (N!)M connection statesif the permutation switchesare nonblocking

– each connection state cancarry NM simultaneousunicast optical connections

– representation of a connectionstate by M NxN connection matrices

2′′

3′′

4′′

1′′

WDMUX’s WMUX’s

1

2

3

4

λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

optical switches


Wavelength interchanging cross-connect(WIXC)

• Dynamic NxN wavelength interchanging crossconnect(WIXC) with M wavelengths

– includes N 1xM WDMUXs, 1 NM x NM permutationswitch, NM WCs, and N Mx1 WMUXs

– (NM)! connection states ifthe permutation switch isnonblocking

– each connection state cancarry NM simultaneousunicast connections

– representation of a connectionstate by a NMxNMconnection matrix WDMUX’s WMUX’s

optical switch

WC’s

1

2 2′′

3

4

3′′

4′′

1′′λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

λλ1,… ,λλ4

20


Waveband selective LDC

• Dynamic RxN waveband selective LDC with M wavebands

– includes R 1xM WDMUXs, M RxN LDCs, and N Mx1 WMUXs

– 2RNM connection states (if usedas a generalized switch)

– each connection state cancarry (at most) RMsimultaneous multi-castconnections

– representation of aconnection state by a M RxNconnection matrices

WDMUX’s WMUX’s

2′′

3′′

4′′

1′′1

2

3

4

w1,… ,w4

w1,… ,w4

w1,… ,w4

w1,… ,w4

w1,… ,w4

w1,… ,w4

w1,… ,w4

w1,… ,w4

LDC’s


Contents

• The Big Picture




– Network Access Stations– Electrical domain resources


21


Network access stations (1)

• Network Access Station (NAS) operates in the logicalconnection, transmission channel and λ-channel sublayers

• NASs are the gateways between the electrical and opticaldomains

• Functions:

– interfaces the external LC ports tothe optical transceivers

– implements the functions necessaryto move signals between the electricaland optical domains

electronic wires optical fibers

12

1′′L

L′′2′′

e/o

a

a’


Network access stations (2)

• Transmitting side components:– Transmission Processor (TP) with a number of LC input ports and

transmission channel output ports connected to optical transmitters(converts each logical signal to a transmission signal)

– Optical Transmitters (OT) with a laser modulated by transmissionsignals and connected to a WMUX (generates optical signals)

– WMUX multiplexes the optical signals to an outbound access fiber

• Receiving side components:– WDMUX demultiplexes optical signals from an inbound access fiber and

passes them to optical receivers

– Optical Receivers (OR) convert optical power to electrical transmissionsignals, which are corrupted versions of the original transmitted signals

– Reception Processor (RP) converts the corrupted transmission signalsto logical signals (e.g. regenerating digital signals)

22


Elementary network access station

TP

RP

OT

OT

OR

OR

ONN

NAS

WMUX

WDMUX

e/o

access fiber pair

logi

cal c

onne

ctio

n po

rts

internodal fiber pairs


Nonblocking network access station

TP

RP

ONN

NAS

WMUX’s

WDMUX’s

e/o

OT

OT

OR

OR

logi

cal c

onne

ctio

n po

rts

access fiber pairs

internodal fiber pairs

23


Wavelength add-drop multiplexer(WADM)

OT

λλ1

λλ2

λλm

OR

...

λλ1

OT ORλλ2

OT ORλλm

...

TP/RP

...

NAS

WADMW

DM

UX

WM

UX


Contents

• The Big Picture





– Electrical domain resources• Network Connections

24


End System

• End systems are in the electrical domain

• In transparent optical networks, they aredirectly connected to NASs

– purpose is to create full logicalconnectivity between end stations

• In hybrid networks, they are connected toLSNs

– purpose is to create full virtualconnectivity between end stations

access wires

a

a’


Logical Switching Node (LSN)

• Logical switching nodes (LSN) are needed in hybrid networks,i.e. logically routed networks (LRN)

• LSNs are in the electrical domain

• They may be e.g.

– SONET digital cross-connect systems(DCS), or

– ATM switches, or

– IP routers

12

1′′2′′

N N′′

input wires output wires

25


Logically routed network

Physical layer

Logical layer

LS

NAS

ONN

LSN

Logicallyswitchingnode

LSN - Logically Switching NodeLS - Logical SwitchNAS - Network Access StationONN - Optical Network Node


Contents

• The Big Picture

• Network Resources

• Network Connections– Connectivity– Connections in various layers

– Example: realizing full connectivity between fiveend systems

26


Connectivity

• Transmitting side:

– one-to-one• (single) unicast

– one-to-many• multiple unicasts

• (single) multicast

• multiple multicasts

• Network wide:

– point-to-point

– multipoint

• Receiving side:

– one-to-one• (single) unicast

• (single) multicast– many-to-one

• multiple unicasts

• multiple multicasts


Connection Graph (CG)

• Representing point-to-point connectivity between end systems

1

Connection graph

2

4 3

Bipartite representation

1

2

4

3

1

2

4

3

transmittingside

receivingside

27


Connection Hypergraph (CH)

• Representing multipoint connectivity between end systems

1

Connection hypergraph

2

4 3

E1

E2

Tripartite representation

1

2

4

3

1

2

4

3

transmittingside

receivingside

E1

hyper-edges

E2


Contents

• The Big Picture


• Network Connections– Connectivity

– Connections in various layers– Example: realizing full connectivity between five

end systems

28


Connections in various layers

• Logical connection sublayer

– Logical connection (LC) is a unidirectional connection betweenexternal ports on a pair of source and destination networkaccess stations (NAS)

• Optical connection sublayer

– Optical connection (OC) defines a relation between onetransmitter and one or more receivers, all operating in the samewavelength

• Optical path sublayer

– Optical path (OP) routes the aggregate power on one wavebandon a fiber, which could originate from several transmitters withinthe waveband


Notation for connections in variouslayers

• Logical connection sublayer– [a, b] = point-to-point logical connection from an external port on station a

to one on station b– [a, {b, c, …}] = multi-cast logical connection from a to set { b, c, …}

• station a sends the same information to all receiving stations

• Optical connection sublayer– (a, b) = point-to-point optical connection from station a to station b– (a, b)k = point-to-point optical connection from a to b using wavelength λk– (a,{ b,c,…} ) = multi-cast optical connection from a to set { b,c,…}

• Optical path sublayer– ⟨a, b⟩ = point-to-point optical path from station a to station b– ⟨a, b⟩k = point-to-point optical path from a to b using waveband wk– ⟨a, {b, c, …} ⟩ = multi-cast optical path from a to set { b,c,…}

29


Example of a logical connection betweentwo NASs

ONN

TP RP

Electrical Electrical

Optical Opticalλλ1 ... λλm λλm ... λλ1 WMUX WDMUX

OT OR

NAS NAS

w2 ONN

ONNw1

Logical connection [A,B]

Transmission channel

Optical connection (A,B)λλ1

λλ-channel

Optical path <A,B>w1


Contents

• The Big Picture


• Network Connections– Connectivity

– Connections in various layers

– Example: realizing full connectivity betweenfive end systems

30


Example: realization of full connectivitybetween 5 end systems

5 2

4 3

1


Solutions

• Static network based on star physical topology– full connectivity in the logical layer (20 logical connections)

– 4 optical transceivers per NAS, 5 NASs, 1 ONN (broadcast star)

– 20 wavelengths for max throughput by WDM/WDMA

• Wavelength routed network (WRN) based on bi-directional ring physicaltopology

– full connectivity in the logical layer (20 logical connections)

– 4 optical transceivers per NAS, 5 NASs, 5 ONNs (WSXCs)

– 4 wavelengths (assuming elementary NASs)

• Logically routed network (LRN) based on star physical topology andunidirectional ring logical topology

– full connectivity in the virtual layer but only partial connectivity in the logicallayer (5 logical connections)

– 1 optical transceiver per NAS, 5 NASs, 1 ONN (WSXC), 5 LSNs

– 1 wavelength

31


Static network realization

5x5 broadcast star LCG

1

2

3

4

5

1

25

4 3

1

25

4 3


Wavelength routed network realization

3x3 WSXC 1

2

3

4

5

1

25

4 3

1

25

4 3

LCG

32


Logically routed network realization

5x5 WSXC

LSN

1

2

3

4

5

1

25

4 3

1

25

4 3

LCG


Multiwavelength OpticalNetwork Architectures


Source: Stern-Bala (1999), Multiwavelength Optical Networks



• Static networks• Wavelength Routed Networks (WRN)• Linear Lightwave Networks (LLN)• Logically Routed Networks (LRN)


Static networks

• Static network, also called broadcast-and-select network, is apurely optical shared medium network

• passive splitting and combining nodes are interconnected by fibers toprovide static connectivity among some or all OTs and ORs

• OTs broadcast and ORs select

• Broadcast star network is an example of such a static network• star coupler combines all signals and broadcasts them to all ORs

- static optical multi-cast paths from any station to the set of all stations- no wavelength selectivity at the network node

• optical connection is created by tuning the source OT and/or destinationOR to the same wavelength

• two OTs must operate at different wavelengths (to avoid interference)- this is called the distinct channel assignment (DCA) constraint

• however, two ORs can be tuned to the same wavelength- by this way, optical multi-cast connections are created


Realization of logical connectivity

• Methods to realize full point-to-point logical connectivity in abroadcast star with N nodes:

• WDM/WDMA- a whole λλ-channel allocated for each LC- N(N-1) wavelengths needed (one for each LC)- N-1 transceivers needed in each NAS

• TDM/TDMA- 1/[N(N-1)] of a λλ-channel allocated for each LC- 1 wavelength needed- 1 transceiver needed in each NAS

• TDM/T-WDMA- 1/(N-1) of a λλ-channel allocated for each LC- N wavelengths needed (one for each OT)- 1 transceiver needed in each NAS, e.g. fixed OT and tunable OR(FT-TR), or tunable OT and fixed OR (TT-FR)


Broadcast star using WDM/WDMA

TPOT

star coupler

OT

TPOTOT

TPOTOT

[1,2][1,3]

[2,1][2,3]

[3,1][3,2]

LCs

RPOROR

RPOROR

RPOROR

[2,1][3,1]

[1,2][3,2]

[1,3][2,3]

LCsNAS 1

λλ1

λλ2

λλ3

λλ4

λλ5

λλ6

λλ3

λλ5

λλ1

λλ6

λλ2

λλ4

λλ1,2

λλ3,4

λλ5,6

λλ1-6

λλ1-6

λλ1-6


Broadcast star using TDM/TDMA

TP OT

TP OT

TP OT

[1,2][1,3]

[2,1][2,3]

[3,1][3,2]

LCs

RPOR

RPOR

RPOR

LCsNAS 1

λλ1

λλ1

λλ1

λλ1

λλ1

λλ1

[2,1][3,1]

[1,2][3,2]

[1,3][2,3]

star coupler


Effect of propagation delay onTDM/TDMA

A TDM/TDMA schedule

[1,2]1 [1,2]2 [1,3]1 [1,2]1 [1,2]2 [1,3]1

[2,3]1

From 1 From 1

[2,3]2

From 2 From 2

From 1 From 1From 2 From 2

From 1 From 1From 2 From 2

OT1

OT2

OR2

OR3

Coupler

F1 F2

F1 F2

F1 F2


Broadcast star using TDM/T-WDMA inFT-TR mode

TP OT

TP OT

TP OT

[1,2][1,3]

[2,1][2,3]

[3,1][3,2]

LCs

RPOR

RPOR

RPOR

LCsNAS 1

λλ1

λλ2

λλ3

λλ1-3

λλ1-3

λλ1-3

fixed tunable

[2,1][3,1]

[1,2][3,2]

[1,3][2,3]

star coupler

λλ2

λλ3

λλ1

λλ3

λλ1

λλ2


Broadcast star using TDM/T-WDMA inTT-FR mode

TP OT

TP OT

TP OT

[1,2][1,3]

[2,1][2,3]

[3,1][3,2]

LCs

RPOR

RPOR

RPOR

LCsNAS 1

λλ2,3

λλ1,3

λλ1,2

λλ1-3

λλ1-3

λλ1-3

tunable fixed

[2,1][3,1]

[1,2][3,2]

[1,3][2,3]

star coupler

λλ1

λλ2

λλ3

λλ2

λλ3

λλ3

λλ1

λλ1

λλ2


Channel allocation schedules for circuitswitching

[1,2][1,3][2,1][2,3][3,1][3,2]

WDM/WDMA

[1,2][1,3][2,1][2,3][3,1][3,2]

[1,2][1,3][2,1][2,3][3,1][3,2]

λλ1λλ2

λλ3

λλ4

λλ5

λλ6

frame

TDM/TDMA

[1,2] [1,3] [2,1]λλ1 [2,3] [3,1] [3,2] [1,2] [1,3] [2,1] [2,3] [3,1] [3,2]

frame

[1,2][1,3][2,1][2,3][3,1][3,2]

[1,2][2,3][3,1]

TDM/T-WDMA with FT-TR

[1,3][2,1][3,2]

[1,2][2,3][3,1]

λλ1λλ2

λλ3

frame

[1,3][2,1][3,2]

[2,1][3,2][1,3]

TDM/T-WDMA with TT-FR

[3,1][1,2][2,3]

[2,1][3,2][1,3]

λλ1λλ2

λλ3

frame

[3,1][1,2][2,3]

Channel allocation schedule (CAS) should be- realizable = only one LC per each OT and time-slot- collision-free = only one LC per each λ and time-slot - conflict-free = only one LC per each OR and time-slot


Packet switching in the optical layer

• Fixed capacity allocation, produced by periodic frames, is welladapted to stream-type traffic. However, in the case of bursty packettraffic this approach may produce a very poor performance

• By implementing packet switching in the optical layer, it ispossible to maintain a very large number of LCs simultaneouslyusing dynamic capacity allocation- packets are processed in TPs/RPs of the NASs (but not in ONNs)- TPs can schedule packets based on instantaneous demand- as before, broadcast star is used as a shared medium- control of this shared optical mediumrequires a Medium AccessControl (MAC) protocol

TP

RP

OT

OR

ONNMACNAS equipped forpacket switching


Additional comments on static networks

• The broadcast-and-select principle cannot be scaled to largenetworks for three reasons:

– Spectrum use: Since all transmissions share the same fibers, thereis no possibility of optical spectrum reuse => the required spectrumtypically grows at least proportionally to the number of transmittingstations

– Protocol complexity: Synchronization problems, signalingoverhead, time delays, and processing complexity all increaserapidly with the number of stations and with the number of LCs.

– Survivability: There are no alternate routes in case of a failure.Furthermore, a failure at the star coupler can bring the wholenetwork down.

– For these reasons, a practical limit on the number of stations in abroadcast star is approximately 100


Contents



Wavelength Routed Networks (WRN)

• Wavelength routed network (WRN) is a purely optical network– each λ-channel can be recognized in the ONNs (= wavelength

selectivity) and routed individually– ONNs are typically wavelength selective crossconnects (WSXC)

• network is dynamic (allowing switched connections)

• a static WRN (allowing only dedicated connections) can be built upusing static wavelength routers

• All optical paths and connections are point-to-point– each point-to-point LC corresponds to a point-to-point OC

– full point-to-point logical/optical connectivity among N stations requiresN-1 transceivers in each NAS

– multipoint logical connectivity only possible by several point-to-pointoptical connections using WDM/WDMA


Static wavelength routed star

• Full point-to-point logical/optical connectivity in a staticwavelength routed star with N nodes can be realized by

– WDM/WDMA• a whole λ-channel allocated for each LC

• N-1 wavelengths needed- spectrum reuse factor is N (= N(N-1) optical connections / N-1 wavelengths)

• N-1 transceivers needed in each NAS


Static wavelength routed star usingWDM/WDMA

TPOT

wavelength router

OT

TPOTOT

TPOTOT

[1,2][1,3]

[2,1][2,3]

[3,1][3,2]

LCs

RPOROR

RPOROR

RPOROR

[2,1][3,1]

[1,2][3,2]

[1,3][2,3]

LC’NAS 1

λλ1

λλ2

λλ2

λλ1

λλ1

λλ2

λλ2

λλ1

λλ1

λλ2

λλ2

λλ1

λλ1,2

λλ1,2

λλ1,2

λλ1,2

λλ1,2

λλ1,2


Routing and channel assignment

• Consider a WRN equipped with WSXCs (or wavelength routers)– no wavelength conversion possible

• Establishing an optical connection requires– channel assignment

– routing

• Channel assignment (executed in the λ-channel sublayer) involves– allocating an available wavelength to the connection and– tuning the transmitting and receiving station to the assigned wavelength

• Routing (executed in the optical path sublayer) involves– determining a suitable optical path for the assigned λ-channel and

– setting the switches in the network nodes to establish that path


Channel assignment constraints

• Following two channel assignment constraints apply to WRNs• wavelength continuity: wavelength of each optical connection

remains the same on all links it traverses from source to destination• this is unique to transparent optical networks, making routing and

wavelength assignment a more challenging task than the relatedproblem in conventional networks

• distinct channel assignment (DCA): all opticalconnections sharing a common fiber must beassigned distinct λ-channels (i.e. distinct wavelengths)- this applies to access links as well as internodal links- although DCA is necessary to ensure distinguishabilityof signals on the same fiber, it is possible (and generallyadvantageous) to reuse the same wavelength onfiber-disjoint paths

1

2

3

1

2

3

1

2

3

1

2

3


Routing and Channel Assignment (RCA)problem

• Routing and channel assignment (RCA) is the fundamentalcontrol problem in large optical networks

– Generally, the RCA problem for dedicated connections can be treatedoff-line => computationally intensive optimization techniques areappropriate

– On the other hand, RCA decisions for switched connections must bemade rapidly, and hence suboptimal heuristics must normally be used

dedicated

1 3 5

2 4 6

switched 1

1 3 5

2 4 6

(1,3)1 (3,5)1

(4,6)2

switched 2

1 3 5

2 4 6

(1,3)1 (3,5)1

(4,6)2


Example bi-directional ring withelementary NASs

• Consider a bi-directional ring of 5 nodes andstations with single access fiber pairs

• Full point-to-point logical/optical connectivityrequires- 4 wavelengths => spectrum reuse factor is20/4 = 5- 4 transceivers in each NAS

RCA

2L 3L 4R 1R --4L 2R 1R -- 3L3R 4R -- 2L 1L1R -- 3L 4L 2R-- 1L 2L 3R 4R1 2 3 4 5

543211 523

12

Fiber from ONN1 to ONN2

1

2

3 4

5L R

physical topology


Example bi-directional ring withnonblocking NASs

• Consider a bi-directional ring of 5 nodes andstations with two access fiber pairs

• Full point-to-point logical/optical connectivityrequires- 3 wavelengths => spectrum reuse factor is20/3 = 6.67- 4 transceivers in each NAS

RCA

1L 3L 1R 3R --2L 3R 2R -- 3L2R 1R -- 2L 1L1R -- 1L 3L 3R-- 1L 2L 2R 1R1 2 3 4 5

543211 523

12

Fiber from ONN1 to ONN2

1

2

3 4

5L R

physical topology


Example mesh network with elementaryNASs

• Consider a mesh network of 5 nodes andstations with single access fiber pairs

• Full point-to-point logical/opticalconnectivity requires

– 4 wavelengths=> spectrum reuse factor is 20/4 = 5

– 4 transceivers in each NAS– despite the richer physical topology, no

difference with the corresponding bi-directional ring (thus, the access fibersare the bottleneck)

RCA?

5

1 2

4 3

physical topology


Example mesh network with nonblockingNASs

• Consider a mesh network of 5 nodes andstations with three/four access fiber pairs

• Full point-to-point logical/opticalconnectivity requires

– only 2 wavelengths=> spectrum reuse factor is 20/2 = 10

– 4 transceivers in each NAS

RCA?

5

1 2

4 3

physical topology


Contents

• Static networks• Wavelength Routed Networks (WRN)

• Linear Lightwave Networks (LLN)• Logically Routed Networks (LRN)


Linear Lightwave Networks (LLN)

• Linear lightwave network (LLN) is a purely optical network– nodes perform (only) strictly linear operations on optical signals

• This class includes– both static and wavelength routed networks– but also something more

• The most general type of LLN has waveband selective LDC nodes– LDC performs controllable optical signal dividing, routing and combining– these functions are required to support multipoint optical connectivity

• Waveband selectivity in nodes means that– optical path layer routes signals as bundles that contain all λ-channels

within one waveband

• Thus, all layers of connectivity and their interrelations must beexamined carefully


Routing and channel assignmentconstraints

• Two constraints of WRNs need also to be satisfied by LLNs• Wavelength continuity: wavelength of each optical connection remains

the same on all the links it traverses from source to destination• Distinct channel assignment (DCA): all optical connections sharing a

common fiber must be assigned distinct λ-channels

• Additionally, the following two routing constraints apply to LLNs• Inseparability: channels combined on a single fiber and situated within

the same waveband cannot be separated within the network- this is a consequence of the fact that the LDCs operate on theaggregate power carried within each waveband

• Distinct source combining (DSC): only signals from distinct sourcesare allowed to be combined on the same fiber- DSC condition forbids a signal from splitting, taking multiple paths, and thenrecombining with itself- otherwise, combined signals would interfere with each other


Inseparability

H

A B

D E

C

GF

S1

S2

S1

S2a

1

2

3

1*

2*

3*

H

A B

D E

C

GF

S2

S1

S2

a

1

2

3

1*

2*

3*

S1


Two violations of DSC

A

C

B

A

C

B


Inadvertent violation of DSC

H

A B

D E

C

GF

S3

S1 + S2S1

d

1

2

3

1*

2*

3*S1 + S2

S1 + S2 + S3

S1 + S2 + S3

S1 + S2 + S3

f

S2


Avoidance of DSC violations

H

A B

D E

C

GF

S3

S1S1

1

2

3

1*

2*

3*

S2 + S3

S2 + S3S2

H

A B

D E

C

GF

S3

S1 + S2 + S3

S1

d

1

2

3

1*

2*

3*

S1 + S2

S1 + S2 + S3

f

S2

a

bh

c


Color clash

H

A B

D E

C

GF

S1S1

1

2

3

1*

2*

3*S2

(1, 1*)1

(2, 2*)1

d

H

A B

D E

C

GF

S3

S1S1

1

2

3

1*

2*

3*S2 + S3S2

f

dS2

(3, 3*)2


Power distribution

• In a LDC it is possible to specify combining and dividing ratios• ratios determine how power from sources is distributed to destinations• combining and dividing ratios can be set differently for each waveband

• How should these ratios be chosen?

• The objective could be• to split each source’s power equally among all destinations it reaches• to combine equally all sources arriving at the same destination

• Resultant end-to-end power transfer coefficients are independent of• routing paths through the network• number of nodes they traverse• order in which signals are combined and split

• Coefficients depend only on• number of destinations for each source• number of sources reaching each destination


Illustration of power distribution

1/3

2/31

(1/2)(S1+ S2) a a’

S3 b’ b (1/6) )(S1+ S2)

2/3

h h’

c c’ (2/9) )(S1+ S2)+(1/3) S3

1

1/3


Multipoint subnets in LLNs

• Attempts to set up several point-to-point optical connections within acommon waveband leads to unintentional creation of multipoint paths=> complications in routing, channel assignment and power distribution

• On the other hand, waveband routing leads to more efficient use ofthe optical spectrum

• In addition, the multipoint optical path capability is useful whencreating intentional multipoint optical connections

– LLNs can deliver a high degree of logical connectivity with minimaloptical hardware in the access stations

– this is one of the fundamental advantages of LLNs over WRNs

• Multipoint optical connections can be utilized when creating a fulllogical connectivity among specified clusters of stations within alarger network => such fully connected clusters are calledmultipoint subnets (MPS)


Example - seven stations on a mesh

• Consider a network containing sevenstations interconnected on a LLN witha mesh physical topology and bi-directional fiber links- notation for fiber labeling: a and a´ forma fiber pair with opposite directions

• Set of stations {2,3,4} should beinterconnected to create a MPS withfull logical connectivity

• This can be achieved, e.g. by creatingan optical path on a singlewaveband in the form of a tree joiningthe three stations (embeddedbroadcast star)

2

3

4

2

3

4

LCG

2

3

4

2

3

4

LCH

E

A B

D C

1

6

2

3

4

5

71

6

4

5

2

7ae

f

h

gb´

d c

physical topology


Realization of MPS by a tree embeddedin mesh

g’

3

B

C

D

B

D

2

4

3

2

4

3’

2’

4’

3

2

4

g

f’f

f

g’

c’

3’

f’

g

c

3

3

4

2

CD

B

Optical path

f

gc


Contents

• Static networks• Wavelength Routed Networks (WRN)

• Linear Lightwave Networks (LLN)– Seven-station example

• Logically Routed Networks (LRN)


Seven-station example

• Assume:– nonblocking access stations

– each transmitter runs at a bit rate of R0• Physical topologies (PT):

– bi-directional ring– mesh– multistar of seven physical stars

• Logical topologies (LT):– fully connected (point-to-point logical topology with 42 edges)

- realized using WRN– fully shared (hypernet logical topology with a single hyperedge)

- realized using a broadcast-and-select network (LLN of a single MPS)– partially shared (hypernet of seven hyperedges)

- realized using LLN of seven MPSs


Physical topologies

multistar

D

E

F

G

C

B

A1

2

3

4

5

6

7

ring

7

6

54

2

3

1

A

B

D E

G

C F

mesh

A B

D C

1

6

2

3

4

5

7

E


Fully connected LT - WRN realizations

• Ring PT:– 6 λs with spectrum reuse factor of 42/6 = 7

=> RCA?– 6 transceivers in each NAS

⇒ network capacity = 7*6 = 42 R0• Mesh PT:

– 4 λs with spectrum reuse factor of 42/4 = 10.5=> RCA?

– 6 transceivers in each NAS ⇒ network capacity = 7*6 = 42 R0

• Multistar PT:– 2 λs with spectrum reuse factor of 42/2 = 21

=> RCA?– 6 transceivers in each NAS

⇒ network capacity = 7*6 = 42 R0

1

2

3

4

5

6

7

1

2

3

4

5

6

7

LCG


Fully shared LT - Broadcast and selectnetwork realizations

• Any PT• WDM/WDMA:

– 42 λs with spectrum reuse factor of 1

– 6 transceivers in each NAS ⇒ network capacity = 7*6 = 42 R0

• TDM/T-WDMA in FT-TR mode:– 7 λs with spectrum reuse factor of 1

– 1 transceiver in each NAS ⇒ network capacity = 7*1 = 7 R0

• TDM/TDMA:– 1 λ with spectrum reuse factor of 1

– 1 transceiver in each NAS ⇒ network capacity = 7*1/7 = 1 R0 LCH

1

2

3

4

5

6

7

1

2

3

4

5

6

7

E1


Partially shared LT - LLN realizations

• Note: Full logical connectivity among all stations• Mesh PT using TDM/T-WDMA in FT-TR mode:

– 2 wavebands with spectrum reuse factor of7/2 = 3.5 => RCA?

– 3 λs per waveband– 3 transceivers in each NAS

⇒ network capacity = 7*3 = 21 R0• Multistar PT using TDM/T-WDMA in FT-TR

mode:– 1 waveband with spectrum reuse factor of 7/1 = 7

=> RCA?

– 3 λs per waveband– 3 transceivers in each NAS

⇒ network capacity = 7*3 = 21 R0 LCH

1

2

3

4

5

6

7

1

2

3

4

5

6

7

E1

E2

E3

E4

E5

E6

E7


Contents



Logically Routed Networks (LRN)

• For small networks, high logical connectivity is reasonably achievedby purely optical networks. However, when moving to largernetworks, the transparent optical approach soon reaches its limits.

• For example, to achieve full logical connectivity among 22 stations ona bi-directional ring using wavelength routed point-to-point opticalconnections 21 transceivers are needed in each NAS and totally 61wavelengths. Economically and technologically, this is well beyondcurrent capabilities.=> we must turn to electronics (i.e. logically routed networks)

• Logically routed network (LRN) is a hybrid optical network

– which performs logical switching (by logical switching nodes(LSN)) on top of a transparent optical network

– LSNs create an extra layer of connectivity between the endsystems and NASs


Two approaches to create fullconnectivity

• Multihop networks based on point-to-point logicaltopologies

– realized by WRNs

• Hypernets based on multipoint logical topologies– realized by LLNs


Point-to-point logical topologies

• In a point-to-point logical topology– a hop corresponds to a logical link between two LSNs– maximum throughput is inversely proportional to the average hop count

• One of the objectives of using logical switching on top of atransparent optical network is

– to reduce cost of station equipment (by reducing the number of opticaltransceivers and complexity of optics) while maintaining high networkperformance

• Thus, we are interested in logical topologies that– achieve a small average number of logical hops at a low cost (i.e., small

node degree and simple optical components)

• An example is a ShuffleNet– for example, an eight-node ShuffleNet has 16 logical links and an

average hop count of 2 (if uniform traffic is assumed)– these networks are scalable to large sizes by adding stages and/or

increasing the degree of the nodes


Eight-node ShuffleNet

logical topology

1

2

3

4

1

2

3

4

5

6

7

8

LCG

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8


ShuffleNet embedded in a bi-directionalring WRN

• Bi-directional ring WRN with elementary NASs

– 2 λs with spectrum reuse factor of 16/2 = 8

– 2 transceivers in each NAS

– average hop count = 2 ⇒ network cap. = 8*2/2 = 8 R0

RCA

-- -- -- ---- -- -- ---- -- -- ---- -- -- --1 2 3 4

4321

-- -- 2L 1L2R 1R -- ---- -- 1R 2R1L 2L -- --5 6 7 8

-- -- 2R 1R2L 1L -- ---- -- 1L 2L

1R 2R -- --

8765 -- -- -- --

-- -- -- ---- -- -- ---- -- -- --

1

4

6 7

2

3

5

8

L

R

Note: station labeling!


Details of a ShuffleNet node

L

R

1

λλ1, λλ2

λλ2

λλ1, λλ2

λλ2

λλ1, λλ2

λλ1, λλ2

L

R

1

ONN1

1 256

15

L

R

Fibers between ONN5 and ONN1

1

5

6

5

6

1 1

2 2

OT1 OT2

TP TP

OR1 OR2

RP RP

1

1 2 1 2


Multipoint logical topologies

• High connectivity may be maintained in transparent optical networkswhile economizing on optical resource utilization through the use ofmultipoint connections

• These ideas are even more potent when combined with logicalswitching

• For example, a ShuffleNet may be modified to a Shuffle Hypernet– an 8-node Shuffle Hypernet has 4 hyperarcs– each hyperarc presents a directed MPS that contains 2 transmitting and

2 receiving stations– an embedded directed broadcast star is created to support each MPS– for a directed star, a (physical) tree is found joining all stations in both the

transmitting and receiving sets of the MPS– any node on the tree can be chosen as a root– LDCs on the tree are set to create optical paths from all stations in the

transmitting set to the root node, and paths from the root to all receivingstations


Eight-node Shuffle Hypernet

LCH

1

2

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5

6

7

8

1

2

3

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5

6

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8

E1

E2

E3

E4

transformation

1

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5

6

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E1


Shuffle Hypernet embedded in a bi-directional ring LLN

• Bi-directional ring LLN with elementaryNASs using TDM/T-WDMA in FT-TR mode

– 1 waveband with spectrum reuse factorof 4/1 = 4

– 2 λs per waveband– 1 transceiver in each NAS

⇒ network cap. = 8*1/2 = 4 R0

Note: station and fiber labeling!

1

4

6 7

2

3

5

8

aa´

b

c

d

h

g

f

e4 4´

RCA

a, b´, c´

inboundfibers

E4

E3

E2

E1 ONN5

root

b

outboundfibers

g, a´, h´ ONN2 he, f´, g´ ONN8 f

c, d , e ONN3 d

1

wave-band

11

1


Details of node in Shuffle Hypernet

a

b´

5

w1

w1

w1

w1

w1

ONN5

a´

b

5´w1

Fibers between ONN3 and ONN1

5 163

56

b´

3 1

b a

a´

c

c´

6 6´ 5 5´ 1 1´3 3´

1

OT

TP

OR

RP

...

7, 1 1, 6

7, 2 1, 67, 15, 2

7, 27, 15, 2

5

7 2

1

3

5

6

3, 51, 6

E2

E1


Contents


– Virtual connections: an ATM example


Virtual connections - an ATM example

• Recall the problem of providing full connectivity among five locations– suppose each location contains a number of end systems that

access the network through an ATM switch. The interconnectedswitches form a transport network of 5*4 = 20 VPs.

• The following five designs are now examined and compared:– Stand-alone ATM star– Stand-alone ATM bi-directional ring– ATM over a network of SONET cross-connects– ATM over a WRN– ATM over a LLN

• Traffic demand: each VP requires 600 Mbits/s (≈ STM-4/STS-12)

• Optical resources: λ-channels and transceivers run at the rate of

2.4 Gbits/s (≈ STM-16/STS-48)


Stand-alone ATM networks

4

5

1

2

3

6

ATM switch/cross-connect with transceiver

4

5

1

2

3


Embedded ATM networks

A 1

A 2 A 3

A 5A 4

AA

A A

S

S

S

4

S

51

S

2

S

3

6

A

A ATM switch SDH/SONET DCSS ONN

DCS network Optical network Shared medium

S

4

5

1

2

6

S

A

S

A

S

A

3S

A

SA


Case 1 - Stand-alone ATM star

• Fiber links are connected directly to ports on ATM switches, creating a point-to-point optical connection for each fiber

– each link carries 4 VPs in each direction ⇒ each optical connection needs 2.4Gbits/s, which can be accomodated using a single λ-channel

– one optical transceiver is needed to terminate each end of a link, for a total of 10transceivers in the network

• Processing load is unequal:– end nodes process their own 8 VPs carrying 4.8 Gbits/s

– center node 6 processes all 20 VPs carrying 12.0 Gbits/s ⇒ bottleneck• Inefficient utilization of fibers, since

– even though only one λ-channel is used, the total bandwidth of each fiber isdedicated to this system

• Poor survivability, since– if any link is cut, network is cut in two

– if node 6 fails, the network is completely distroyed


Case 2 - Stand-alone ATM bi-directionalring

• Fiber links are connected directly to ports on ATM switches, creating a point-to-point optical connection for each fiber

– assuming shortest path routing, each link carries 3 VPs in each direction⇒ each optical connection needs 1.8 Gbits/s, which can beaccommodated using a single λ-channel (leaving 25% spare capacity)

– 1 optical transceiver is needed to terminate each end of a link, for a totalof 10 transceivers in the network

• Equal processing load:– each ATM node processes its own 8 VPs and 2 additional transit VPs

carrying an aggregate traffic of 6.0 Gbits/s• Thus,

– no processing bottleneck– the same problem with optical spectrum allocation as in case 1– but better survivability, since network can recover from any single link cut

or node failure by rerouting the traffic


Case 3 - ATM embedded in DCS network

• ATM end nodes access DCSs through 4 electronic ports• Fiber links are now connected to ports on DCSs, creating a point-to-point

optical connection for each fiber– each link carries 4 VPs in each direction => each optical connection

needs 2.4 Gbits/s, which can be accommodated using a single λ-channel– again, 1 optical transceiver is needed to terminate each end of a link

• Processing load is lighter– ATM nodes process their own 8 VPs carrying 4.8 Gbits/s– but it is much simpler to perform VP cross-connect functions at the STM-

4/STS-12 level than at the ATM cell level (as was done in case 1)– a trade-off must be found between optical spectrum utilization and costs

– the more λ-channels on each fiber (to carry “background” traffic), themore (expensive) transceivers are needed

• Survivability and reconfigurability are good– since alternate paths and additional bandwidth exist in the DCS network


Case 4 - ATM embedded in a WRN

• DCSs are now replaced by optical nodes containing WSXCs• Each ATM end node is connected electronically to a NAS• Each VP in the virtual topology must be supported by

– a point-to-point optical connection occupying one λ-channel

– thus, 4 tranceivers are needed in each NAS (and totally 20 transceivers)

– however, no tranceivers are needed in the network nodes• With an optimal routing and wavelength assignment,

– the 20 VPs can be carried using 4 wavelengths (= 800 GHz)

• Processing load is very light– due to optical switching (without optoelectronic conversion at each node)– Note: ATM nodes still process their own 8 VPs carrying 4.8 Gbits/s

• As in case 3, survivability and reconfigurability are good– since alternate paths and additional bandwidth exist in the underlying

WRN


Case 5 - ATM embedded in an LLN

• WSXCs are now replaced by LDCs• A single waveband is assigned to the ATM network, and the LDCs are set to

create an embedded tree (MPS) on that waveband– the 20 VPs are supported by a single hyperedge in the logical topology

– since each λ-channel can carry 4 VPs, 5 λ-channels are needed totally,all in the same waveband (= 200 GHz)

– only 1 transceiver is needed in each NAS (and totally 5 transceivers)using TDM/T-WDMA in FT-TR mode

• Processing load is again very light– due to optical switching (without optoelectronic conversion at each node)– Note: ATM nodes still process their own 8 VPs carrying 4.8 Gbits/s

• As in cases 3 and 4, survivability and reconfigurability are good– since alternate paths and additional bandwidth exist in the underlying LLN


Comparison of ATM network realizations

Case

Opticalspectrum

usage

Number ofoptical

transceivers

Nodeprocessing

load Others

12345

Very highVery highLowestMediumLow

101010205

Very highHighMediumVery lowVery low

Poor survivability-High DCS-Rapid tunability required, optical multi-cast possible

1


Optical switches



Optical switches

• Components and enablingtechnologies

• Contention resolution• Optical switching schemes

2


Components and enabling technologies

• Optical fiber

• Light sources, optical transmitters

• Photodetectors, optical receivers

• Optical amplifiers

• Wavelength converters

• Optical multiplexers and demultiplexers

• Optical add-drop multiplexers

• Optical cross connects

• WDM systems


Optical fiber

• Optical fiber is the most important transport medium for high-speed communications in fixed networks

• Pros– immune to electromagnetic interference– does not corrode– huge bandwidth (25 Tbit/s)

• Cons– connecting fibers requires special techniques (connectors,

specialized personnel to splice and connect fibers)– does not allow tight bending

• An optical fiber consists of– ultrapure silica– mixed with dopants to adjust the refractive index

3


Optical fiber (cont.)• Optical cable consists of several layers

– silica core– cladding, a layer of silica with a different mix of dopants– buffer coating, which absorbs mechanical stresses– coating is covered by a strong material such as Kevlar– outermost is a protective layer of plastic material

Plastic

KevlarTM

Cladding

Buffer coating

Glassy core

Cross section (not to scale)


Optical fiber (cont.)

• Fiber cable consists of a bundle of optical fibers, up to 432 fibers.• Refractive index profile of a fiber is carefully controlled during

manufacturing phase

• Typical refractive index profiles

– step index profile

– graded index profile

Core fiberCladding

Step indexprofilen1

n2

n(x)

n2

x

Graded indexprofilen1

n2

n(x)

n2

x ∆∆

4



• Light beams are confined in the fiber- by total reflection at the core-cladding interface in step-index fibers- by more gradual refraction in graded index fibers

n2

n1 Step index

Graded index



• Fiber can be designed to support• several propagation modes => multimode fiber• just a single propagation mode => single-mode fiber

Multimode fiber(many directional rays)

Core fiberncore

Claddingnclad

d = 50 µµm

D = 125 ±± 2 µµm

Single-mode fiber(one directional rays due to small d/D ratio)

Claddingnclad

d = 8.6 - 9.5 µµm

D = 125 ±± 2 µµm

5



• Multimode graded index fiber• small delay spread

• 1% index difference between core and cladding amounts to1-5 ns/km delay spread

• easy to splice and to couple light into it

• bit rate limited up to 100 Mbit/s for lengths up to 40 km• fiber span without amplification is limited

• Single mode fiber• almost eliminates delay spread

• more difficult to splice and to exactly align two fibers together

• suitable for transmitting modulated signals at 40 Gbit/s or higherand up to 200 km without amplification


Optical fiber characteristics• Dispersion is an undesirable phenomenon in optical fibers

• causes an initially narrow light pulse to spread out as itpropagates along the fiber

• There are different causes for dispersion• modal dispersion• chromatic dispersion

• Modal dispersion• occurs in multimode fibers• caused by different (lengths) propagation paths of different modes

• Chromatic dispersion• material properties of fiber, such as dielectric constant and

propagation constant, depend on the frequency of the light• each individual wavelength of a pulse travels at different speed

and arrives at the end of the fiber at different time

6


Optical fiber characteristics (cont.)

• Chromatic dispersion (cont.)• dispersion is measured in ps/(nm*km), i.e. delay per wavelength

variation and fiber length• Dispersion depends on the wavelength

• at some wavelength dispersion may be zero

• in conventional single mode fiber this typically occurs at 1.3 µm- below, dispersion is negative, above it is positive

• For long-haul transmission, single mode fibers with specializedindex of refraction profiles have been manufactured

• dispersion-shifted fiber (DSF)

• zero-dispersion point is shifted to 1.55 µm



• Fiber attenuation is the most important transmission characteristic

• limits the maximum span a light signal can be transmittedwithout amplification

• Fiber attenuation is caused by light scattering on

• fluctuations of the refractive index• imperfections of the fiber

• impurities (metal ions and OH radicals have a particular effect)

• A conventional single-mode fiber has two low attenuation ranges

• one at about 1.3 µm

• another at about 1.55 µm

7



• Between these ranges is a high attenuation range(1.35-1.45 µm), with a peak at 1.39 µm, due to OH radical

• special fibers almost free of OH radicals have beenmanufactured

• such fibers increase the usable bandwidth by 50%

• the whole range from 1.335 µm to 1.625 µm is usable, allowingabout 500 WDM channels at 100 GHz channel spacing



• The attenuation is measured in dB/km; typical values are• 0.4 dB/km at 1.31 µm

• 0.2 dB/km at 1.55 µm

• for comparison, attenuation in ordinary clear glass is about 1dB/cm = 105 dB/km

Zero-dispersion line

λλ (µµm)

Absorption due to OH-(peak at 1385 nm)

Without OH-Transmittedoptical loss orattenuation (dB)

1.2 1.4 1.6

8


Light sources and opticaltransmitters

• One of the key components in optical communications is themonochromatic (narrow band) light source

• Desirable properties• compact, monochromatic, stable and long lasting

• Light source may be one of the following types:• continuous wave (CW); emits at a constant power; needs an

external modulator to carry information

• modulated light; no external modulator is necessary

• Two most popular light sources are

• light emitting diode (LED)

• semiconductor laser


Light emitting diode (LED)

• LED is a monolithically integrated p-n semiconductor diode

• Emits light when voltage is applied across its two terminals

• In the active junction area, electrons in the conduction band andholes in the valence band are injected

• Recombination of the electron with holes releases energy in theform of light

• Can be used either as a CW light source or modulated light source(modulated by the injection current)

Terminal

P-type

ActivejunctionN-type

Terminal

Emittedlight

9


Characteristics of LED

• Relatively slow - modulation rate < 1 Gbit/s

• Bandwidth depends on the material - relatively wide spectrum• Amplitude and spectrum depend on temperature

• Low cost

• Transmits light in wide cone - suitable for multimode fibers

1.0

0.5

0.0

45 oC

50 oC

Relativeintensity

As temperature rises,spectrum shifts andintensity decreases

λλ (nm)~690 ~ 700


Semiconductor laser

• LASER (Light amplification by stimulated emission of radiation)

• Semiconductor laser is also known as laser diode and injectionlaser

• Operation of a laser is the same as for any other oscillator - gain(amplification) and feedback

• As a device semiconductor laser is similar to a LED (i.e. p-nsemiconductor diode)

• A difference is that the ends of the active junction area are carefullycleaved and act as partially reflecting mirrors

• this provides feedback• The junction area acts as a resonating cavity for certain frequencies

(those for which the round-trip distance is multiple of the wavelengthin the material - constructive interference)

10


Semiconductor laser (cont.)

• Light fed back by mirrors is amplified by stimulatedemission

• Lasing is achieved above a threshold currentwhere the optical gain is sufficient toovercome losses (including thetransmitted light) from the cavity

p n+ -

i

Cleavedsurface

Cleavedsurface



• Cavity of a Fabry-Perot laser can support many modes of oscillation=> it is a multimode laser

• In single frequency operation, all but a single longitudinal mode mustbe suppressed - this can be achieved by different approaches:

• cleaved-coupled cavity (C3) lasers

• external cavity lasers• distributed Bragg reflector (DBR)

lasers

• distributed feedback (DFB) lasers

• The most common light sourcesfor high-bit rate, long-distance

• transmission are the DBR andDFB lasers.

Activelayer

p p p n

ΛΛ

Guidinglayer

Activelayer

Diffractiongratings

p p n

11



• Laser tunability is important for multiwavelength network applications

• Slow tunability (on ms time scale) is required for setting upconnections in wavelength or waveband routed networks

• achieved over a range of 1 nm via temperature control

• Rapid tunability (on ns-µs time scale) is required for TDM-WDMmultiple access applications

• achieved in DBR and DFB lasers by changing the refractiveindex, e.g. by changing the injected current in grating area

• Another approach to rapid tunability is to use multiwavelength laserarrays

• one or more lasers in the array can be activated at a time



• Lasers are modulated either directly or externally

• direct modulation by varying the injection current

• external modulation by an external device, e.g. Mach-Zehnderinterferometer

0

VLight input Ii Modulated light Io

Mach-Zehnder interferometer

12


Photodetectors and opticalreceivers

• A photodetector converts the optical signal to a photocurrent that isthen electronically amplified (front-end amplifier)

• In a direct detection receiver, only the intensity of the incoming signalis detected

• in contrast to coherent detection, where the phase of the opticalsignal is also relevant

• coherent systems are still in research phase• Photodetectors used in optical transmission systems are

semiconductor photodiodes

• Operation is essentially reverse of a semiconductor optical amplifier• junction is reverse biased• in absence of optical signal only a small minority carrier current is

flowing (dark current)


Photodetectors and opticalreceivers (cont.)

• Operation is essentially reverse of a semiconductor optical amplifier(cont.)

• a photon impinging on surface of a device can be absorbed by anelectron in the valence band, transferring the electron to theconduction band

• each excited electron contributes to the photocurrent

• PIN photodiodes (p-type, intrinsic, n-type)

• An extra layer of intrinsic semiconductor material is sandwichedbetween the p and n regions

• Improves the responsivity of the device

• captures most of the light in the depletion region

13


Photodetectors and opticalreceivers (cont.)

• Avalanche photodiodes (APD)

• In a photodiode, only one electron-hole pair is produced by anabsorbed photon

• This may not be sufficient when the optical power is very low

• The APD resembles a PIN

• an extra gain layer is inserted between the i (intrinsic) and nlayers

• a large voltage is applied across the gain layer

• photoelectrons are accelerated to sufficient speeds

• produce additional electrons by collisions => avalanche effect

• largely improved responsivity


Optical amplifiers

• Optical signal propagating in a fiber suffers attenuation

• Optical power level of a signal must be periodically conditioned

• Optical amplifiers are key components in long haul optical systems

• An optical amplifier is characterized by

• gain - ratio of output power to input power (in dB)• gain efficiency - gain as a function of input power (dB/mW)• gain bandwidth - range of frequencies over which the amplifier

is effective• gain saturation - maximum output power, beyond which no

amplification is reached• noise - undesired signal due to physical processes in the

amplifier

14


Optical amplifiers (cont.)

• Types of amplifiers• Electro-optic regenerators

• Semiconductor optical amplifiers (SOA)• Erbium-doped fiber amplifiers (EDFA)


Electro-optic regenerators

• Optical signal is• received and transformed to an electronic signal

• amplified in electronic domain

• converted back to optical signal at the same wavelength

λλ O/E Amp E/O λλFiber Fiber

Photonic domain

Optical receiver Optical transmitter

Photonic domainElectronic domain

O/E - Optical to ElectronicE/O - Electronic to OpticalAmp - Amplifier

15


Semiconductor optical amplifiers(SOA)

• Structure of SOA is similar to that of a semiconductor laser

• It consists of an active medium (p-n junction) in the form ofwaveguide - usually made of InGaAs or InGaAsP

• Energy is provided by injecting electric current over the junction

OA

Current pump

Weak input signal Amplified output signal

AR AR

Fiber Fiber


Semiconductor optical amplifiers(cont.)

• SOAs are small, compact and can be integrated with othersemiconductor and optical components

• They have large bandwidth and relatively high gain (20 dB)

• Saturation power in the range of 5-10 dBm

• SOAs are polarization dependent and thus require a polarization-maintaining fiber

• Because of nonlinear phenomena SOAs have a high noise figureand high cross-talk level

16


Erbium-doped fiber amplifiers(EDFA)

• EDFA is a very attractive amplifier type in optical communicationssystems

• EDFA is a fiber segment, a few meters long, heavily doped witherbium (a rare earth metal)

• Energy is provided by a pump laser beam

EDFAWeak signal in

Fiber

Amplified signal out

IsolatorIsolatorFiberFiber

Pump(980 or 1480 nm at 3 W)


Erbium-doped fiber amplifiers(cont.)

• Amplification is achieved by quantum mechanical phenomenon ofstimulated emission

• erbium atoms are excited to a high energy level by pump laser signal• they fall to a lower metastable (long-lived, 10 ms) state

• an arriving photon triggers (stimulates) a transition to the ground leveland another photon of the same wavelength is emitted

Excited erbium atoms at high energy level

Erbium atoms at low energy level

Longer wavelenghtsource (1480 nm)

Short- wavelenghtsource (980 nm)

~1 µµs

Stimulated emission(1520 - 1620 nm)

Atoms at metastableenergy (~10 ms)

17


Erbium-doped fiber amplifiers(cont.)

• EDFAs have a high pump power utilization (> 50 %).

• Directly and simultaneously amplify a wide wavelength band (> 80nm in the region 1550 nm) with a relatively flat gain

• Flatness of gain can be improved with gain-flattening optical filters

• Gain in excess of 50 dB• Saturation power is as high as 37 dBm

• Low noise figure

• Transparent to optical modulation format

• Polarization independent

• Suitable for long-haul applications• EDFAs are not small and cannot easily be integrated with other

semiconductor devices


Wavelength converters

Wavelength converters• Enable optical channels to be relocated

• Achieved in optical domain by employing nonlinear phenomena

Types of wavelength converters• Optoelectronic approach

• Optical gating - cross-gain modulation

• Four-wave mixing

18


Wavelength converters -optoelectronic approach

• Simplest approach

• Input signal is• received

• converted to electronic form

• regenerated

• transmitted using a laser at a different wavelength.

Receiver Regenerator Transmitterλλs λλp


Optical gating -cross-gain modulation

• Makes use of the dependence of the gain of a SOA (semiconductoroptical amplifier) on its input power

• Gain saturation occurs when high opticalpower is injected

• carrier concentration is depleted

• gain is reduced

• Fast• can handle 10 Gbit/s rates

SOA

Signal λλsSignal λλp

Filter λλp

Probe λλp

SignalCarrierdensity

Gain

Sprobeoutput

Time

19


Four-wave mixing

• Four-wave mixing is usually an undesirable phenomenon in fibers

• Can be exploited to achieve wavelength conversion

• In four-wave mixing, three waves at frequencies f1, f2 and f3 producea wave at the frequency f1 + f2 - f3

• When• f1 = fs (signal)

• f2 = f3 = fp (pump)=> a new wave is produces at 2fp - fs

• Four-wave mixing can be enhanced by using SOA to increase thepower levels

• Other wavelengths are filtered out


Four-wave mixing (cont.)

SOA Filterfs fp

2fs-

f p f s f p2f

p- f s 2fp- fs

2fp- fs

20


Optical multiplexers anddemultiplexers

• An optical multiplexer receives many wavelengths from many fibersand converges them into one beam that is coupled into a single fiber

• An optical demultiplexer receives a beam (consisting of multipleoptical frequencies) from a fiber and separates it into its frequencycomponents, which are directed to separate fibers (a fiber for eachfrequency)

Optical multiplexer

λλ1

λλ2

λλN

...

λλ1 ,λλ2 , …,λλN

Optical demultiplexer

λλ2

λλN

...

λλ1

λλ1 ,λλ2 , …,λλN


Prisms and diffraction gratings

• Prisms and diffraction gratings can be used to achieve these functionsin either direction (reciprocity)

• in both of these devices a polychromatic parallel beam impingingon the surface is separated into frequency components leaving thedevice at different angles

• based on different refraction (prism) or diffraction (diffractiongrating) of different wavelengths

Fibers

λλ1+ λλ2+ ...+λλN

λλ1

λλ2

λλN

...

Multiplexed beam

Lens

Fibers


λλ1

λλ2

λλN

...

Diffractiongrating

Lens

Diffractedwavelenghts

Incident beam

21


Prisms and diffraction gratings(cont.)


Multiplexed beam

Fiber Lens Prism Lens

λλ1λλ2

λλN

λλ3...

n2

n1


Multiplexed beamλλ1

λλ2

λλN

λλ3...

n2

n1


Arrayed waveguide grating (AWG)

• AWGs are integrated devices based on the principle of interferometry• a multiplicity of wavelengths are coupled to an array of waveguides

with different lengths• produces wavelength dependent phase shifts• in the second cavity the phase difference of each wavelengths

interferes in such a manner that each wavelength contributesmaximally at one of the output fibers

• Reported systems• SiO2 AWG for 128 channels with 250 GHz channel spacing• InP AWG for 64 channels with 50 GHz channel spacing


λλ1

λλN

...

w1

wN

Array of waveguides

Array of fibersS2S1

22


Optical add-drop multiplexers(OADM)

• Optical multiplexers and demultiplexers are components designed forwavelength division (WDM) systems

• multiplexer combines several optical signals at differentwavelengths into a single fiber

• demultiplexer separates a multiplicity of wavelengths in a fiber anddirects them to many fibers

• The optical add-drop multiplexer• selectively removes (drops) a wavelength from the multiplex• then adds the same wavelength, but with different data

λλ1, λλ2, ... ,λλN λλ1, λλ2, ... ,λλN

OADM

λλ2, ... ,λλN

λλ1 λλ1


Optical add-drop multiplexers (cont.)

• An OADM may be realized by doing full demultiplexing andmultiplexing of the wavelengths

• a demultiplexed wavelength path can be terminated and a newone created

OA OAλλ1, λλ2, ... ,λλN λλ1, λλ2, ... ,λλN

OADMλλ1, λλ2, ... ,λλN-1

λλN λλN

23


Optical cross-connects

• Channel cross-connecting is a key function in communication systems

• Optical cross-connection may be accomplished by• hybrid approach: converting optical signal to electronic domain, using

electronic cross-connects, and converting signal back to optical domain• all-optical switching: cross-connecting directly in the photonic domain

• Hybrid approach is currently more popular because the all-opticalswitching technology is not fully developed

• all optical NxN cross-connects are feasible for N = 2…32

• large cross-connects ( N ∼1000) are in experimental or planning phase

• All-optical cross-connecting can be achieved by• optical solid-state devices (couplers)• electromechanical mirror-based free space optical switching devices


Solid-state cross-connects

• Based on semiconductor directional couplers

• Directional coupler can change optical property of the path• polarization• propagation constant• absorption index• refraction

• Optical property may be changed by means of• heat, light, mechanical pressure• current injection, electric field

• Technology determines the switching speed, for instance• LiNbO3 crystals: order of ns• SiO2 crystals: order of ms

Signal in Signal “on”

Signal “off”

Propagation constantcontrol (voltage)

Lightguide

24


Solid-state cross-connects (cont.)

• A multiport switch, also called a star coupler, is constructed byemploying several 2x2 directional couplers

• For instance, a 4x4 switch can be constructed from six 2x2 directionalcouplers

• Due to cumulative losses, the number of couplers in the path is limitedand, therefore, also the number of ports is limited, perhaps to 32x32

2x2

2x2

12

34

2x2

2x2

2x2

2x2

12

34

WaveguideControl

Substrate


Microelectromechanical switches(MEMS)

• Tiny mirrors micromachined on a substrate• outgrowth of semiconductor processing technologies: deposition,

etching, lithography• a highly polished flat plate (mirror) is connected with an electrical

actuator• cab be tilted in different directions by applied voltage

R.J. Bates, Optical switching and networking handbook, McGraw-Hill, 2001

25


Optical cross connects

• MEMS technology is still complex and expensive.

• Many MEMS devices may be manufactured on the same wafer• reduces cost per system

• Many mirrors can be integrated on the same chip• arranged in an array• experimental systems with 16x16=256 mirrors have been built• each mirror may be independently tilted

• An all-optical space switch can beconstructed using mirror arrays

R.J. Bates, Optical switching and networking handbook, McGraw-Hill, 2001


Optical switches

• Components and enabling technologies

• Contention resolution• Optical switching schemes

26


Contention resolution

• Contention occurs when two or more packets aredestined to same output at the same time instant

• In electronic switches, contention solved usually bystore-and-forward techniques

• In optical switches, contention resolved by– optical buffering (optical delay lines)– deflection routing– exploiting wavelength domain

• scattered wavelength path (SCWP)• shared wavelength path (SHWP)


Optical delay loop

mT

. . . . . .

. . .

. . .

T

2T

In_1In_2

In_n

Out_1

Out_2

Out_n

27


Deflection routing

. . . . . .

In_1In_2

In_n

Out_1Out_2

Out_n

Out_3Out_4

In_3In_4


Wavelength conversion

. . . . . .

In_1In_2

In_n

Out_1Out_2

Out_n

Out_3Out_4

In_3In_4

λλ1

λλ1 λλ2

λλ3

28


Optical switches

• Components and enabling technologies• Contention resolution

• Optical switching schemes


Optical packet switching

• User data transmitted in optical packets– packet length fixed or variable

• Packets switched in optical domain packet-by-packet• No optical-to-electrical (and reverse) conversions for

user data

• Switching utilizes TDM and/or WDM

• Electronic switch control

• Different solutions suggested– broadcast-and-select– wavelength routing– optical burst switching

29


Optical packet switch

• packet delineation• packet alignment• header and payload separation• header information processing• header removal

• switching of packets frominputs to correct outputsin optical domain

• contention resolution

• header insertion• optical signalregeneration

Inputinterfaces

Switchfabric

Outputinterfaces

Switchcontrol

Headerrewrite

Sync.control

. . .

. . .

. . .

. . .


Broadcast-and-select

• Input ports support different wavelengths (e.g. onlyone wavelength/port)

• Data packets from all input ports combined andbroadcasted to all output ports

• Each output port selects dynamically wavelengths, i.e.packets, addressed to it

• Inherent support for multi-casting• Requires that control unit has received

routing/connection information before packets arrive

30


Broadcast-and-select

In_1

In_2

In_n

. . .

TWC/FWCC

OM

BIN

ER

. . .

. . .

1

k

Out_1

Out_n

Wavelength encoding Buffering Wavelength selection

TWC - Tunable Wavelength ConverterFWC - Fixed Wavelength Converter


Wavelength routing

• Input ports usually support the same set of wavelengths• Incoming wavelengths arrive to “contention resolution and buffering”

block, where the wavelengths are– converted to other wavelenths (used inside the switch)– demultiplexed– routed to delay loops of parallel output port logics

• Contetion free wavelengths of the parallel output port logics arecombined and directed to “wavelength switching” block

• Wavelength switching block converts internally routed λ-channels towavelengths used in output links and routes these wavelengths tocorrect output ports

• Correct operation of the switch requires that control unit has receivedrouting/connection information before packets arrive

31


Wavelength routing

In_1

. . .

TWC

. . .

. . .

1

k

Out_1

Out_n

Contention resolution and buffering Wavelength switching

In_nTWC

1

k

. . .

. .. .

TWC

TWC

TWC - Tunable Wavelength Converter


Optical burst switching

• Data transmitted in bursts of packets

• Control packet precedes transmission of a burst and isused to reserve network resources

– no acknowledgment, e.g. TAG (Tell-and-Go)– acknowledgment, e.g. TAW (Tell-and-Wait)

• High bandwidth utilization (lower avg. processing andsynchronization overhead than in pure packetswitching)

• QoS and multicasting enabled

32


Header and packet formats

• In electronic networks, packet headers transmittedserially with the payload (at the same bit rate)

• In optical networks, bandwidth is much larger andelectronic header inspection cannot be done at wirespeed

• Header cannot be transmitted serially with the payload• Different approaches for optical packet format

– packets switched with sub-carrier multiplexed headers

– header and payload transmitted in different λ-channels– header transmitted ahead of payload in the same λ-channel

– tag (λ) switching - a short fixed length label containing routinginformation


Fiber

λλ1

λλ2

Payload

Header Sub-carrier

Header and packet formats (cont.)

Packets with sub-carrierheaders

Fiberλλ1

λλ2Header

PayloadHeader and payload indifferent λ-channels

Header transmittedahead of payload inthe same λ-channel

Fiberλλ1

λλ2

Payload Header

Payload Header

33


Example optical packet format(KEOPS)

Head

er s

ynch

.pa

ttern

Rout

ing

tag

Payl

oad

Payl

oad

sync

h.pa

ttern

Gua

rd ti

me

Gua

rd ti

me

Gua

rd ti

me

Time slot


Research issues in optical switching

• Switch fabric interconnection architectures• Packet coding techniques

(bit serial, bit parallel, out-of-band)• Optical packets structure (fixed vs. variable length)

• Packet header processing and insertion techniques• Contention resolution techniques• Optical buffering (delay lines, etc.)• Reduction of protocol layers between IP and fiber• Routing and resource allocation (e.g. GMPLS, RSVP-TE)• Component research (e.g. MEMS)