orange coast college business division computer science department cs 116- computer architecture the...

Orange Coast CollegeBusiness Division

Computer Science Department

CS 116- Computer Architecture

The Processor: Datapath & Control

OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 2OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers)

Processor Design Step 3• Assemble Datapath Meeting Requirements

– Build the data path by adding up the components required to execute each instruction

– We need to consider:• Register transfer requirements • Instruction fetch• Read operands and execute operation

– We are going to consider one instruction format at a time and then combine what we have after each step


Processor Design Step 3-a• Instruction Fetch Unit

– Common to all instruction types

– Actions taken:• Fetch the instruction

from Memory: mem[PC]

• Update program counter:– Sequential Code:

PC <- PC + 4 – Branch and Jump:

PC <- branch address

PC

Instruction Memory

Read Address

4

Adder


Consider R-Type instructions• R-Format Instructions:

– Arithmetic instructions– Logic instructions

• Main actions:– Read 2 registers– Perform an ALU operation– Write result to destination

op rs rt rd shamt funct061116212631

6 bits 6 bits5 bits5 bits5 bits5 bits


R-Type: What do we need?• To read data from a register we need

– 2-inputs to register file specifying register to be read

– 2-outputs from register file will carry the values read • Remember output is always available to whatever

register# given, therefore no control signal is needed

• To write data to a register we need– 1-input to register file with register# to write into– 1-data input will carry the data to be written – Write control signal that enables data to be written


Datapath for R-Format Instructions• Main components:

Register file

RegWrite

Writeregister

Readdata 1

Readdata 2

Readregister 1Readregister 2

Writedata

5

5

5ALU Operation

ALUresult

ALUZero

3


R-Type Datapath• Datapath for Add & Subtract Instructions

R[rd] R[rs] ± R[rt] – Example:

add rd, rs, rt– The register selection lines come from register

fields– Control signals are from the control logic after

decoding the instruction • Opcode + funct


Now, consider the I-Type• Load & Store

R[rt] Mem[R[rs] + SignExt[imm16]] R[rt] Mem[R[rs] + SignExt[imm16]]

– Main actions:• Sign-extend offset• Add to contents of base register to calculate address• Load from or store into the calculated address

– We need a sign-extend unit for offset

11op rs rt/rd? offset

016212631

6 bits 16 bits5 bits5 bits

offset016 1531

16 bits16 bitssign-extended 16-bits


Datapath for I-Format instructions:• Immediate arithmetic operations

R[rt] R[rs] op SignExt[imm16]– Main actions:

• Sign extend immediate operand• Perform operation• Store result

– We need a “sign-extend” unit for immediate operand

11op rs rt/rd? offset

016212631


offset016 1531

16 bits16 bitssign-extended 16-bits


Datapath for I-Format instructions:• Immediate logical operations

R[rt] R[rs] op ZeroExt[imm16]– Main actions:

• Zero extend immediate operand• Perform operation• Store result

– We need a “zero-extend” unit for immediate operand

11op rs rt/rd? immediate

016212631


immediate016 1531

16 bits16 bits0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Load - The Details• Use offset in 16 immediate operand bits • Value read from memory must be written into

register fileR[rt] <- Mem[R[rs] + SignExt[imm16]]

• Example: lw rt, rs, imm16lw $t1, offset($t2) #$t2 = Base register

op rs rt immediate6 bits 5 bits 5 bits 16 bit

31 26 21 16 0


Store- The Details• Use offset in 16 immediate operand bits • Value to be stored read from register file

Mem[ R[rs] + SignExt[imm16] ] <- R[rt]• Example:

sw rt, rs, imm16sw $t1, offset($t2) #$t2 = Base register

op rs rt immediate6 bits 5 bits 5 bits 16 bit

31 26 21 16 0


Load & Store- What do we need?• Actions:

– Register access– Memory address calculation– Read/Write from memory– Write into register (for load)

• What do we need?– Sign-extend unit– Data memory unit to read/ or write– Both write & read control signals


Implementation of Load & Store

RegWrite

RegisterFileWrteregister

Readdata 1

Readdata 2


Wrtedata

5

5

5ALU Operation

ALUALUresut

Zero

3

16 32Signextend MemRead

MemWrite

Wr i t edata

Readdata

Address

Instruction

Data Memory


Combining Datapath components• A single datapath can be assembled

– From previous datapaths by adding multiplexors • One MUX at ALU input to read

– Either data bus – Or sign extended word

• One at the data input to the register file that – Takes the data from ALU – Or from data memory


Putting it all Together

Instruction

16 32

RegistersWriteregister

Readdata 1

Readdata 2


DatamemoryWritedata

Readdata MuxMuxWritedata

Signextend

ALUresultZero

ALUAddress

RegWrite

ALU operation3

MemRead

MemWriteALUSrc MemtoReg


Combining Datapath components• Add in the instruction fetch

PC

Instructionmemory

Readaddress

Instruction

16 32

Registers

WriteregisterWritedata

Readdata 1Read

data 2


Signextend

ALUresultZero

Datamemory

Address

Writedata

Readdata Mux

4Add

Mux

ALU

RegWrite

ALU operation3

MemRead

MemWrite

ALUSrcMemtoReg


Datapath for Branching (I-Format)• Datapath For Branch Instructions (I-Format)

beq $t1, $t2, offset• Steps:

– Compute branch target address– Compare register contents– Determine next instruction based on comparison

• In MIPS, branches are delayed– Instruction following the branch is always

executed• Independent of the branch condition– If branch condition is true, backtrack– Helps in speeding up (See pipelining)


Branching- The details• Step1: Compute branch target address

– Branch target address = PC + sign-extended offset field

– HW needed:• sign-extension unit• Adder

– Notes:• Offset could be positive or negative• Offset field is “Word offset”

– Shift offset left 2 bits (multiply by 4) to get byte offset• Branch offset based on instruction following branch

– i.e from PC +4


Branching- The details• Step2: Compare register contents

– Hardware needed:• Register file to get register contents• ALU to perform comparison

– By subtraction


Branching- The details• Step3: Determine next instruction

– Depends on the result of comparison– If condition is true:

• Branch is taken – If condition is false

• Branch is not taken

– Hardware needed:• ALU:

– Zero signal from ALU if the result is zero indicating the condition is true


Branching- The details• Step 4: Modify instruction fetch datapath

– If branch is taken • PC Branch target address

– If branch not taken• PC PC +4

– Hardware needed• Adder


The Branching Datapath

RegWrite

Read Reg1

5

5

ALU Control

ALUZero

3

16 32

AddSum

Shiftleft 2 Branch

target

To branch control logicInstruction

PC +4 from instruction datapath

Read Reg2Write Reg

Write data

Register File

Read Data1

Read Data2

Sign exten

d


Finally, the J-typej target

• Unconditional jump – Requires no comparison

• Target is “Word target”– Target needs shifting 2 bits to the left – Original target 26 bits– Target after shifting 28 bits

• Target need to be loaded into PC– The lower 28 bits of PC are replaced with target

• Hardware needed:– Concatenating “00” unit

2 target 6 bits 26 bits


The Combined Datapath• 1 clock cycle for each operation

– Load/store, ALU operations, Branches

PC

Instructionmemory

Readaddress

Instruction

32

Add ALUresult

Mux

Registers

WriteregisterWritedata

Readdata 1Readdata 2


Shiftleft 2

4

Mux

ALU operation3

RegWrite

MemRead

MemWrite

PC Src

ALUSrc MemtoRegALUresultZero

ALU

Datamemory

Address

Writedata

Readdata Mux

Signextend

Add

16


Critical Path for Load• Total time needed =

PC’s change time+ Instruction Memory’s Access Time+ Register File’s Access Time+ ALU to Perform a 32-bit Add+ Data Memory Access Time+ Setup Time for Register File Write+ Clock Skew


Assemble Control Logic• Control Unit

– Analyze implementation of each instruction to determine setting of control points

Instruction<31:0>Inst

Memory

Address

Control

<21:25><16:20>

<11:15>

<0:15>

<21:25>

Imm16RdRsRtOp Fun

ALUctr

RegDst ALUSrcExtOp MemtoRegMemWr EqualnPC_sel RegWr

DATA PATH


What control signals do we need?• Register selection:

– Rs, Rt, Rd and Imed16 hardwired into datapath• Operation selection:

– nPC_sel: 0 => PC <– PC + 4;1 => PC <– PC + 4 + SignExt(Im16) || 00

• Extension 16-bit control– ExtOp: “zero”, “sign”

• ALU data source – Register or immediate address– ALUsrc: 0 => regB; 1 => immed


What control signals do we need?• ALU Operation selection (control)

– ALUctr: “add”, “sub”, “or”• Memory Write:

– MemWr• MemtoReg:

– 1 => Mem• RegDst:

– 0 => “rt”; 1 => “rd”• RegWr:

– write dest register


Control Signals for each instructioninst Register TransferADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4

ALUsrc=RegB, ALUctrl=“add”, RegDst=rd, RegWr, nPC_sel=“+4”

SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4ALUsrc=RegB, ALUctr=“sub”, RegDst=rd, RegWr, nPC_sel=“+4”

ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4ALUsrc=Im, Extop=“Z”, ALUctr=“or”,RegDst=rt, RegWr, nPC_sel=“+4”


Control Signals for each instructioninst Register TransferLOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4

ALUsrc = Im, Extop = “Sn”, ALUctr = “add”,MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4”

STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rs]; PC <– PC + 4 ALUsrc=Im, Extop=“Sn”, ALUctr=“add”, MemWr, nPC_sel=“+4”

BEQ if (R[rs]== R[rt]) then PC<– PC+sign_ext(Imm16)] || 00 else PC <– PC + 4nPC_sel = EQUAL, ALUctr = “sub”


Assemble each signal

nPC_sel <= if (OP==BEQ) then EQUAL else 0

ALUsrc <= if (OP==“000000”) then “regB” else “immed”

ALUctr <= if (OP==“000000”) then functelseif (OP==ORi) then “OR”

elseif (OP==BEQ) then “SUB” else “ADD”


Assemble each signal

ExtOp <= if (OP == ORi) then “zero” else “sign”

MemWr <= (OP == Store)MemtoReg <= (OP == Load)

RegWr: <= if ((OP== Store) || (OP==BEQ)) then 0 else 1

RegDst: <= if ((OP==Load) || (OP==ORi))then 0 else 1


Datapath with Control Unit

MemReg

MemRead

MemWrite

ALUOp

ALUSrc

RegDst

PC

Instruction memory

Read addressInstruction

(31-0)Instruction [20–16]

Instruction [25–21]

Add

Instruction [5–0]

RegWrite4

16 32Instruction [15–0]0

Register file

Writedata

Read reg1

Sign exten

d

ALUresultZero

Datamemory

Address Readdata Mux

1

0

Mux

1

0

Mux

1

0

Mux

1

Instruction [15–11]

ALU Contr

ol

Shiftleft 2

PCSrc

ALU

Add ALUresult

Read reg2WriteregWrite data

Read data1Read data2


Summary• 5 steps to design a processor

1. Analyze instruction set => datapath requirements2. Select set of datapath components & establish

clock methodology3. Assemble datapath meeting the requirements4. Analyze implementation of each instruction to

determine setting of control points that effects the register transfer.

5. Assemble the control logic


Summary•MIPS makes it easier

–Instructions are all the same size–Source registers are always in same place in the

instruction–Immediate operands are the same size & in the

same location–Operations are always on either register contents or

immediate operands•Single cycle datapath

=> CPI=1


The Control Unit• Functions:

– Select operations to be performed (ALU, read/write, etc.)

– Control data flow (multiplexor inputs) • Major components:

– ALU control• Operation based on instruction type and function code

– Other controls• Input:

– Information comes from the 32 bits of the instruction • Output:

– Control signals

Control Unit

Instruction code

Control Signals


Quick review: MIPS Instruction Formats

op target address0 2631

6 bits 26 bits

op rs rt rd shamt funct0 6 11 16 21 2631

6 bits 6 bits5 bits5 bits5 bits5 bits

rsop rt immediate0 16 21 2631


R-type

I-type

J-type


ALU Control• ALU has 3 control inputs

– Allows 8-combinations• Only 5 combinations are used.

– The rest could be used as don’t-care in minimization000 AND001 OR010 add110 subtract111 set-on-less-than


ALU Control• Remember:

– ALU is needed for all instruction categories• lw/sw(I-Format): Compute memory address• Arithmetic/logic(R-Format): Arithmetic / logic

operation• Branch(beq)(I-Format): Subtract registers

– We need to find ALU control signals from the information in the instruction

1111010100x2a0SLL1101000100x220SUB0101000000x200ADD0011001010x250OR0001001000x240AND

ALUControl

Funct-Binary

Funct-field0x

Op-fieldInstruction


ALU Control• ALU performs one of 5 instructions based on

instruction class• ALUOp:

– A 2-bit input control used with the “funct” field • Determines 3-bit combination to control the ALU

ALUOp Control

6-bit “funct feld”

2-bit “ALUOp” input00 Add(for load & store)01 Subtract (for beq)10 Depends on code in funct field

3-bit “ALU operation”000 and001 or010 add110 sub111 slt


How ALU control bits are set• (ALUOp = 00 or 01 )

– Depend on “op” field & not on “funct” field• (ALUOp code = 10 )

– Depend on “funct” field to set the ALU control input

InstructionOpcode ALUOp

Instructionoperation Funct field

Desired ALUaction

ALU controlinput

lw 00 load word XXXXXX add 010sw 00 store word XXXXXX add 010Branch equal 01 branch equal XXXXXX subtract 110R-type 10 add 100000 add 010R-type 10 subtract 100010 subtract 110R-type 10 AND 100100 and 000R-type 10 OR 100101 or 001R-type 10 set on less than 101010 set on less than 111

1

2

1

2


ALU Control• Multiple level of decoding is used

1. The main control unit generates the ALUOp bits2. ALUOp bits are used as input to ALU control3. ALU control generates the actual signal to ALU unit

• Why use multiple levels?– Reduce size of main control unit– Increase speed of control unit


ALU Control: Truth Table

• 8-input lines, 3 output lines– Actual table size should be 28 = (256)– Only relevant combinations are listed

• Details in (Appendix C2, p. C4)• F5 & F4 are always don’t cares

– F3-F0 only are considered

ALUOp Funct field Operation InstructionALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0

0 0 X X X X X X 010 lw/swX 1 X X X X X X 110 beq1 X X X 0 0 0 0 010 add1 X X X 0 0 1 0 110 sub1 X X X 0 1 0 0 000 and1 X X X 0 1 0 1 001 or1 X X X 1 0 1 0 111 sll


ALU Control: Logic Circuit• Details in Appendix C2, p. C4• Based on “funct” code & ALUOp

Operation2ALU operation(Control signals)

F3F2F1F0

F (5– 0)

ALUOp0

ALUOpALU Control Circuit Diagram

3

2

5

ALUOp1

Operation1

Operation0

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